High quality atomic-layer-deposited ultrathin Si-nitride gate dielectrics with low density of interface and bulk traps

Abstract

Interface trap and bulk trap densities of atomic-layer-deposited (ALD) Si-nitride dielectrics have been evaluated by bipolar-voltage-pulse-induced current and electrical-stress-induced leakage-current measurements, respectively. In comparison with the conventional SiO2 dielectrics, significantly lower (∼1/3) interface trap density near the conduction band edge is observed in the ALD Si-nitride dielectrics. Moreover, the observed lower interface and bulk trap generations consistently explain the soft-breakdown-free phenomena observed in capacitors with the ALD Si-nitride gate dielectrics. Enhanced dielectric reliability and several other significant features have made the ALD Si-nitride gate dielectrics a front line candidate for extremely thin (equivalent oxide thickness ∼1 nm) gate dielectrics of sub-100-nm technology nodes.