Thin-film Transistor Structure Research Articles

Circular Structure for High Mechanical Bending Stability of a-IGZO TFTs

We employ a circular (Corbino) thin-film transistor (TFT) structure, in which the outer-ring is the drain and the inner-ring is the source, to improve the stability of amorphous–indium–gallium–zinc–oxide TFTs under tensile bending strain. We attribute the stability improvement to a more uniform electric field distribution across the circular channel, as it is isolated from local electric field crowding at sharp corners or channel edges. In addition, the effect of strain-induced increase in channel charge concentration is small in Corbino TFTs, owing to the larger outer-ring electrode, which depletes more electrons than the drain of rectangular TFTs. Furthermore, the circular shape results in bending direction independence, which is very important in multi-TFT circuits, where TFT orientation varies with position.

Comprehensive review on the development of high mobility in oxide thin film transistors

Oxide materials are one of the most advanced key technology in the thin film transistors (TFTs) for the high-end of device applications. Amorphous oxide semiconductors (AOSs) have leading technique for flat panel display (FPD), active matrix organic light emitting display (AMOLED) and active matrix liquid crystal display (AMLCD) due to their excellent electrical characteristics, such as field effect mobility (μ FE ), subthreshold swing (S.S) and threshold voltage (V th ). Covalent semiconductor like amorphous silicon (a-Si) is attributed to the anti-bonding and bonding states of Si hybridized orbitals. However, AOSs have not grain boundary and excellent performances originated from the unique characteristics of AOS which is the direct orbital overlap between s orbitals of neighboring metal cations. High mobility oxide TFTs have gained attractive attention during the last few years and today in display industries. It is progressively developed to increase the mobility either by exploring various oxide semiconductors or by adopting new TFT structures. Mobility of oxide thin film transistor has been rapidly increased from single digit to higher than 100 cm2/V·s in a decade. In this review, we discuss on the comprehensive review on the mobility of oxide TFTs in a decade and propose bandgap engineering and novel structure to enhance the electrical characteristics of oxide TFTs.

Robust SiO2 gate dielectric thin films prepared through plasma-enhanced atomic layer deposition involving di-sopropylamino silane (DIPAS) and oxygen plasma: Application to amorphous oxide thin film transistors

DIPAS (di-isopropylamino silane, H3Si[N(C3H7)2]) and O2 plasma were employed, using plasma-enhanced atomic layer deposition (PEALD), to deposit silicon oxide to function as the gate dielectric at low temperature, i.e., below 200°C. The superior amorphous SiO2 thin films were deposited through the self-limiting reactions of atomic layer deposition with a deposition rate of 0.135nm/cycle between 125 and 200°C. PEALD-based SiO2 thin layer films were applied to amorphous oxide thin film transistors constructed from amorphous In-Ga-Zn-O (IGZO) oxide layers, which functioned as channel layers in the bottom-gated thin film transistor (TFT) structure, with the aim of fabricating transparent electronics. The SiO2 gate dielectric exhibited the highest TFT performance through the fabrication of heavily doped n-type Si substrates, with a saturation mobility of 16.42cm2/V·s, threshold voltage of 2.95V and large on/off current ratio of 3.69 × 108. Ultimately, the highly doped Si was combined with the ALD-based SiO2 gate dielectric layers, leading to a saturation mobility of 16.42cm2/V·s, threshold voltage of 2.95V, S-slope of 0.1944, and on/off current ratio of 3.69 × 108. Semi-transparent and transparent TFTs were fabricated and provided saturation mobilities of 22.18 and 24.29cm2/V·s, threshold voltages of 4.18 and 2.17V, S-slopes of 0.1944 and 0.1945, and on/off current ratios of 9.63 × 108 and 1.03 × 107, respectively.

Impact of repeated uniaxial mechanical strain on flexible a-IGZO thin film transistors with symmetric and asymmetric structures

This letter investigates repeated uniaxial mechanical stress-induced degradation behavior in flexible amorphous In-Ga-Zn-O thin-film transistors (TFTs) of different geometric structures. Two types of via-contact structure TFTs are investigated: symmetrical and UI structure (TFTs with I- and U-shaped asymmetric electrodes). After repeated mechanical stress, I-V curves for the symmetrical structure show a significant negative threshold voltage (VT) shift, due to mechanical stress-induced oxygen vacancy generation. However, degradation in the UI structure TFTs after stress is a negative VT shift along with the parasitic transistor characteristic in the forward-operation mode, with this hump not evident in the reverse-operation mode. This asymmetrical degradation is clarified by the mechanical strain simulation of the UI TFTs.

The effect of device electrode geometry on performance after hot-carrier stress in amorphous In-Ga-Zn-O thin film transistors with different via-contact structures

In this letter, the effects of hot carriers on amorphous In-Ga-Zn-O thin film transistors (TFTs) of different geometric structures were investigated. Three types of via-contact structure TFTs are used in this experiment, defined as source-drain large (SD large), source-drain normal (SD normal), and fork-shaped. After hot-carrier stress, the I-V curves of both SD normal and fork-shaped TFTs with U-shaped drains show a threshold voltage shift along with the parasitic transistor characteristic in the reverse-operation mode. Asymmetrical degradation is exhibited in an ISE-TCAD simulation of the electric field, which shows the distribution of hot electrons injected into the etch-stop layer below the redundant drain electrode.

Systematic Decomposition of the Positive Bias Stress Instability in Self-Aligned Coplanar InGaZnO Thin-Film Transistors

We propose an experimental method to decompose the positive gate-bias stress (PBS)-induced threshold voltage shift ( $\Delta {V}_{\mathsf {th}})$ of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) into the contributions of distinct degradation mechanisms. Top-gate self-aligned coplanar structure TFTs are used for this letter. Stress-time-divided measurements, which combine the subgap density-of-states (DOS) extraction and the analysis on recovery characteristics, are performed to separate the $\Delta {V}_{\mathsf {th}}$ components. Change in excess oxygen ( $\text{O}_{\mathsf {ex}})$ -related DOS is clearly observed, and $\Delta {V}_{\mathsf {th}}$ by PBS is quantitatively decomposed into the contributions of the active $\text{O}_{\mathsf {ex}}$ , and the deep and shallow gate insulator traps. The quantitative decomposition of PBS-induced $\Delta {V}_{\mathsf {th}}$ provides physical insight and key guidelines for PBS stability optimization of a-IGZO TFTs.

Silicon and Dopant Ink-Based CMOS TFTs on Flexible Steel Foils

ABSTRACTPolysilicon complementary metal oxide semiconductor (CMOS) thin film transistors (TFTs) are fabricated on large area, flexible stainless steel foils using novel ink depositions within a hybrid printed/conventional process flow. A self-aligned top gate TFT structure is realized with an additive materials approach to substitute the use of high capital cost ion implantation and lithography processes. Polyhydrosilane-based silicon ink is coated and laser crystallized to form the polysilicon channel. Semiconductor grade P-type and N-type unique dopant ink formulations are screen printed and combined with thermal drive in and activation to form self-aligned doped source and drain regions. A high refractory top gate material is chosen for its process compatibility with printed dopants, chemical resistance, and work function. Steel foil substrates are fully encapsulated to allow for high temperature processing. The resultant materials set and process flow enables TFT electrical characteristics with NMOS and PMOS mobilities exceeding 120 cm2/Vs and 60 cm2/Vs, respectively. On/Off ratios are >107. Reproducibility, uniformity, and reliability data in a production environmental is shown to demonstrate high volume, high throughput manufacturability. The device characteristics and scheme enable NFC (13.56MHz) capable circuits for use in flexible NFC and display-based smart labels and packaging.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (∼17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (∼87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH−1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Role of deposition and annealing of the top gate dielectric in a-IGZO TFT-based dual-gate ion-sensitive field-effect transistors

The deposition of the top gate dielectric in thin film transistor (TFT)-based dual-gate ion-sensitive field-effect transistors (DG ISFETs) is critical, and expected not to affect the bottom gate TFT characteristics, while providing a higher pH sensitive surface and efficient capacitive coupling between the gates. Amorphous Ta2O5, in addition to having good sensing properties, possesses a high dielectric constant of ∼25 making it well suited as the top gate dielectric in a DG ISFET by providing higher capacitive coupling (ratio of Ctop/Cbottom) leading to higher amplification. To avoid damage of the a-IGZO channel reported to be caused by plasma exposure, deposition of Ta2O5 by e-beam evaporation followed by annealing was investigated in this work to obtain sensitivity over the Nernst limit. The deteriorated bottom gate TFT characteristics, indicated by an increase in the channel conductance, confirmed that plasma exposure is not the sole contributor to the changes. Oxygen vacancies at the Ta2O5/a-IGZO interface, which emerged during processing, increased the channel conductivity, became filled by optimum annealing in oxygen at 400 °C for 1 h, which was confirmed by an x-ray photoelectron spectroscopy depth profiling analysis. The obtained pH sensitivity of the TFT-based DG ISFET was 402 mV pH−1, which is about 6.8 times the Nernst limit (59 mV pH−1). The concept of capacitive coupling was also demonstrated by simulating an a-IGZO-based DG TFT structure. Here, the exposure of the top gate dielectric to the electrolyte without applying any top gate bias led to changes in the measured threshold voltage of the bottom gate TFT, and this obviated the requirement of a reference electrode needed in conventional ISFETs and other reported DG ISFETs. These devices, with high sensitivities and requiring low volumes (∼2 μl) of analyte solution, could be potential candidates for utilization as chemical sensors and biosensors.

A Thin-Film Transistor With High Drain Current Induced by a Trap-Assisted Electric Double Layer

A thin-film transistor (TFT) structure is proposed, where high current operation at low gate voltage is obtained through creation of an electric double layer at the semiconductor/insulator interface. For an n-type transistor, the dipole layer consists of electrons accumulated in the channel and holes trapped in the insulator close to the interface. The dipole layer results in high gate capacitance even with larger insulator thicknesses resulting in low voltage operation. To enable charge/discharge of traps, the insulator is replaced by a semiinsulating layer that allows moderate amounts of gate current to flow; 2-D device simulation results are presented to illustrate and validate the proposed transistor concept. Evidence of trap assisted creation of higher gate capacitance and drain current are provided through experimental measurements on amorphous In-Ga-Zn-O TFTs with e-beam evaporated SiO2 gate dielectric.

Electrical and optical characteristics of aerosol assisted CVD grown ZnO based thin film diode and transistor

The prospect of developing thin film diodes (TFDs) and thin film transistors (TFTs) by using indigenously developed aerosol assisted chemical vapor deposition system is reported in this paper. Optical, structural, elemental and current (I) - voltage (V) characterization of fabricated structures manifest distinctly the properties of both TFT and TFT. UV-VIS spectroscopy shows that the average transmittance of single and multilayer thin films range between 80 and 95% implying that highly transparent deposition can be achieved. X-ray photoelectron spectroscopy manifest the deposition of ZnO, Al:ZnO and Al2O3 thin films. X-ray diffraction of the films confirm the polycrystalline type of deposition. I-V characteristics of In/n-ZnO/n+-Al:ZnO/In bi-layer structure suggests the fabrication of a TFD. Linear dependency of barrier height (BH) and exponential decrease of ideality factor of fabricated TFD with increasing temperature are observed. Modified Richardson plot is used to measure the inhomogeneity in BH and Richardson constant of In/n-ZnO/n+-Al:ZnO/In TFD. Transfer and output characteristics of the present TFT structure is found to be in agreement with those for a p-channel TFT system. The threshold voltage, saturation field effect mobility, subthreshold swing and current on/off ratio of the TFT were measured as 2.2 V, 24.3 cm2 V-1 s−1, 0.23 V/decade and 36, respectively.

Single-Walled Carbon-Nanotubes-Based Organic Memory Structures.

The electrical behaviour of organic memory structures, based on single-walled carbon-nanotubes (SWCNTs), metal–insulator–semiconductor (MIS) and thin film transistor (TFT) structures, using poly(methyl methacrylate) (PMMA) as the gate dielectric, are reported. The drain and source electrodes were fabricated by evaporating 50 nm gold, and the gate electrode was made from 50 nm-evaporated aluminium on a clean glass substrate. Thin films of SWCNTs, embedded within the insulating layer, were used as the floating gate. SWCNTs-based memory devices exhibited clear hysteresis in their electrical characteristics (capacitance–voltage (C–V) for MIS structures, as well as output and transfer characteristics for transistors). Both structures were shown to produce reliable and large memory windows by virtue of high capacity and reduced charge leakage. The hysteresis in the output and transfer characteristics, the shifts in the threshold voltage of the transfer characteristics, and the flat-band voltage shift in the MIS structures were attributed to the charging and discharging of the SWCNTs floating gate. Under an appropriate gate bias (1 s pulses), the floating gate is charged and discharged, resulting in significant threshold voltage shifts. Pulses as low as 1 V resulted in clear write and erase states.

Vertical Oxide Thin-Film Transistor with Solution-Processed Channel Define Layer

High performance thin-film transistor (TFT) is essential for the next-generation display. Especially, scale-downed TFT becomes very important to develop high resolution display. The vertical-channel TFTs (V-TFTs) attracts lots of interests from the view point of minimizing pixel size because V-TFTs have very small footprint compared to the lateral TFT. V-TFTs provide the smallest pixel size without the limitation of channel length. [1] In addition, V-TFTs could show high strain stress stability due to the small channel size formed vertically when they are adapted in flexible display. Channel length of V-TFTs is controlled by the thickness of spacer placed between source and drain. Since the main purpose of adoption of V-TFTs is to increase the current driving ability, typical channel length of V-TFT is shorter than 1 um (~0.5 um). The length of channel in vertical TFT, however, should be adjustable according to the TFT applications. The major method to deposit spacer which determine the channel length (channel define layer) is vacuum process such as plasma-enhanced chemical vapor deposition (PECVD). Such vacuum process could provide high film performance, quality and good uniformity. Nonetheless, vacuum process has disadvantage in the deposition of spacer with thick thickness because of very long process time. In contrast, solution-process coating is easy and fast method. By controlling coating speed and time, solution process provides thick films uniformly. Furthermore, solution process can be applied using both of organic and inorganic materials. While inorganic materials result in films with low defects, the space processed with organic materials yields low stress, making this suitable for the flexible vertical TFTs. In this study, we fabricate vertical TFT with spacers deposited with various materials such as organic and inorganic by solution-process coating. We also investigate back-channel effect and TFT strain stress depending on the kinds of spacer materials. We select three different types of materials for the spacer; SiO2, PI, carbon based organic material. Solution-processed SiO2 film have dielectric constant of 4.27 and similar film quality with PECVD SiO2. The solution-processed films show very low leakage current of 1.35x10-9A/cm-2at 0.1MV/cm. Carbon based organic material also has low dielectric constant and is approximately 1um~3um thick. We studied the effect of back-channel according to various spacer materials. Instead of V-TFTs, top gate staggered TFTs were fabricated to mimic the structure of V-TFT because both TFTs have same process sequence. Figure 1(a) shows the schematic structure of top-gate TFT. The various buffer layers corresponding to the spacer in V-TFT were deposited by solution processes. The TFT with solution-processed film did not show degradation of electrical characteristics in comparison to that with PECVD SiO2. After confirming the feasibility of solution-processed spacer for the vertical TFT, three types of solution-processed layer are applied to actual vertical TFT as a spacer. The patterned source ITO electrode was coated with solution processed spacer, followed by the deposition of drain electrode. Drain and spacer were patterned with spacer mask. In sequence, active, gate insulator and gate are deposited and patterned at once. We will report the performance of V-TFTs with solution processed spacer in terms of mobility, stability, and thermal stability. Figure 1. (a) Schematic diagram of top-gate TFT, (b) Schematic structure of vertical TFT with solution processed spacer Acknowledgements This work was supported by 'The Cross-Ministry Giga KOREA Project' grant from the Ministry of Science, ICT and Future Planning, Korea [GK15D0100].

Crack-guided effect on dynamic mechanical stress for foldable low temperature polycrystalline silicon thin film transistors

In the thin film transistors (TFTs) device research for foldable display, the degradation effect by the mechanical stress is crucial. Here, the crack position is critical for TFT reliability. However, it is difficult to characterize the crack position due to the random generation of the crack by mechanical stress. In this paper, the crack-guided low temperature polycrystalline silicon (LTPS) TFT test structures are fabricated and the crack-guided effects on mechanical stress of the tested TFT structure are analyzed. To strain on the foldable LTPS TFTs, 50,000cycles of tensile and parallel direction dynamic mechanical stresses were applied with 2.5-mm bending radius. Based on the results, the generating crack position can be guided and controlled and also TFT reliability for foldable display can be enhanced.

Multilevel Resistive-Change Memory Operation of Al-Doped ZnO Thin-Film Transistor

A multilevel resistive-change memory device with thin-film transistor (TFT) structure is proposed, in which both functions of transistor and nonvolatile memory can be performed. Al-doped ZnO was employed for the active channel of the TFT as well as for the resistive-change material of the memory device. Multilevel memory operations could be realized by controlling the number of conducting filaments within the channel. Sound TFT characteristics and nonvolatile memory functions were demonstrated. The programmed current ratios for three-level memory states were 1:3.8:25. As results, long-time stability ( $10^{4}$ s) and program endurance (100 cycles) for the three-level memory states were also confirmed.

Back-Channel Electrolyte-Gated a-IGZO Dual-Gate Thin-Film Transistor for Enhancement of pH Sensitivity Over Nernst Limit

A dual-gate amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) was studied to obtain a pH sensitivity of $\sim 160$ mV/pH, which is above Nernst limit (59 mV/pH) with a low value of operating voltage (−5 to 5 V). The utilization of the active layer itself as the sensitive surface constitutes the dual-gate TFT structure with the back-channel gated with the electrolyte. The TFT characteristics were optimized by annealing the IGZO film in varying temperatures in oxygen ambience. A double-layered a-IGZO was used to sandwich the source/drain electrodes to eliminate the issues related with the high contact resistance and critical passivation of source/drain electrodes to protect from the exposure of the electrolyte. The single-gate electrolyte-gated thin film transistor showed the pH sensitivity of 24 mV/pH, which was enhanced by 6.7-fold by its dual-gate operation. The operation of dual-gate TFT ion-sensitive field-effect transistors (ISFETs) with varying only bottom gate voltage eliminates the requirement of a reference electrode necessary in single-gate ISFETs. Such dual-gate ISFETs obviate the need of an additional high- $K$ dielectric needed for the dual-gate TFT ISFETs and could also be fabricated on flexible substrates. These structures with the high sensitivity of $\sim 160$ mV/pH and requiring low ( $\sim 2~\mu \text{L}$ ) analyte solution could be the potential candidates for utilization as chemical and bio-sensors.

Rational Design of ZnO:H/ZnO Bilayer Structure for High-Performance Thin-Film Transistors.

The intriguing properties of zinc oxide-based semiconductors are being extensively studied as they are attractive alternatives to current silicon-based semiconductors for applications in transparent and flexible electronics. Although they have promising properties, significant improvements on performance and electrical reliability of ZnO-based thin film transistors (TFTs) should be achieved before they can be applied widely in practical applications. This work demonstrates a rational and elegant design of TFT, composed of poly crystalline ZnO:H/ZnO bilayer structure without using other metal elements for doping. The field-effect mobility and gate bias stability of the bilayer structured devices have been improved. In this device structure, the hydrogenated ultrathin ZnO:H active layer (∼3 nm) could provide suitable carrier concentration and decrease the interface trap density, while thick pure-ZnO layer could control channel conductance. Based on this novel structure, a high field-effect mobility of 42.6 cm(2) V(-1) s(-1), a high on/off current ratio of 10(8) and a small subthreshold swing of 0.13 V dec(-1) have been achieved. Additionally, the bias stress stability of the bilayer structured devices is enhanced compared to the simple single channel layer ZnO device. These results suggest that the bilayer ZnO:H/ZnO TFTs have a great potential for low-cost thin-film electronics.

High-Performance Photo-Modulated Thin-Film Transistor Based on Quantum dots/Reduced Graphene Oxide Fragment-Decorated ZnO Nanowires.

In this paper, a photo-modulated transistor based on the thin-film transistor structure was fabricated on the flexible substrate by spin-coating and magnetron sputtering. A novel hybrid material that composed of CdSe quantum dots and reduced graphene oxide (RGO) fragment-decorated ZnO nanowires was synthesized to overcome the narrow optical sensitive waveband and enhance the photo-responsivity. Due to the enrichment of the interface and heterostructure by RGO fragments being utilized, the photo-responsivity of the transistor was improved to 2000 A W−1 and the photo-sensitive wavelength was extended from ultraviolet to visible. In addition, a positive back-gate voltage was employed to reduce the Schottky barrier width of RGO fragments and ZnO nanowires. As a result, the amount of carriers was increased by 10 folds via the modulation of back-gate voltage. With these inherent properties, such as integrated circuit capability and wide optical sensitive waveband, the transistor will manifest great potential in the future applications in photodetectors.

Critical role of silk fibroin secondary structure on the dielectric performances of organic thin-film transistors

Correlation between silk fibroin (SF) secondary structure and dielectric performances of organic thin-film transistors (OTFTs) was investigated using various SF films.

A Current-Induced Channel Organic Thin-Film Transistor

An organic thin-film transistor structure is proposed in which a channel is created through formation of an electric dipole layer at the semiconductor–insulator interface. The dipole is composed of mobile carriers, electrons, and holes and results from the modification of gate insulator to allow controlled amounts of gate current to flow in the ON-state. 2-D device simulations are used to show that the proposed structure offers the potential for obtaining significantly higher channel charge and current without requiring higher voltages. It is also shown that these advantages come while maintaining OFF-current and unity gain frequency comparable with conventional transistors.