Thin-film Transistors Parameters Research Articles

Zinc tin oxide thin film transistor: Effect on channel isolation and channel width

The n-channel field-effect thin-film transistors (TFTs) with amorphous zinc tin oxide as an active layer has been investigated. The transparent ZTO thin films deposited at room temperature using rf magnetron sputtering have an optical bandgap of 3.3 eV. Before the fabrication of TFT postdeposition annealing of the film was carried out 300°C for 1 hour. The channel layer on Si/SiO2 substrate was deposited in two different structures, isolating each device from the neighboring devices and without isolation. The isolation of active material improves TFT performance by reducing the gate leakage current and parasitic bias stress. The on-off ratio and subthreshold swing were significantly changed from 2.3x103 and 0.73 V/dec to 2.55x106 and 0.23 V/dec respectively on isolation. The effect of channel width on the TFT parameters such as saturated mobility, subthreshold swing and threshold voltage are also studied. The threshold voltage decreases with increasing channel width but mobility and subthreshold swing are relatively constant. The threshold voltage decreased from 19 V to 11 V when the channel width increased. It may be due to the increasing parasitic resistance between the source/drain contacts and the ZTO channel layer.

Influence of structural defects in solution-processed InZnO semiconductors on the electrical stability of thin-film transistors

In this study, we investigate the morphological effect of solution-processed indium-zinc-oxide (InZnO) active layers on the electrical stability of InZnO thin-film transistors (TFTs). We first observe that in the spin-coating method, precursor agglomerates and aggregates remain on the substrates after spin coating an InZnO solution at a low spin speed, thereby causing particle-type morphological defects in the InZnO films. The morphological defects are proven to degrade the basic performance parameters of the InZnO TFTs, including the electrical current level, field-effect mobility, and threshold voltage. In addition, devices having morphological defects show a relatively large hysteresis in transfer characteristics compared to those without defects. In a test of the electrical stability over time, we determine that particle-type morphological defects cause a rapid increase in the conductivity of the InZnO films, which affects the variations in the saturation drain current and the threshold voltage.

(Invited) Stability under Gate Bias Stressing of Amorphous Oxide Thin Film Transistors

Amorphous oxide semiconductors (AOSs) are highly transparent, wide band gap materials with high electron mobility (>= 10 cm2 V–1 s–1), which are suitable for channel layers in thin film transistors (TFTs).1 With the emergence of these materials as the alternative to the incumbent a-Si:H for large area electronics and displays,2 understanding of the stability of these devices becomes vitally important. Stability studies have been reported for the leading AOS material, amorphous indium gallium zinc oxide (a-IGZO) and others such as amorphous zinc tin oxide (a-ZTO), indium zinc oxide and polycrystalline zinc oxide. Various methods such as illumination, gate or drain bias stressing, gate pulsing and constant current stressing have been reported. The deposition technology, choice of gate dielectrics, use of passivation and operation environment can also affect the device stability, as previously reported in a comprehensive review.3 Here, we focus on gate bias stressing – namely positive bias stress (PBS) and negative bias illumination stress (NBIS). We review different experiments and the models used to analyse the threshold voltage (Vth ) shift arising from bias stressing. In particular, the oxygen vacancy migration model that is proposed for the Vth shift in a-IGZO TFTs is discussed and contrasted with the defect creation model used for a-Si:H TFTs.4-6 We will compare the stability under PBS of a-IGZO TFTs with a-ZTO TFTs. These films are deposited by remote-plasma reactive sputtering. Staggered bottom gate architecture TFT are produced using thermal SiO2 as gate dielectric. Typical TFTs operate in enhancement mode with field effect mobility > 10 cm2 V–1 s–1, switching ratio of ~108 and a sub-threshold slope of ~ 0.6 V dec–1. TFTs were subjected to a gate bias stress field of 1MV cm-1 over the initial threshold field and IDS was measured as a function of time up to 80,000 s at temperatures between 65 and 105 °C. The time and temperature dependence of the Vth shift was analysed using the thermalization energy concept, which allows two parameters with some physical interpretation to be extracted: a measure of the energy barrier to the Vth shift process and an associated attempt-to-escape frequency. The extracted parameters of oxide TFTs are also compared to those of a-Si:H TFTs. This work is funded by the Engineering and Physical Sciences Research Council (EP/M013650/1). References 1 K. Nomura, Nature 432 (2004). 2 J. K. Jeong, J. H. Jeong, J. H. Choi, J. S. Im, S. H. Kim, H. W. Yang, K. N. Kang, K. S. Kim, T. K. Ahn, H.-J. Chung, M. Kim, B. S. Gu, J.-S. Park, Y.-G. Mo, H. D. Kim, and H. K. Chung, SID Symposium Digest of Technical Papers 39, 1 (2008). 3 J. F. Conley, in Instabilities in oxide semiconductor transparent thin film transistors, 2009, p. 50. 4 A. J. Flewitt and M. J. Powell, Journal of Applied Physics 115, 134501 (2014). 5 S. C. Deane, R. B. Wehrspohn, and M. J. Powell, Physical Review B 58, 12625 (1998). 6 K. M. Niang, P. M. C. Barquinha, R. F. P. Martins, B. Cobb, M. J. Powell, and A. J. Flewitt, Applied Physics Letters 108, 093505 (2016).

Influence of Carrier Concentration at Front- and Back-Channel on Transfer Characteristics of Bottom-Gate Ιn-Ga-Zn-O Thin-Film Transistors

High drain current (I DS) is required for thin-film transistors (TFTs) to drive next-generation high-definition and large-screen flat panel displays (FPDs). An In-Ga-Zn-O (IGZO) TFT has received considerable attention for the next-generation FPDs because it has high electron mobility (µ >10 cm2V-1s-1) and large area uniformity [1]. Previously, we reported that the I DS and an apparent field-effect mobility (µ FE) of IGZO TFT was enhanced owing to a reduction of an effective channel length (L eff) when the sheet carrier concentration (N s) at back-channel interface increased [2]. However, it has not clarified the influence of carrier concentration at either front- or back-channel on transfer characteristics of the IGZO TFT. In this research, an influence of N s at front- and back-channel on transfer characteristics of bottom-gate IGZO TFT was analysed by device simulator (ATLAS). First, physical parameters of the IGZO TFT was defined to reproduce the transfer characteristics of actual fabricated TFT which was used as reference [3] (denoted hereafter as ref.-TFT). Next, a thin layer, that was modulated the N s from 6.8×1011 to 2.5×1014 cm-2, was set at the back-channel region of the TFT as shown in Fig.1 (a) (denoted hereafter as MD-TFTs). Fig.1 (b) shows the comparison of transfer characteristics of the TFTs. From Fig.1 (b), the I DS of MD-TFTs drastically increased as compared with the ref.-TFT. In addition, it can be seen that the I DS enhancement was increased with increasing N s at back-channel. From these I DS enhancement, an apparent µ FE calculated from transfer characteristics enhanced for the MD-TFTs as shown in Fig1 (c). For the case of the N s was 6.8×1011 cm-2, an apparent µ FE was increased to 29.8 cm2V-1s-1 for sub-threshold region, whereas an apparent µ FE was almost the same as ref.-TFT at on (V GS=+20 V) region. When the N s further increased to 2.5×1013 cm-2, the overestimation of an apparent µ FE was observed for both sub-threshold and on (V GS=+20 V) region. To investigate the reason for changing apparent µ FE of MD-TFT with 6.8×1011 cm-2 with gate-voltage, current density in MD-TFT with N s of 6.8×1011 cm-2 was simulated as shown Figs.2 (a) and 2 (b). In case of sub-threshold region (V GS=+3 V), the L eff at front-channel interface drastically reduce as compared with the mask-defined channel length (L m). On the other hand, the L eff at the on (V GS=+20 V) region was unchanged to the L m. As a consequence of reduction of the L eff, it was increased to apparent µ FE of MD-TFT with 6.8×1011 cm-2 at the sub-threshold region. These results suggested that N s difference between back- and front-channel interfaces are strongly related to the carrier transport mechanism in MD-TFTs, because the carrier transport path was changed by increasing N s at front-channel with gate-voltage. As a results of further analysis by device simulator, it was revealed that the enhancement of I DS and an apparent µ FE were induced owing to the difference of N s between back- and front-channel interfaces. Detail of the results will be presented at the conference. [1] T. Kamiya, K. Nomura and H. Hosono, “Present status of amorphous In-Ga-Zn-O thin-film transistors” Sci. Technol. Adv. Mater, Vol.11, pp.044305-044328, Sept. 2010. [2] D. Koretomo, T. Toda, D. Wang and M.Furuta, “Anomalous Increase of Field-Effect Mobility in In-Ga-Zn-O Thin-Film Transistors Caused by Dry-Etching Damage Through Etching-Stopper” presented at 35-4, 15th Int. Conf. IMID, 2015.[3] Mutsumi Kimura, “Practical Guidance of Parameter Extraction for Device Simulation of Thin-Film Transistors”, J. Appl. Phys., vol.51, pp.054302-1-054302-5, April 2012 Figure 1

Electrical Characterization of Flexible InGaZnO Transistors and 8-b Transponder Chip Down to a Bending Radius of 2 mm

In this paper, we present the fabrication and characterization of highly flexible indium-gallium-zinc-oxide (IGZO)-based thin-film transistors (TFTs) and integrated circuits on a transparent and thin polymer substrate. Mechanical reliability tests are performed under bending conditions down to a bending radius of 2 mm. All the TFT parameters show only a weak dependence on mechanical strain. TFTs can withstand bending strain up to 0.75% without any significant change in the device operation. Mechanical reliability is further demonstrated to a higher TFT integration level by ring oscillators and 8-b transponder chips operating at a bending radius of 2 mm.

Effect of indium low doping in ZnO based TFTs on electrical parameters and bias stress stability

Some applications of thin film transistors (TFTs) need the bottom-gate architecture and unpassivated channel backside. We propose a simple routine to fabricate indium doped ZnO-based TFT with satisfactory characteristics and acceptable stability against a bias stress in ambient room air. To this end, a channel layer of 15 nm in thickness was deposited on cold substrate by DC reactive magnetron co-sputtering of metal Zn-In target. It is demonstrated that the increase of In concentration in ZnO matrix up to 5% leads to negative threshold voltage (VT) shift and an increase of field effect mobility (μ) and a decrease of subthreshold swing (SS). When dopant concentration reaches the upper level of 5% the best TFT parameters are achieved such as VT = 3.6 V, μ = 15.2 cm2/V s, SS = 0.5 V/dec. The TFTs operate in enhancement mode exhibiting high turn on/turn off current ratio more than 106. It is shown that the oxidative post-fabrication annealing at 250oC in pure oxygen and next ageing in dry air for several hours provide highly stable operational characteristics under negative and positive bias stresses despite open channel backside. A possible cause of this effect is discussed.

Six‐Fold Mobility Improvement of Indium‐Zinc Oxide Thin‐Film Transistors Using a Simple Water Treatment

DOI: 10.1002/aelm.201500014 Figure 1 a shows the process-fl ow for the fabrication of IZO TFTs. The TFTs with IZO fi lms that were immersed in DIW prior to fi nal crystallization at 250 °C are henceforth referred to as DIW-treated IZO TFTs and the TFTs with IZO fi lms that were not immersed in DIW are henceforth referred to as untreated IZO TFTs. Figure 1 b shows the schematic of the device structure and Figure 1 c shows the top-view image of an actual device obtained by a 3D optical surface profi ler (NewView 7300, Zygo). The output characteristics of the untreated and DIW-treated IZO TFTs are shown in Figure 1 d,e, respectively. Transfer characteristics of the untreated and DIW-treated IZO TFTs are shown in Figure 1 f. All TFTs work in a low operating voltage range due to the spin coated AlO x dielectric having high capacitance of ca. 151 nF cm −2 measured at 1 Hz (Figure S1, Supporting Information). Untreated IZO TFTs exhibited an average μ FE of ~8.6 ± 0.9 cm 2 V −1 s −1 with a drain on-current to off-current ratio ( I on / I off ) in the range of 10 4 –10 5 . Interestingly, DIW-treated IZO TFTs exhibited higher I on / I off (>10 6 ) with a maximum peak μ FE of ca. 51 ± 5 cm 2 V −1 s −1 , which is six times higher than the untreated IZO TFTs. The dual sweep of the transfer curve showed a very negligible hysteresis with a voltage difference of ca. 0.02 V between the forward and backward sweep (Figure S2, Supporting Information). No signifi cant difference in μ FE of the TFTs was observed with varying channel width to length ratio (W/L) from 5 to 10 (W = 500 μm, L = 100, 75, and 50 μm). The average sub-threshold swing ( SS ) value of untreated and DIW-treated IZO TFTs was found to be 0.189 ± 0.016 V dec −1 and 0.102 ± 0.012 V dec −1 , respectively. Reproducibility of the IZO TFTs with similar performance was checked with repeated experiments. The statistics of the TFT parameters obtained from different experiments is listed in Table S1, Supporting Information, and the corresponding transfer curves are shown in Figure S3, Supporting Information. These results represent the highest fi eld-effect mobility among the solution-processed TFTs using patterned metal oxide channel layers. Positive gate-bias stress (PBS) and negative gate-bias stress (NBS) stability tests were carried out, especially for the DIWtreated IZO TFT and the PBS results are shown in the left panel of Figure 1 g. A bias voltage of +/−1 V was applied to the gate terminal of the TFT during PBS/NBS while the drain and source voltage was fi xed as 0 V. Parallel shifting of the transfer curves was observed in the positive direction with increasing PBS duration. A maximum threshold voltage shift of +0.3 V was observed after 100 s of stress and no signifi cant threshold voltage shift was observed with further increase in PBS duration up to 3000 s. Similar shifting of the transfer curve in the negative direction was observed with increasing NBS duration up to 500 s (Figure S4a, Supporting Information). Parallel shifting of the transfer curves under PBS/NBS with no signifi cant change Transparent metal oxide based thin fi lm transistors (TFTs) have been extensively studied during the last decade due to their potential application in displays and other electronic devices. [ 1 ]

Low‐Temperature, Nontoxic Water‐Induced Metal‐Oxide Thin Films and Their Application in Thin‐Film Transistors

Here, a simple, nontoxic, and inexpensive “water‐inducement” technique for the fabrication of oxide thin films at low annealing temperatures is reported. For water‐induced (WI) precursor solution, the solvent is composed of water without additional organic additives and catalysts. The thermogravimetric analysis indicates that the annealing temperature can be lowered by prolonging the annealing time. A systematic study is carried out to reveal the annealing condition dependence on the performance of the thin‐film transistors (TFTs). The WI indium‐zinc oxide (IZO) TFT integrated on SiO2 dielectric, annealed at 300 °C for 2 h, exhibits a saturation mobility of 3.35 cm2 V−1 s−1 and an on‐to‐off current ratio of ≈108. Interestingly, through prolonging the annealing time to 4 h, the electrical parameters of IZO TFTs annealed at 230 °C are comparable with the TFTs annealed at 300 °C. Finally, fully WI IZO TFT based on YOx dielectric is integrated and investigated. This TFT device can be regarded as “green electronics” in a true sense, because no organic‐related additives are used during the whole device fabrication process. The as‐fabricated IZO/YOx TFT exhibits excellent electron transport characteristics with low operating voltage (≈1.5 V), small subthreshold swing voltage of 65 mV dec−1 and the mobility in excess of 25 cm2 V−1 s−1.

Design and analysis of noise margin, write ability and read stability of organic and hybrid 6-T SRAM cell

This paper analyzes SRAM cell designs based on organic and inorganic thin film transistors (TFTs). The performance in terms of static noise margin (SNM), read stability and write ability for all-p organic (Pentacene–Pentacene), organic complementary (Pentacene–C60) and hybrid complementary (Pentacene–ZnO) configurations of SRAM cell is evaluated using benchmarked industry standard Atlas 2-D numerical device simulator. Moreover, the cell behaviour is analyzed at different cell and pull-up ratios. The electrical characteristics and performance parameters of individual TFT used in SRAM cell is verified with reported experimental results. Furthermore, the analytical result for SNM of all-p organic SRAM cell is validated with respect to the simulated result. Besides this, the cell and pull-up ratios of the hybrid and organic SRAM cells are optimized for achieving best performance of read and write operations and thereafter, the results are verified analytically also. The SNM of hybrid cell is almost two times higher than the all-p SRAM, whereas this improvement is just 18% in comparison to the organic memory cell. On the other hand, the organic complementary SRAM cell shows an improvement of 26% and 22% for the read stability in comparison to the all-p organic and hybrid SRAM cells, respectively. Contrastingly, this organic cell demonstrates a reduction of 16% in the SNM and an increment of 76% in write access time in comparison to the hybrid cell. To achieve an overall improved performance, the organic complementary SRAM cell is designed such that the access transistors are pentacene based p-type instead of often used n-type transistor. Favorably, this organic SRAM design shows reasonably lower write access time in comparison to the cell with n-type access OTFTs. Moreover, this cell shows adequate SNM and read stability that too at substantially lower width of p-type access OTFTs.

Influence of molybdenum source/drain electrode contact resistance in amorphous zinc–tin-oxide (a-ZTO) thin film transistors

This paper investigates the feasibility of a low-resistivity electrode material (Mo) for source/drain (S/D) electrodes in thin film transistors (TFTs). The effective resistances between Mo source/drain electrodes and amorphous zinc–tin-oxide (a-ZTO) thin film transistors were studied. Intrinsic TFT parameters were calculated by the transmission line method (TLM) using a series of TFTs with different channel lengths measured at a low source/drain voltage. The TFTs fabricated with Mo source/drain electrodes showed good transfer characteristics with a field-effect mobility of 10.23cm2/Vs. In spite of slight current crowding effects, the Mo source/drain electrodes showed good output characteristics with a steep rise in the low drain-to-source voltage (VDS) region.

A high-yield vacuum-evaporation-based R2R-compatible fabrication route for organic electronic circuits

Advances are described in a vacuum-evaporation-based approach for the roll-to-roll (R2R) production of organic thin film transistors (TFTs) and circuits. Results from 90-transistor arrays formed directly onto a plasma-polymerised diacrylate gate dielectric are compared with those formed on polystyrene-buffered diacrylate. The latter approach resulted in stable, reproducible transistors with yields in excess of 90%. The resulting TFTs had low turn-on voltage, on–off ratios ∼106 and mobility ∼1cm2/Vs in the linear regime, as expected for dinaphtho[2,3-b:2′,3′-f] thieno[3,2-b]thiophene the air stable small molecule used as the active semiconductor. We show that when device design is constrained by the generally poor registration ability of R2R processes, parasitic source–drain currents can lead to a >50% increase in the mobility extracted from the resulting TFTs, the increases being especially marked in low channel width devices. Batches of 27 saturated-load inverters were fabricated with 100% yield and their behaviour successfully reproduced using TFT parameters extracted with Silvaco’s UOTFT Model. 5- and 7-stage ring oscillator (RO) outputs ranged from ∼120Hz to >2kHz with rail voltages, VDD, increasing from −15V to −90V. From simulations an order of magnitude increase in frequency could be expected by reducing parasitic gate capacitances. During 8h of continuous operation at VDD=−60V, the frequency of a 7-stage RO remained almost constant at ∼1.4kHz albeit that the output signal amplitude decreased from ∼22V to ∼10V. Over the next 30days of intermittent operation further degradation in performance occurred although an unused RO showed no deterioration over the same period.

Stability characteristics of gallium-doped zinc-tin-oxide thin-film transistors fabricated using a sol-gel method

We investigated the incorporation of Ga into zinc-tin-oxide (ZTO) thin-film transistors (TFTs) and assessed the TFTs’ electrical and stability properties. The Ga-doped ZTO (ZTO:Ga) thin films were deposited on thermally oxidized silicon substrates by using a sol-gel technique. The Ga contents were varied from 1 to 20 atomic percent (at.%) while the Zn:Sn ratio was maintained at 1:1. The dependence of the ZTO:Ga thin films’ structural properties on the Ga content was analyzed using Xray diffraction (XRD) spectra, scanning probe microscopy (SPM), X-ray photoelectron spectroscopy (XPS), and UV-visible spectrophotometry. The field effect mobilities and the I on /I off ratios of the ZTO:Ga-TFTs were between 0.68 and 2.95 cm2Vs−1s−1 and ∼104 and ∼106, respectively. At low Ga contents, the (<10-at.%) TFTs displayed similar TFT parameters, but the 20-at.%-Ga TFT showed improved mobility and stability characteristics. Moreover, the 20-at.%-Ga thin film had a smoother surface and increased crystallinity than the low Ga-content samples did.

Correlation between Ti source/drain contact and performance of InGaZnO-based thin film transistors

Ti contact properties and their electrical contribution to an amorphous InGaZnO (a-IGZO) semiconductor-based thin film transistor (TFT) were investigated in terms of chemical, structural, and electrical considerations. TFT device parameters were quantitatively studied by a transmission line method. By comparing various a-IGZO TFT parameters with those of different Ag and Ti source/drain electrodes, Ti S/D contact with an a-IGZO channel was found to lead to a negative shift in VT (−Δ 0.52 V). This resulted in higher saturation mobility (8.48 cm2/Vs) of a-IGZO TFTs due to effective interfacial reaction between Ti and an a-IGZO semiconducting layer. Based on transmission electron microcopy, x-ray photoelectron depth profile analyses, and numerical calculation of TFT parameters, we suggest a possible Ti contact mechanism on semiconducting a-IGZO channel layers for TFTs.

Contactless Functionality Inspection of Flat-Panel-Display Pixels and Thin-Film Transistors by Capacitive Coupling

A fast and thorough detection of structural and functional defects of flat-panel displays, large-area image detectors, and printed electronics requires a contactless and flexible inspection technique. Moreover, to accelerate the development of new products and to increase yields, efficient device characterization including the analysis of single component functionality and testing under operating conditions is essential. In this contribution, a contactless inspection method solely based on capacitive coupling is used to analyze pixel and thin-film transistor (TFT) functionality of active-matrix liquid crystal and electrophoretic display backplanes. Employing a capacitively coupled sensor, the measurement of the evolution of the pixel electrode voltage during TFT operation (switching) yields display flicker and TFT parameters, such as TFT on- and off-currents, TFT threshold, and intrinsic capacitance. To confirm the measurement results, the pixel voltage was also measured with an active voltage probe brought into contact with the pixel electrodes under test.

Role of ${\hbox{HfO}} _{2} $/${\hbox{SiO}}_{2}$ Gate Dielectric on the Reduction of Low-Frequent Noise and the Enhancement of a-IGZO TFT Electrical Performance

High-κ dielectric is regarded as an effective material to reduce the operating voltage of the amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs). However, the dielectric with high permittivity often has the drawbacks of inducing small conduction band offset energy and high interface trap density. Here a bilayer HfO2/SiO2 gate dielectric for thin-film transistors (TFTs) is employed to address the issues. Compare to the a-IGZO TFT with solely 15 nm-thick HfO2 gate dielectric, the TFT with the bilayer HfO2/SiO2 (10 nm/5 nm) gate dielectric improves the subthreshold swing (SS) from 0.22 to 0.12 V/decade, the mobility from 1.4 to 7 cm2/V·s and current on-off ratio from 9×106 to 1.3×10 9. Finally, Hooge's parameters (extracted from the low-frequency noise measurement) of a-IGZO TFTs were investigated to understand the defects near the channel/dielectrics interface so that the role of the thin SiO2 layer can be verified. The device with bilayer HfO2/SiO2 structure exhibits a value of 2×10-3, which is an order of magnitude lower than the one with a single HfO2 layer. The Hooge's parameter of our bilayer dielectric is the lowest among the reported metal-oxide based TFTs on the glass substrate.

Edge Effects in Bottom-Gate Inverted Staggered Thin-Film Transistors

For thin-film transistor (TFT) characterization and simulation, accurate knowledge of the effective channel width ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W_{\rm EFF}$</tex></formula> ) and effective channel length ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L_{\rm EFF}$</tex></formula> ) is required, particularly in narrow and/or short devices, where small dimensional variations may result in large overestimation/underestimation of device parameters. Although a substantial amount of research has been done to determine <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$L_{\rm EFF}$</tex></formula> , there is very little work presented regarding <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W_{\rm EFF}$</tex></formula> . Here, we report a design-related existence of current leakage paths along the channel edges in inverted staggered TFT structures. Applied here for the case of amorphous-silicon- and amorphous-oxide-semiconductor-based TFTs, a model is developed to investigate the edge effect from a series of TFTs with various channel widths ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W$</tex></formula> ). <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$W_{\rm EFF}$</tex></formula> is found to be larger than the designed <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W$ </tex></formula> , resulting in an overestimation of the extracted TFT parameters such as the field-effect mobility. It is concluded that a preferred TFT design consists of source and drain electrodes that extend over the active area along the <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$W$</tex></formula> direction to minimize the edge effects and, hence, improve the accuracy of the extracted TFT parameters.

Dynamic charge transport in pentacene and zinc oxide thin-film transistors: Dark and UV illumination conditions

The electronic charge transport of thin film transistors (TFTs) based on pentacene and zinc oxide semiconductors was studied. A mathematical model is presented based on the variable range hopping (VRH) transport theory. Using the VRH model, the expression of source drain current is established under dark and under UV illumination (365nm) in linear regime for drain bias VD=−2V and 2V, when we used pentacene and zinc oxide, respectively, at 300K. All electrical key parameters of TFTs based on pentacene and zinc oxide were extracted. A good agreement between theoretical model and experimental measurement, transfer characteristics was obtained under dark and UV illumination conditions. Finally, we give a simple small-signal equivalent circuit to the organic and inorganic thin film transistor.

Effect of Ag doping on the electrical properties of thermally deposited CdS–La2O3 TFTs

In this article, we have reported the fabrication of CdS thin film transistors (TFTs) doped with Ag by thermal evaporation technique on chemically cleaned glass substrates using multiple pumps down process. High-k rare earth oxide La2O3 is used as gate dielectric in CdS TFTs. Some important electrical parameters have been evaluated using Weimer's model. The electrical parameters are compared with the parameters of undoped CdS TFTs. The Ag-doped CdS TFTs exhibit a high mobility of 6.1 cm2 V−1 s−1 than that of the undoped CdS TFTs, mobility of which is found as 6.25 × 10−2 cm2 V−1 s−1. The TFTs also exhibit low threshold voltage. Both Ag-doped and undoped TFTs are characterised using Levinson et al. model.

Analytic model for ZnO-thin film transistor under dark and UV illumination

A ZnO thin film transistor (TFT) was fabricated on a SiO2/Si substrate by sol-gel method. Electrical characteristics of the zinc oxide transistor under various illuminations were analyzed. We have developed a method to extract the TFT parameters under dark and under UV illuminations. This component requires an ohmic source and drain contacts for ideal operation. The performance of electronic-device is often limited by injection. In many real situations, the injection of charge carriers from metals into semiconductors is non-linear. This paper deals with the effects of non-ohmic contacts on the modeling of ZnO thin film transistor and gives specific rules on how to extract the real transistor parameters using only electrical measurements under dark and illumination.We have extracted the TFT parameters using developed method from output characteristics under dark and UV illumination. The drain current of the ZnO thin film transistor under UV illumination is improved. We have demonstrated that the UV illumination reduce the total resistance and improve the performance of the transistor.

Effect of fluorination and hydrogenation by ion implantation on reliability of poly-Si TFTs under gamma irradiation

Sputtered thin film transistors (TFTs), which were hydrogenated and fluorinated by ion implantation, were exposed to gamma irradiation up to 2500 Gy. Long term post-irradiation stability of TFTs was studied after eight months of storage and under positive bias test at 150 °C in time intervals of 1–10 h. The effects induced by irradiation and during relaxation period were monitored by current–voltage (I–V) measurements. I–V data were used to determine post-irradiation changes in different TFT parameters, such as threshold voltage, interface states density and grain boundaries trap density. The behaviour of these parameters was compared for four types of TFTs: non-fluorinated-hydrogenated, fluorinated, hydrogenated and fluorinated-hydrogenated, and it was found that hydrogenated TFTs showed greater instability. A mechanism for grain boundary traps generation is proposed.