Thin-film Transistor Structure Research Articles

Junctionless Structure Indium-Tin Oxide Thin-Film Transistors Enabling Enhanced Mechanical and Contact Stability.

In recent years, considerable attention has focused on high-performance and flexible crystalline metal oxide thin-film transistors (TFTs). However, achieving both high performance and flexibility in semiconductor devices is challenging due to the inherently conductive and brittle nature of crystalline metal oxide. In this study, we propose a facile way to overcome this limitation by employing a junctionless (JL) TFT structure via oxygen plasma treatment of the crystalline indium-tin oxide (ITO) films. The oxygen plasma treatment significantly reduced oxygen vacancies in the ITO films, contributing to the significant reduction in the carrier concentration from 4.67 × 1020 to 1.39 × 1016. Importantly, this reduction was achieved without inducing any noticeable structural changes in the ITO, enabling the successful realization of ITO JL TFTs with an adjustable threshold voltage. Furthermore, the ITO JL TFTs demonstrate good stability and reliability under various bias stress conditions, aging in the air atmosphere, and high-temperature processes. In addition, the ITO JL TFTs exhibit low light sensitivity due to the wide bandgap of ITO and further suppression of Vo defects, making them suitable for applications requiring stable performance under light exposure. To compare and analyze the flexibility of the JL structure and conventional structure with additional source/drain (S/D) junction in ITO TFTs with nonencapsulation, we utilized mechanical simulations and transmission line method (TLM). By employing the JL structure in ITO TFT through carefully optimized oxygen plasma treatment, we successfully mitigated stress concentration at the S/D-channel interface. This resulted in a JL ITO TFT that exhibited a change in contact resistance of less than 20% even after 20,000 bending cycles. Consequently, a stable and flexible ITO TFT with field-effect mobility (μFE) of 12.74 cm2/(V s) was realized, outperforming conventionally structured ITO TFTs with additional S/D junction, where the contact resistance nearly tripled.

50‐4: Invited Paper: Low‐Temperature Metal‐Oxide Thin‐Film Transistor Technology and the Realization of Electronic Systems on Flexible Substrates

A low‐temperature technology for fabricating thin‐film transistors (TFTs) is essential for the realization of electronic systems on flexible substrates. Presently reviewed are improved techniques for forming the source/drain regions and reducing the population of channel defects in a metal‐oxide TFT. These have been applied to the construction of different TFT structures, including ones with bottom gate, top gate, and dual gates. The utility of the improved 300‐°C technology has been demonstrated by the realization of a variety of electronic systems, such as a gate‐driver on array for active‐matrix displays, an analog front‐end for acquiring biopotential signals, and an artificial neural network for neuromorphic computing.

P‐19: High Mobility and Reliability Oxide Stacked TFT for Application to Next Generation Display

The stacked structure thin film transistors (TFT) has caused the widespread attention to achieve high mobility and reliability simultaneously. To ensure the stacked structure TFT application to mass production, it is critical to reduce the number of mask‐count. In this paper, 8‐mask‐count stacked TFT‐array process using the first semiconductor layer overlapped with the source and drain layer directly, which is the first layer on the glass substrate, is studied. By adopting this novel process, the device mobility is 25.4 cm2/Vs, which is more than twice that of conventional top‐gate self‐aligned a‐IGZO device. Besides, the ΔVth under the positive bias stress of 30V and negative bias temperature illumination stress of ‐30V for 1 h is +0.41V and ‐0.13V, respectively, achieving the stability to the level of a‐IGZO TFTs.

Performance Improvement of In-Ga-Zn Oxide Thin-Film Transistors by Excimer Laser Annealing.

We applied excimer laser annealing (ELA) on indium-zinc oxide (IZO) and IZO/indium-gallium-zinc oxide (IGZO) heterojunction thin-film transistors (TFTs) to improve their electrical characteristics. The IZO and IZO/IGZO heterojunction thin films were prepared by the physical vapor deposition method without any other annealing process. The crystalline state and composition of the as-deposited film and the excimer-laser-annealed films were analyzed by X-ray diffraction and X-ray photoelectron spectroscopy. In order to further enhance the electrical performance of TFT, we constructed a dual-heterojunction TFT structure. The results showed that the field-effect mobility could be improved to 9.8 cm2/V·s. Surprisingly, the device also possessed good optical stability. The electron accumulation at the a-IZO/HfO, HfO/a-IGZO, and a-IGZO/gate insulator (GI) interfaces confirmed the a-IGZO-channel conduction. The dual-heterojunction TFT with IZO/HfO/a-IGZO-assisted ELA provides a guideline for overcoming the trade-off between high mobility (μ) and positive VTh control for stable enhancement mode operation with increased ID.

Electrical performance of La-doped In2O3 thin-film transistors prepared using a solution method for low-voltage driving.

In this paper, La-doped In2O3 thin-film transistors (TFTs) were prepared by using a solution method, and the effects of La doping on the structure, surface morphology, optics, and performance of In2O3 thin films and TFTs were systematically investigated. The oxygen defects concentration decreased from 27.54% to 17.93% when La doping was increased to 10 mol%, and La served as a carrier suppressor, effectively passivating defects such as oxygen defects. In fact, the trap density at the dielectric/channel interface and within the active layer can be effectively reduced using this approach. With the increase of La concentration, the mobility of LaInO TFTs decreases gradually; the threshold voltage is shifted in the positive direction, and the TFT devices are operated in the enhanced mode. The TFT device achieved a subthreshold swing (SS) as low as 0.84 V dec-1, a mobility (μ) of 14.22 cm2 V-1 s-1, a threshold voltage (VTH) of 2.16 V, and a current switching ratio of Ion/Ioff of 105 at a low operating voltage of 1 V. Therefore, regulating the doping concentration of La can greatly enhance the performance of TFT devices, which promotes the application of such devices in high-performance, large-scale, and low-power electronic systems.

Synaptic Characteristics of Atomic Layer-Deposited Ferroelectric Lanthanum-Doped HfO2 (La:HfO2) and TaN-Based Artificial Synapses.

Analog synaptic devices have made significant advances based on various electronic materials that can realize the biological synapse properties of neuromorphic computing. Ferroelectric (FE) HfO2-based materials with nonvolatile and low power consumption characteristics are being studied as promising materials for application to analog synaptic devices. The gradual reversal of FE multilevel polarization results in precise changes in the channel conductance and allows analogue synaptic weight updates. However, there have been few studies of FE synaptic devices doped with La, Y, and Gd. Furthermore, an investigation of interface quality is also crucial to enhance the remnant polarization (Pr), synaptic conductance linearity, and reliability characteristics. In this study, we demonstrate improved FE and artificial synaptic characteristics using an atomic layer-deposited (ALD) lanthanum-doped HfO2 (La:HfO2) and TaN electrode in the structure of an FE thin-film transistor (ITO/IGZO/La:HfO2/TaN), where indium-tin oxide (ITO) and indium-gallium-zinc oxide (IGZO) were used as source/drain and channel materials, respectively. Improved Pr and lower surface roughness were achieved by doped HfO2 and ALD TaN thin films. This synaptic transistor shows long-term potentiation and long-term depression with 200 levels of conductance states, high linearity (Ap, 0.97; Ad, 0.86), high Gmax/Gmin (∼6.1), and low cycle-to-cycle variability. In addition, a pattern recognition accuracy higher than 90% was achieved in an artificial neural network simulation.

In2O3-based thin-film transistors with a (400) polar surface for CO2 gas detection at 150 °C

Because of increasing demand for CO2 detection, CO2 sensors capable of low-temperature operation are desired. However, conventional oxide semiconductor sensors still require high operating temperatures. In this study, we fabricated a CO2 sensor that can operate at 150 °C. The sensor is based on an open-channel-type thin-film transistor (TFT) structure with an In2O3(400) polar plane as a channel. Because the In2O3(400) surface is polar, many OH groups are adsorbed onto the as-prepared surface. When CO2 gas is introduced, CO2 molecules react with the OH groups and the TFT characteristics change. As a result, CO2 can be detected with a sensitivity 2.9 times greater than that under an inert N2 atmosphere despite the operating temperature of only 150 °C. In a TFT with nonpolar In2O3(222) planes, the sensitivity remains at 1.3 times. We therefore believe that TFTs fabricated with the polar surface of an oxide semiconductor are useful for gas-sensing applications.

Electrical Characterization of InGaZnO-Based Thin Film Transistor fabricated by Three-mask Process

Indium Gallium Zinc Oxide (InGaZnO) has gained increasing attention as a replacement for amorphous silicon in thin-film transistors (TFTs) owing to its excellent electrical and optoelectronic properties, chemical stability, and potential for low-temperature processing.
 However, efforts are being made to optimize the design to improve the performance and reduce costs.
 In this study, a top-contact top-gate (TCTG) structure of InGaZnO TFTs was fabricated using three lithography steps. The electrical current–voltage characteristics of the device were measured and used to extract the device parameters.
 The result shows transistor parameters with threshold voltage of –9 V, ON-OFF ratio of in the range of 103, maximum mobility of 1.15 cm2V-1 s-1, subthreshold slope of in the range of 103 mV/dec, and maximum interface trap density of 1.53x103 (cm-2eV-1) at maximum applied voltage of 5 V.

Improving the electrical stability of a‐IGZO TFT through gate surround structures

AbstractThis paper delves into a structural modification of dual‐gate oxide thin film transistor (TFT). Diverging from the conventional dual‐gate TFT structure, the authors’ approach connects the bottom and top gate electrodes, effectively enveloping all four sides of the a‐IGZO channel. This shielding configuration ensures stable operation, even under light illumination. Moreover, capitalizing on the stability under light conditions, the authors observed a remarkable threefold improvement in the mobility of the fabricated TFT with this proposed structure, resulting in a substantial 156% increase in current. Furthermore, in the negative bias illumination stress test, the proposed TFT exhibited minimal fluctuations when compared to its single‐gate counterpart, further underscoring its exceptional and robust performance.

Single‐layer thin‐film transistor analysis and design

AbstractA set of direct current (DC) analytical equations is formulated for the analysis and design of a single‐layer thin‐film transistor (TFT). For a specified TFT structure, drain current is calculated as a function of drain and gate voltage (taking the source as ground) according to the Enz, Krummenacher, Vittoz (EKV) compact model. One model parameter function is required to implement this EKV‐based equation, that is, drift mobility as a function of gate voltage. Drift mobility is evaluated as a consequence of accumulation layer electrostatics assessment of the TFT structure specified. In order to implement the model, three semiconductor properties (low‐frequency (static) relative dielectric constant, free electron concentration, and maximum (no trapping) mobility), two structure properties (insulator capacitance density and TFT width‐to‐length ratio), and one physical operating parameter (temperature) must be specified. Optimal TFT mobility performance is achieved when the thickness of the semiconductor channel layer is constrained to be less than 2.22 times the channel layer Debye length such that “short‐base” TFT operation obtains. Additionally, higher mobility TFT performance is obtained by selecting a channel layer with a small electron effective mass, reducing channel layer trap density, reducing channel layer thickness, reducing the free electron concentration, and/or increasing gate capacitance density.

Control of subthreshold swing using an in situ PEALD nano-laminated IGZO/Al2O3 multi-channel structured TFT

This study presents the development of multi-channel thin-film transistors (TFTs) using plasma-enhanced atomic layer deposition (PEALD) to stack layers of IGZO/Al2O3, with the number of stacking layers ranging from 1 to 10 (1S, 3S, 5S and 10S). To optimize the performance of the AM-LED display, the subthreshold swing (S·S) and mobility of each type of transistor, such as switching and driving transistors, were customized to meet specific requirements. The results show that as the number of stacking layers increased, the field-effect mobility (µ FE) improved by 323% from 1.34 to 4.33 cm2/Vs, while S·S improved by 0.14 V/dec from 0.31 to 0.45 V/dec, with no variation in threshold voltage (V th) and reliability. The study attributes the improvement in µ FE and S·S to the formation of multiple electron transport paths as confirmed by a TCAD simulation showing an increase in current density. Overall, this study demonstrates the potential of PEALD in creating multi-channel TFTs with improved performance by customizing oxide semiconductor properties. This research may have important implications in the development of advanced electronic devices that rely on thin-film transistors, as it provides a new approach in enhancing the performance of these devices.

Research Progress of Vertical Channel Thin Film Transistor Device.

Thin film transistors (TFTs) as the core devices for displays, are widely used in various fields including ultra-high-resolution displays, flexible displays, wearable electronic skins and memory devices, especially in terms of sensors. TFTs have now started to move towards miniaturization. Similarly to MOSFETs problem, traditional planar structure TFTs have difficulty in reducing the channel's length sub-1μm under the existing photolithography technology. Vertical channel thin film transistors (V-TFTs) are proposed. It is an effective solution to overcome the miniaturization limit of traditional planar TFTs. So, we summarize the different aspects of VTFTs. Firstly, this paper introduces the structure types, key parameters, and the impact of different preparation methods in devices of V-TFTs. Secondly, an overview of the research progress of V-TFTs' active layer materials in recent years, the characteristics of V-TFTs and their application in examples has proved the enormous application potential of V-TFT in sensing. Finally, in addition to the advantages of V-TFTs, the current technical challenge and their potential solutions are put forward, and the future development trend of this new structure of V-TFTs is proposed.

Frequency Response Characteristics Depending on the Metal Capping Structure and Length of the Amorphous SiZnSnO Thin Film Transistor

Frequency Response Characteristics Depending on the Metal Capping Structure and Length of the Amorphous SiZnSnO Thin Film Transistor

32‐2: Mask Reducing Backplane Architecture for Advanced Micro‐LED Display

In this work, a novel thin film transistor (TFT) structure named ASD was prepared, which means active layer bottom‐contact with source/drain(SD) layer. ASD device use the first light shield metal layer served as SD electrode simultaneously, which can reduce 2‐count‐mask array process compared with traditional top gate (TG) device. The mobility and subthreshold swing of the ASD a‐IGZO TFT device can reach 14 cm2/Vs and 0.18 V/dec, respectively. The PBTS and NBTIS are within 0.5V through process optimization. In addition, a 7.1 inch Micro‐LED display used ASD TFT backplane has demonstrated, and Finally, the Micro‐LED panel shows +0.7V Vth shift after the high temperature and high humidity operation (HTHHO) 500h reliability test.

P-type nickel oxide deposited by reactive hollow cathode gas flow sputtering for the potential usage in thin-film transistors

Thin Nickel Oxide film were deposited by reactive pulsed-direct current hollow cathode gas flow sputtering. This unique technique allows for sputtering magnetic target materials with very high rates without magnetron. Deposition was carried out from a nickel target at room temperature. The influence of process parameters on optical, electrical, and structural film properties are investigated. High deposition rates of 6 nm/s and 2 nm/s are achieved for both direct current and pulsed-direct current power supply. All films are highly resistive and show p-type conduction that is tunable with oxygen flow. The films exhibit optical band gap around 3,8 eV depending on process parameters like oxygen flow and pulsing parameter. Secondary electron microscopy shows pillar-like growth perpendicular to the surface, while grazing incidence X-ray diffraction reveals smaller, randomly oriented crystals. Electrical properties of the films were tested by Hall measurements, revealing mobilities in the range of 1 cm2Vs. The nano crystalline thin films were tested in staggered bottom gate Thin-Film Transistor structures for potential use as channel layer.

Homojunction structure amorphous oxide thin film transistors with ultra-high mobility

Amorphous oxide semiconductors (AOS) have unique advantages in transparent and flexible thin film transistors (TFTs) applications, compared to low-temperature polycrystalline-Si (LTPS). However, intrinsic AOS TFTs are difficult to obtain field-effect mobility (μ FE) higher than LTPS (100 cm2/(V·s)). Here, we design ZnAlSnO (ZATO) homojunction structure TFTs to obtain μ FE = 113.8 cm2/(V·s). The device demonstrates optimized comprehensive electrical properties with an off-current of about 1.5 × 10–11 A, a threshold voltage of –1.71 V, and a subthreshold swing of 0.372 V/dec. There are two kinds of gradient coupled in the homojunction active layer, which are micro-crystallization and carrier suppressor concentration gradient distribution so that the device can reduce off-current and shift the threshold voltage positively while maintaining high field-effect mobility. Our research in the homojunction active layer points to a promising direction for obtaining excellent-performance AOS TFTs.

The impact of multi-layered dielectrics on the electrical performance of ZnO thin-film transistors

The electrical performance of ZnO thin film transistors (TFTs) fabricated on three different dielectric layers is investigated using an inverted staggered bottom gate thin film transistor structure. This work demonstrated the potential of integrating high-k dielectrics in ZnO TFTs in a dielectric multi-layered stack using SiO2 as the support layer for all the hero-dielectrics layers. In order to achieve this, ZnO thin film semiconducting layers were deposited at room temperature by radio frequency (RF) sputtering method and with no post deposition heat treatment, making them suitable candidates for low cost large area electronics on low temperature substrates (such as plastics). The dielectric films investigated were aluminium nitride (AlN), silicon nitride (SiN) and silicon dioxide (SiO2). The effective mobility of SiN devices was about half that observed in AlN devices. However, the dielectric layers exhibited hysteresis of approximately 0 V, 2 V and 7 V for the SiO2, AlN and SiN respectively. In addition, SiO2 TFTs have lowest threshold voltage (VT) and turn-on voltage (Von). The capacitance-voltage measurement for these device show that the flatband and threshold voltage of SiN and AlN MOS capacitors shifted towards more negative voltages instead when compared with the single layer SiO2 devices.

Solution processed low operating voltage SnO2 thin film transistor by using Li2SnO3/TiO2 stacked gate dielectric

A thin layer of sol–gel derived lithium stannate (Li2SnO3) was deposited by a spin coating method that shows high areal capacitance with low DC conductivity which originated due to the mobile lithium ion (Li+) and low carrier concentration. The DC conductivity of this Li2SnO3 thin film has been reduced further by adding a sol–gel derived titanium-oxide (TiO2) layer. Moreover, bilayer thin film effective areal capacitance also increases due to the higher relative permittivity of TiO2 layer. The measured areal capacitance of such Li2SnO3 /TiO2 bilayer thin films is 518 nF/cm2 with a low current density of 3.8 X 10-5 A/cm2 under 5 V external bias, can fulfil the requirement as gate dielectric of a low operating voltage (≤3V) thin film transistor (TFT). For identifying its applicability as gate insulator, a solution-processed tin oxide (SnO2) thin film transistor (TFT) was fabricated with Li2SnO3/TiO2 stacked gate dielectric. In this TFT structure, thin film of TiO2, SnO2 and Li2SnO3 are all polycrystalline in nature. The electrical characterization of TFT has been done under DC mode operation in ambient atmosphere measurement which remain almost unaltered under 11 cyclic measurements. The optimized TFT required only 3.0 V external bias that shows an electron mobility of 3.47 cm2 V−1 s−1 with on/off ratio of 50.

Study on semiconductor materials for TFT and their application in flat panel displays

TFT has been widely used in recent years because of its excellent performance. Considerable research has been done to meet the demand for high-quality and high-resolution displays, making the choice of well-suited and high-performance materials more significant than ever. This work first presents the overall development from a historic perspective. The next section introduces the basic structure of thin film transistors (TFTs), followed by recent advancements in semiconductor materials of TFT, including metal oxide, amorphous silicon, polycrystalline silicon, carbon nanotubes, and organic semiconductors. These materials are analyzed from various aspects: electrical properties, process temperature, fabrication complexity, mobility uniformity on large panels, and compatibility with substrates. After that, the properties of these materials are compared in terms of their large-scale fabrication capability in flat panel displays. Advantages and challenges are also discussed as each of the five materials is suitable for specific commercial products. This work provides a reference for the selection of TFT materials in future flat panel display industry.

High mobility achieved in InGaZnO TFT with vacuum-gap as insulating layer

In this Letter, an amorphous In-Ga-Zn-O (InGaZnO) thin-film transistor (TFT) structure with a vacuum-gap as a dielectric layer is proposed and investigated. Field-effect conduction at the vacuum/InGaZnO interfaces exhibits extraordinary effective mobility (μ) up to 65 ± 20 cm2 V−1 s−1, while the μ is only around 10 cm2 V−1 s−1 at the SiO2/InGaZnO interfaces with similar film processing conditions. Temperature-dependent transport is performed for deeper insight of the physical origin of the much higher μ at the vacuum/InGaZnO interface. We have found the density of states (DOS) of tail states is notably lower for the transport near the vacuum (8 × 1017 compared to 1.1 × 1019 cm−3 eV−1 at the SiO2/vacuum interface). These indicate that traditional dielectric materials like SiO2 have strong effects on the charge transport degradation in InGaZnO TFTs by introducing extra energetic disorders, and the intrinsic charge transport in InGaZnO is potentially approaching those in poly-silicon TFTs. Exploring a high-quality dielectric layer should be one effective way to further optimize the electrical performance in TFTs based on amorphous oxide semiconductors.