Thin Film Transistor Fabrication Process Research Articles

Low-temperature process design for inversion mode n-channel thin-film-transistor on polycrystalline Ge formed by solid-phase crystallization

We fabricated an inversion mode n-channel thin-film-transistor (TFT) on polycrystalline (poly-) Ge at low temperatures for monolithic three-dimensional large-scale IC (3D-LSI) and flexible electronics applications. Based on our previously reported solid-phase crystallization (SPC) method, we designed an n-channel TFT fabrication process with phosphorous ion implantation to provide the source/drain (S/D). We succeeded in fabricating an n-channel TFT with typical electrical characteristics on poly-Ge and confirmed its operation mode to be inversion mode. However, the fabrication process included a high temperature (500 °C) step for S/D activation. To reduce the process temperature, we used a metal-induced dopant activation method and successfully reduced the activation temperature to 360 °C. This combination is expected to pave the way for high-performance 3D-LSI and flexible electronic devices based on SPC-Ge.

Performance and reliability enhancement of flexible low-temperature polycrystalline silicon thin-film transistors via activation-annealing temperature optimization

The high performance and reliability of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on flexible substrates need to be ensured for the proper operation of advanced flexible organic light-emitting diode (OLED) displays. However, due to the heat-sensitive components of flexible LTPS TFTs, their fabrication process faces challenges in the temperature management of its thermal treatment procedures such as activation annealing, which is an essential step in the in-line fabrication process of LTPS TFTs for activating dopants and reducing silicon lattice-related structural defects. In this work, we investigate the optimization of the activation-annealing process through the modulation of its process temperature. As the activation-annealing temperature was increased from 320 °C to 370 °C, the electrical characteristics and reliability of flexible LTPS TFTs improved owing to a decrease in the gate dielectric/channel interface and bulk channel defects. However, as the temperature was further increased to 420 °C, considerable degradations in device performance and reliability were observed due to a significant increase in the deep-level gate dielectric/channel interface and bulk channel defects. Physical analysis revealed that significant dehydrogenation, in which the breakage of Si−H bonds causes excess Si dangling bonds, occurred at 420 °C. This work shows that a fine temperature optimization of the activation annealing process is a necessary procedure for ensuring highly performant and reliable LTPS TFTs on flexible substrates.

(Invited, Digital Presentation) Evaluation of Polycrystalline-Si1-XGex Thin-Film Transistors Grown Laterally on a Glass Substrate Using a Continuous-Wave Laser

System-on-glass requires high-performance thin-film transistors (TFTs). In order to realize high-performance polycrystalline-Si (poly-Si) TFTs, we grew high-quality poly-Si thin films using a continuous-wave solid-state laser, in a method known as continuous-wave laser lateral crystallization (CLC). The grain boundary (G.B.) of CLC poly-Si is characterized by being parallel to the laser scan direction with shape of nearly straight line. Ge-based devices are attractive because of the superior carrier mobility of Ge in comparison to Si; however, as carriers in poly-Ge thin film are high concentration of hole generated from defects, it is difficult to control the level of doping. Moreover, fabrication of stable gate dielectric GeO2 is highly challenging. Addition of Ge to Si is expected to improve carrier mobility in Si, leading to poly-Si1-xGex TFTs with better performance than conventional poly-Si TFTs. Hence, our work here is a step in that direction. The purpose of this study is to understand the performance of poly-Si1-xGex TFTs, and to highlight the issues pertaining to poly-Si1-xGex thin films by comparing the performance of poly-Si1-xGex TFTs with that of poly-Si TFTs.A typical TFT fabrication process is as follows. An amorphous Si1-xGex thin film (~100 nm) with a Ge concentration of 10% is grown on a quartz substrate. After cleaning the substrate surface with hydrogen fluoride solution, CLC is carried out in air without substrate heating, followed by the preparation of transistor islands using reactive ion etching (RIE). A 50-nm-thick SiO₂ film is deposited by plasma enhanced chemical vapor deposition (PECVD), followed by heat treatment in nitrogen atmosphere at 550 °C for 4 h and deposition of Mo film as the top gate. Next, P or BF₂ is ion-implanted into poly-Si1-xGex for source-drain (SD) respectively, at 10 keV and 3×1015 cm-2. After ion implantation is completed, interlayer dielectric SiO2 film is deposited by PECVD and activated by heating in nitrogen atmosphere at 550 °C for 6 h. Subsequently, contact holes and Mo electrodes are formed. Finally, hydrogenation using step-cooling is performed to complete the TFT. N-channel (n-ch) and P-channel (p-ch) poly-Si TFTs are also fabricated using identical processes. Two types of TFTs were fabricated for both poly-Si1-xGex TFTs and poly-Si TFTs: one with the G.B. lying parallel to the SD direction (parallel type) and the other with the G.B. perpendicular to the SD direction (perpendicular type).The transfer characteristics of n-ch TFTs showed that the threshold voltages (Vth) of poly-Si1-xGex shifted in the positive direction in comparison with those of poly-Si TFTs. The mobility and sub-threshold swing (s.s.) values of poly-Si1-xGex were inferior to those of poly-Si TFTs, for both the parallel and perpendicular types.Considering the p-ch TFTs, the transfer characteristics of parallel poly-Si1-xGex TFTs showed higher OFF current and lower ON current than the corresponding poly-Si TFTs. In case of perpendicular types, OFF currents of poly-Si1-xGex TFTs were comparable with that of poly-Si TFTs and ON currents of poly-Si1-xGex TFTs were lower than those of poly-Si TFTs. Moreover, Vth values of poly-Si1-xGex TFTs were shifted in the positive direction in comparison to those of poly-Si TFTs, for both parallel and perpendicular types.The segregation coefficient of Ge in Si is less than 1.0, and it has been shown that Ge segregates to G.B.s in poly-Si1-xGex thin films during solidification. As acceptors are generated in regions with high Ge concentration along G.B.s, p-type quasi-one-dimensional conduction regions were formed in Si1-xGex along G.B.s. Therefore, when SD regions are parallel to a G.B., a current path connecting those regions is formed along G.B.s in p-type poly-Si1-xGex TFTs, leading to enhancement of OFF current. However, when G.B.s lie perpendicular to SD regions, the latter remain unconnected, leading to normal OFF current values.The positive shift in Vth of poly-Si1-xGex TFTs can be explained by the formation of acceptors. It can also be concluded that the decrease of ON current in poly-Si1-xGex TFTs is due to ionized impurity scattering by the acceptors. In addition, the difference in the magnitude of ON current depending on the G.B. direction can be explained as follows: when G.B.s are parallel to the SD direction, ON current is higher than that of the perpendicular type, because G.B.s do not act as strong scattering centers.In summary, the characteristics of CLC poly-Si1-xGex TFTs can be explained by the formation of acceptors. In particular, the large OFF current in parallel p-ch poly-Si1-xGex TFTs is explained by Ge segregation along G.B.s, resulting in formation of quasi-one-dimensional p-type conduction channels and electrical connection between SD region.

(Invited) Hydrogenated Polycrystalline In2O3 (In2O3:H) Thin-Film Transistor with High Mobility Exceeding 100 cm2V−1s−1 Via Solid-Phase Crystallization

Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μ FE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50–100 cm2V−1s−1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µ FE = 139.2 cm2V−1s−1. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future electronic applications.

High-mobility hydrogenated polycrystalline In2O3 (In2O3:H) thin-film transistors

Oxide semiconductors have been extensively studied as active channel layers of thin-film transistors (TFTs) for electronic applications. However, the field-effect mobility (μFE) of oxide TFTs is not sufficiently high to compete with that of low-temperature-processed polycrystalline-Si TFTs (50–100 cm2V−1s−1). Here, we propose a simple process to obtain high-performance TFTs, namely hydrogenated polycrystalline In2O3 (In2O3:H) TFTs grown via the low-temperature solid-phase crystallization (SPC) process. In2O3:H TFTs fabricated at 300 °C exhibit superior switching properties with µFE = 139.2 cm2V−1s−1, a subthreshold swing of 0.19 Vdec−1, and a threshold voltage of 0.2 V. The hydrogen introduced during sputter deposition plays an important role in enlarging the grain size and decreasing the subgap defects in SPC-prepared In2O3:H. The proposed method does not require any additional expensive equipment and/or change in the conventional oxide TFT fabrication process. We believe these SPC-grown In2O3:H TFTs have a great potential for use in future transparent or flexible electronics applications.

Impact of NH3 plasma treatment for solution-processed indium oxide thin-film transistors with low thermal budget

The challenges associated with low-temperature solution-processed metal oxide thin-film transistors (TFTs) have hindered the realization of flexible oxide electronics at temperatures lower than 200 °C. NH3 plasma treatment is embarked upon as a route to effectively transform the chemical precursors to semiconducting metal oxides with high electrical quality. NH3 plasma-activated indium oxide (InOx) TFTs with saturated mobility 2.48 cm2V−1s−1 have been obtained at temperature as low as 150 °C. The low-temperature activation mechanism of NH3 plasma treatment for InOx films and the role of post-annealing in the fabrication process of InOx TFTs have been explored. Research shows that NH3 plasma treatment activates InOx films based on plasma bombardment, radicals doping and radical reactions; then, unreacted radicals and interstitial radicals were effectively removed by extra thermal energy from post-annealing. In comparison to thermal annealing, NH3 plasma treatment with moderate post-annealing is capable of achieving high degrees of condensation and densification reactions for InOx film and modulating the carrier concentration in a manner suitable for high-performance semiconducting behavior with low thermal budget. However, The InOx film after NH3 plasma treatment exhibited a non-uniform geometry due to the effect of plasma-induced damage in the local regions of InOx film, which restricts its commercial application. Some strategies were reported to eliminate the effect of plasma-induced damage by changing plasma conditions or pre-annealing temperature. The results demonstrated that changing plasma conditions by decreasing the plasma chamber temperature or the plasma power can eliminate plasma-induced damage, but attenuate the electrical performance of InOx TFT; nevertheless, changing pre-annealing temperature to 30 °C not only effectively eliminate plasma-induced damage, but also further improve the electrical performances of InOx TFT. These results provide a way for fabricating low-temperature oxide circuitry and supply an effective idea for avoiding plasma-induced damage.

Integration of GaN light-emitting diodes with a-Si:H thin-film transistors for flexible displays

In this work, the successful integration of a-Si:H thin-film transistors (TFTs) and high-efficiency μ-iLEDs on large-area flexible substrates has been demonstrated. A conventional low-temperature a-Si:H TFT fabrication process combined with a laser lift-off transfer procedure was used to integrate μ-iLEDs with flexible TFT pixel circuits. Electrical and optical characterization showed the current-voltage and electroluminescence characteristics of the TFTs and LEDs did not change after integration onto the flexible platforms. This approach provides a potential methodology for creating flexible optoelectronic systems for wearable and large-area display applications.

Direct imprinting of indium–tin-oxide precursor gel and simultaneous formation of channel and source/drain in thin-film transistor

We report on a new fabrication process for thin-film transistors (TFTs) with a new structure and a new operation principle. In this process, both the channel and electrode (source/drain) are formed simultaneously, using the same oxide material, using a single nano-rheology printing (n-RP) process, without any conventional lithography process. N-RP is a direct thermal imprint technique and deforms oxide precursor gel. To reduce the source/drain resistance, the material common to the channel and electrode is conductive indium–tin-oxide (ITO). The gate insulator is made of a ferroelectric material, whose high charge density can deplete the channel of the thin ITO film, which realizes the proposed operation principle. First, we have examined the n-RP conditions required for the channel and source/drain patterning, and found that the patterning properties are strongly affected by the cooling rate before separating the mold. Second, we have fabricated the TFTs as proposed and confirmed their TFT operation.

Electrical and Structural Characterization of Self-Aligned InGaZnO Thin-film Transistors Fabricated by Excimer Laser Irradiation

We conducted electrical and structural characterization of a self-aligned InGaZnO (IGZO) thin-film transistor (TFT) fabricated by selectively reducing the resistance of the source and drain (S/D) regions by backside excimer laser irradiation. We present the influence of the resistance of the S/D regions on the transfer characteristics and discuss the applicability of our resistance reduction method to the self-aligned oxide TFT fabrication process. In our proposed method, since the low-resistance regions are formed directly by using the gate electrode as a mask, the positions of the S/D regions can be accurately set. We demonstrate this by analyzing the spreading resistance and height profiles for the IGZO film.

Fully Inkjet‐Printed Thin‐Film Transistor Array Manufactured on Paper Substrate for Cheap Electronic Applications

AbstractOver the past decade, inkjet technology has been well recognized for the manufacturing of products that include “printing beyond colors.” This micrometer‐scale precise technology provides a straightforward approach toward judicious deposition of electronically functional material inks on various substrates over relatively large areas, for printed/flexible electronics. The technology promotes upscalability and has become a renowned process tool for fabricating electronic devices in the field of printed/flexible electronics. Here, the fabrication of printed thin‐film transistors (TFT) on cheap coated paper substrate using inkjet technology is reported. For developing the TFT layer stack conductive nanoparticle inks, a polymeric dielectric ink and a p‐type organic semiconductor ink are employed. The coating on the paper provides several advantages for fabrication process of TFTs; for example, control over ink spreading. This control of ink spreading can directly influence the fabrication of interdigitated source/drain (S/D) electrodes for TFTs, when a top gate bottom contact architecture is considered. This results in better manufacturing yields and promising electrical performance, which are also the focus of this research. The all inkjet‐printed TFTs on paper exhibit electrical performance with maximum S/D current ranging to 170 nA, charge carrier mobility of 0.087 cm2 V−1 s−1, and current on/off ratio of 330.

Highly Stable, High Mobility Al:SnZnInO Back-Channel Etch Thin-Film Transistor Fabricated Using PAN-Based Wet Etchant for Source and Drain Patterning

We report the electrical characteristics of backchannel etch (BCE) metal–oxide–semiconductor thin-film transistor (TFT) comprised of aluminum-doped tin–zinc–indium oxide (ATZIO). It has high etch selectivity in wet chemical etchants, which consist of H3PO4, CH3COOH, and HNO3. This is contrary to the conventional metal–oxide–semiconductors of indium–gallium–zinc oxides, which are highly soluble in the acidic chemicals. As a result, no etch stop layer is needed to protect the backchannel from the wet etchant damage during the source and drain patterning in the bottom-gate-staggered TFT structure. This provides the possibility of oxide TFT fabrication process made as simple as that of the current amorphous silicon TFT using three or four photomasks with short channel length and less parasitic capacitance. The electrical characteristics of our ATZIO BCE-TFTs have the mobility of 21.4 cm2/ $\text{V}\cdot \text{s}$ , subthreshold swing (S.S) of 0.11 V/decade, and threshold voltage of 0.8 V. In spite of the BCE structure, they have excellent stability against bias temperature stress, which shows the threshold voltage shifts of +0.75 V and −0.51 V under the prolonged positive (+20 V) and negative (−20 V) gate bias stresses for 10 000 s at 60 °C, respectively.

Drain Bias Effect on the Instability of Amorphous InGaZnO Thin-Film Transistors under Negative Gate Bias and Illumination Stress

Recently, amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) have been much investigated for their applications due to their excellent electrical properties such as high mobility (μ) and low subthreshold swing (SS) values. However, device reliability under light exposure has been recognized as an issue remaining to be resolved. In this study, the effect of drain bias (V DS) on the negative bias and illumination stress (NBIS) stability of a-IGZO TFTs was investigated. The degradation mechanisms of a-IGZO TFTs under NBIS with different V DSbiases were clarified.The fabrication process of the bottom-gate IGZO TFT was reported in detail elsewhere (1). NBIS was applied with a gate voltage (V GS) of −40 V under blue light (460 nm) at an intensity of 0.2 mW/cm2. The NBIS was temporarily interrupted when the transfer characteristics were measured by a double-sweeping V GS mode in darkness at V DS of 0.1 V, and then NBIS was reapplied up to an accumulated stress time of 104 s. For the double-sweeping V GS mode, transfer characteristics were measured with V GSfrom −10 to 20 V (denoted hereafter as forward measurement), and then scanned instantly back to −10 V (denoted hereafter as reverse measurement).Figure 1 shows the variation in the transfer characteristics under NBIS with grounded V DS for the forward and reverse measurements, respectively. In the initial stage of NBIS (< 1000 s), the transfer curves shifted in the negative V GS direction without SS degradation; on-current degradation was then observed in the subsequent stage (> 1000 s) in the forward measurement. In contrast, for the reverse measurements, the transfer curves hardly shifted within the initial NBIS duration of 1000 s, and then these exhibited a parallel shift in the positive V GS direction without SS degradation with increasing NBIS duration. We considered that the generated donor-like defects, originated from the ionized oxygen vacancies (VO + and/or VO 2+) and contributing to on-current degradation, were stabilized by capturing electrons during the forward measurement, and the trapped holes at the front-channel interface were detrapped by the positive V GSduring the forward measurement (2); therefore, electron trapping at the back-channel interface was an origin of the positive shift of the transfer curve without SS degradation in the subsequent reverse measurement.To investigate the effect of the V DS bias on the NBIS degradation, V DS biases of 40 and −60 V were applied with V GS of −40 V. Figure 2 shows the transfer characteristics in the forward and reverse measurements before and after NBIS duration of 104 s with different V DS biases. NBIS with an additional positive V DS bias of 40 V accelerated the donor-like state creation near the source side because of the positively charged VO + and/or VO 2+ drifting from the drain to the source side under the influence of the lateral electric field, which contributed to more severe on-current degradation. The NBIS degradation was significantly suppressed by applying a large negative V DS bias of −60 V, because the positive charges of VO + and/or VO 2+ were easily neutralized by electrons under the accumulation condition in the drain region. The detailed degradation mechanisms of a-IGZO TFTs under NBIS with various V DSbiases will be presented at the conference.Reference1. D. Wang, M. P. Hung, J. Jiang, T. Toda, C. Li, and M. Furuta, Jpn. J. Appl. Phys., 53, 03CC01 (2014).2. M. P. Hung, D. Wang, J. Jiang, and M. Furuta, ECS Solid State Letters, 3 (3), Q13 (2014).

Effects of Grain Size in Sequential Lateral Solidification Processed on Active Matrix Organic Light Emitting Diode Displays

In this work, we investigated the correlation between the spacing of primary grain boundaries in sequential lateral solidification (SLS) polycrystalline silicon and the brightness non-uniformity of active matrix organic light emitting diode panels. The oblique line is attributed both to the SLS method and the thin film transistor fabrication process. We found that the oblique line type of brightness non-uniformity disappeared when the spacing of primary grain boundaries is exactly the same in the individual transistor channel or when the non-uniform size is between 2.7 and 3.3 μ m( � Lg < ±10%) in active patterns. © 2014 The Electrochemical Society. [DOI: 10.1149/2.0071408ssl] All rights reserved.

Fabrication of suspended amorphous indium–gallium–zinc oxide thin-film transistors using bulk micromachining techniques

In this article, we propose a novel application of amorphous indium–gallium–zinc oxide (a-InGaZnO) thin films to micro electromechanical systems (MEMS). For this purpose, we investigated the residual stress in the a-InGaZnO thin films deposited by magnetron sputtering. The films with various residual stresses were characterized using atomic force microscopy, scanning electron microscopy, and X-ray diffraction. We found that the residual stress strongly depended on the sputtering gas pressure. In addition, we discovered a relationship between the residual stress and the microstructure in a-InGaZnO thin films. To gain more insight into the a-InGaZnO thin films with various residual stresses, we fabricated a-InGaZnO thin-film transistors (TFTs), and measured their transfer characteristics. We also fabricated a-InGaZnO TFTs on self-supported membranes, combining the typical TFT fabrication process and bulk micromachining techniques, for the application of a-InGaZnO to MEMS devices.

Effects of thermal annealing on variations of electron traps in the channel region of amorphous In-Ga-Zn-O thin film transistor

Photoinduced transient spectroscopy (PITS) was applied to study the effects of thermal annealing in the thin-film transistor (TFT) fabrication process on the variations of the electron traps in the channel region of amorphous In-Ga-Zn-O (a-IGZO). A dominant peak with a maximum of around 130 K was observed in the PITS spectra, but the detailed features were varied depending on the annealing conditions. The six particular temperatures corresponding to the trap states were extracted at about 100, 140, 150, 210, 320, and 390 K from the differential PITS spectra, showing good correlation with the trap states observed in ZnO. The results of thermal desorption spectrometry suggested that the variation of electron traps in the a-IGZO thin films has its origin in the decomposition of O and Zn during the annealing process. The annealing after the etch-stop layer deposition was also examined. The peak at about 150 K extracted from the differential PITS spectra before and after the annealing was markedly decreased. The activation energy of the corresponding trap states was estimated to be around 0.3 eV, which was close to those known as the E3 center in ZnO. Secondary ion mass spectroscopy analysis suggested that the reduction of trap density was mainly due to a decrease in the number of defects which involve hydrogen atoms in their configuration. Considering these results, the variations in the electron traps in the a-IGZO thin films during the TFT fabrication process should be attributed to the introduction of Zn, O, and/or H-related defects into tetrahedra consisting of Zn-O bonds.

Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors with a Low-Temperature Polymeric Gate Dielectric on a Flexible Substrate

Amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with a solution-processed polymeric gate dielectric of cross-linked poly(4-vinylphenol) (c-PVP) film were fabricated on a poly(ethylene terephthalate) (PET) substrate on which an a-IGZO film, as the active channel layer, was deposited by radio frequency (RF) sputtering. The entire TFT fabrication process was carried out at a temperature below 110 °C. The device exhibited an on/off ratio of 1.5×106 and a high field-effect mobility of 10.2 cm2 V-1 s-1, which is, to our knowledge, the best result ever achieved among a-IGZO TFTs with polymeric gate dielectrics on a plastic substrate.

Woven active-matrix display

In this paper, we present a woven textile display enabled by replacing standard textile threads with flexible stripes. Each stripe contains amorphous indium-gallium-zinc-oxide thin-film transistors (TFTs) that actuate light-emitting diodes (LEDs) on the same stripe. Weaving exposes thin-film layers on stripes to bending radii smaller than 200 μm (corresponding to strains higher than 10%). Therefore, we adapted our TFT fabrication process by omitting the usual blanket brittle silicon-nitride (SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> ) layer. TFTs fabricated without this layer have an equivalent electrical performance to devices fabricated using a SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> layer. Furthermore, TFTs are locally protected from excessive bending by covering them with 1.6 mm × 0.8 mm surface mount device LEDs. To demonstrate the feasibility of weaving TFTs on flexible stripes into textiles, we fabricated stripes consisting of three TFTs connected to three LEDs. Three of these stripes were subsequently integrated into a textile using a commercial weaving machine to create a 3 × 3 LED matrixLED matrix. The matrix was completed using conductive textile threads that are inserted perpendicular to the woven stripes to connect contact pads on adjacent stripes. The results show that TFTs can be woven into textiles without performance loss.

Low-Temperature-Processed Zinc Oxide Thin-Film Transistors Fabricated by Plasma-Assisted Atomic Layer Deposition

We investigated zinc oxide (ZnO) thin films prepared by plasma assisted atomic layer deposition (PA-ALD), and thin-film transistors (TFTs) with the ALD ZnO channel layer for application to next-generation displays. We deposited the ZnO channel layer by PA-ALD at 100 or 300 °C, and fabricated TFTs. The transfer characteristic of the 300 °C-deposited ZnO TFT exhibited high mobility (5.7 cm2 V-1 s-1), although the threshold voltage largely shifted toward the negative (-16 V). Furthermore, we deposited Al2O3 thin film as a gate insulator by PA-ALD at 100 °C for the low-temperature TFT fabrication process. In the case of ZnO TFTs with the Al2O3 gate insulator, the shift of the threshold voltage improved (-0.1 V). This improvement of the negative shift seems to be due to the negative charges of the Al2O3 film deposited by PA-ALD. On the basis of the experimental results, we confirmed that the threshold voltage of ZnO TFTs is controlled by PA-ALD for the deposition of the gate insulator.

Low-Temperature-Processed Zinc Oxide Thin-Film Transistors Fabricated by Plasma-Assisted Atomic Layer Deposition

We investigated zinc oxide (ZnO) thin films prepared by plasma assisted atomic layer deposition (PA-ALD), and thin-film transistors (TFTs) with the ALD ZnO channel layer for application to next-generation displays. We deposited the ZnO channel layer by PA-ALD at 100 or 300 °C, and fabricated TFTs. The transfer characteristic of the 300 °C-deposited ZnO TFT exhibited high mobility (5.7 cm2 V-1 s-1), although the threshold voltage largely shifted toward the negative (-16 V). Furthermore, we deposited Al2O3 thin film as a gate insulator by PA-ALD at 100 °C for the low-temperature TFT fabrication process. In the case of ZnO TFTs with the Al2O3 gate insulator, the shift of the threshold voltage improved (-0.1 V). This improvement of the negative shift seems to be due to the negative charges of the Al2O3 film deposited by PA-ALD. On the basis of the experimental results, we confirmed that the threshold voltage of ZnO TFTs is controlled by PA-ALD for the deposition of the gate insulator.

Real-time automatic inspection of macro defects in in-line TFT fabrication process

In this article, an automatic detection and judgement method for macro defects in thin film transistor (TFT) fabrication process is proposed using a high-resolution line charge-coupled device camera as a preliminary inspection method for TFT liquid crystal display (TFT-LCD) panel. Macro defects are classified primarily into four types. Relevant detection and judgement methods are then applied according to the type of macro defect using different criteria such as diffraction pattern shifts, just noticeable differences, and the gradient of inspection images. The proposed method is verified with industrial experiments. In the experiment, 559 TFT glasses are used, which are sampled among the glasses and were judged as PASS (i.e. non-killer-defected glass) in the TFT fabrication process by a conventional human inspection method, but were judged as REJECT (i.e. killer-defected glass) in the module process. All macro defects in the sampled glasses were detected and rejected in the TFT fabrication process using the proposed method.