Thin-film Silicon-on-insulator Research Articles

Preparation of thin-film SOI wafer by low-dose ion implantation

Silicon-on-insulator (SOI) devices have many advantages, such as high speed, low energy consumption, radiation-hard, and high integration. In this paper, the separation by implanted oxygen process under low-dose implantation conditions is studied by the two-step implantation method combined with the internal thermal oxidation process. The effects of different types of silicon wafers and different implantation doses on SOI surface defects, top Si thickness, buried oxide (BOX) layer thickness, BOX layer breakdown voltage, and top Si defect density were investigated. Ultra-thin SOI wafers are prepared by epitaxial silicon wafers and control the first implantation dose. The number of surface defects of SOI materials is less than 100 counts, the breakdown voltage of the BOX layer is about 7.8 MV/cm, and the top Si dislocation density is about 8 × 103 cm−2.

Comparison of the instability in device characteristics for thin-film SOI power n- and p-MOSFETs at high temperature under AC stress

In this study, we compare the device instability (hot carrier effect, negative bias temperature instability (NBTI), and positive bias temperature instability (PBTI)) of a thin-film Silicon on Insulator (SOI) power n-MOSFET and p-MOSFET at a high temperature under AC stress. For a p-MOSFET, the degradation rate of the on-resistance increases with an increase in temperature beyond 373 K. Contrarily, for an n-MOSFET, the degradation rate decreases with an increase in temperature. For a p-MOSFET, the threshold voltage shift increases with an increase in temperature due to the NBTI, whereas, for an n-MOSFET, it decreases with an increase in temperature. This is because the hot carrier effect decreases with an increase in temperature under AC stress. In this study, we clarify that the instability mechanism of the p-MOSFET under AC stress is different from that of the n-MOSFET.

Coupling effect in field Hall elements based on thin-film SOI MOS transistors

The influence of the coupling effect on the parameters of field Hall elements based on thin-film MOS transistors has been studied. Analysis of the development of today’s microelectronics shows the necessity of developing the element base for high performance sensors based on silicon technologies. One way to significantly improve the performance of sensing elements including magnetic field sensors is the use of thin-film transistors on the basis of silicon on insulator (SOI) structures. It has been shown that field Hall sensors (FHS) may become the basis of high-performance magnetic field sensors employing the coupling effect occurring in the double gate vertical topology of these sensing elements. Electrophysical studies of FHS have been conducted for different gate bias and power supply modes. The results show that the coupling effect between the gates occurs in FHS if the thickness of the working layer between the gates is 200 nm. This effect leads to an increase in the effective carrier mobility and hence an increase in the magnetic sensitivity of the material. Thus field Hall elements based on thin-film transistors fabricated using silicon technologies provide for a substantial increase in the magnetic sensitivity of the elements and allow their application in highly reliable magnetic field sensors.

Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.

High Temperature 0.35 Micron Silicon-on-Insulator CMOS Technology

Silicon-on-Insulator (SOI) is the most commonly used technology for integrated circuits capable of operating at high temperature. Due to the efficient reduction of leakage current paths much higher operation temperatures are achievable with SOI than with bulk technologies. Published work on high temperature CMOS circuits typically refers to technologies with a minimum feature size of 0.8 to 1.0 micron [1][2][3] even though for complex digital circuits this results in large die size. Technologies with smaller feature size are available but typically not suitable for reliable high temperature operation due to high leakage currents, decreasing threshold voltages over temperature or reliability issues with the standard aluminum metallization. Fraunhofer IMS has developed a high temperature 0.35 micron thin film SOI technology. The mixed signal technology provides numerous devices, e.g. specific transistors for analog and digital circuit design, diodes, resistors and voltage independent capacitors. Also non-volatile memory cells (EEPROM) are available. In addition the technology is equipped with a tungsten metallization for highly reliable operation even at high temperatures. An overview on the new technology including characterization results of devices and test circuits is given in this paper.

A Technique to Improve the Performance of an NPN HBT on Thin-Film SOI

The performance of an npn SiGe HBT on thin-film silicon on insulator (SOI) is investigated using 2-D numerical simulation. A technique of using N+ buried layer has been presented to improve the performance of an SiGe HBT on thin-film SOI. The tradeoff in the performance of HBT has been observed and the results are compared to the standard SOI HBT. The HBT offers better βV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">A</sub> product at high collector currents. A 341 GHzV of f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> BV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CEO</sub> product can be obtained by using this technique. The scalability of film thickness is applied and the enhancement in the speed is observed. The self-heating performance of the proposed HBT is studied and the BOX thickness has been scaled to improve the thermal performance. The maximum lattice temperature is obtained. The proposed HBT is suitable for RF applications and can be used in addition to the existing 130 nm SOI CMOS technology for better performance.

High Temperature Characterization up to 450°C of MOSFETs and Basic Circuits Realized in a Silicon-on-Insulator (SOI) CMOS Technology

Standard bulk CMOS technology targets operating temperatures of not more than 175°C. Silicon-on-insulator technologies are commonly used up to 250°C. In this work, we evaluate the limit for electronic circuit function realized in thin film SOI technologies for even higher temperatures. At Fraunhofer IMS, a versatile 1.0 μm SOI-CMOS process based on 200 mm wafers is available. It features three layers of tungsten metallization with excellent reliability concerning electromigration, as well as voltage-independent capacitors, various resistors, and single-poly-EEPROMs. We present a study of the temperature dependence of MOSFETs and basic circuits produced in this process. The electrical characteristics of an NMOSFET transistor and a PMOSFET transistor are studied up to 450°C. In a second step, we investigate the functionality of a ring oscillator (representing a digital circuit) and a band gap reference as an example of a simple analog component. The frequency and the current consumption of the ring oscillator, as well as the output voltage and the current of the band gap reference, are characterized up to 450°C. We find that the ring oscillator still oscillates at this high temperature with a frequency of about one third of the value at room temperature. The output voltage of the band gap reference is in the specified range (change &amp;lt; 3%) up to 250°C. The deviations above this temperature are analyzed and measures to improve the circuit are discussed. The acquired data provide an important foundation to extend the application of CMOS technology to its real maximum temperature limits.

Thin-film LDMOS on partial SOI with improved breakdown voltage and suppressed kink effect

Thin-film (TF) lateral double-diffused metal-oxide-semiconductor field effect transistor (LDMOSFET or LDMOS) of small dimensions on partial silicon-on-insulator (PSOI) with improved breakdown voltage and suppressed kink effect is introduced and studied. The silicon window and field plate can modulate the surface electric field of silicon film and, thus, their design parameters can be adjusted to achieve optimal breakdown voltage. Moreover, the silicon window can also provide a conduction path from the thin silicon film to the substrate and prevent hole accumulation in the floating body of silicon-on-insulator (SOI) devices, which can consequently suppress the kink effect. Effects of the device parameters (e.g. location of the field plate, location of silicon window, and doping concentrations of the drift region, silicon window and substrate) that control the performance of TF PSOI LDMOS are carefully studied. Compared with the conventional TF SOI LDMOS of small dimensions, the simulation results show that this proposed TF PSOI LDMOS exhibits approximately 100% improvement on the breakdown voltage and entirely eliminates the kink effect.

Defect delineation by chemical etching techniques in silicon and engineered silicon substrates: Novel chemistries and basic aspects

AbstractPreferential etching techniques in combination with light optical microscopy are still the workhorse for the evaluation of defect types and area densities in engineered silicon substrates such as silicon‐on‐insulator (SOI) wafers. Most etching recipes are based on chromium (VI) compounds as oxidizing agent. Since in the meantime the use of carcinogenic Cr (VI) compounds is restricted by law there is a need for Cr‐free recipes with adequate or superior defect delineation performance. We present novel Cr‐free etching chemistries based on organic peracids or on organic oxidizing agents (OOE) such as benzoquinone and derivatives in organic solvents. Some of these have very low removal rates (nm/min at 25 °C), are very defect sensitive and are especially suitable for the application on thin (&lt;50 nm) SOI films. Preferential etching solutions can be characterized by parameters like removal rate, activation energy for the etching process and selectivity. The selectivity describes the ratio of the removal at the crystal defect and at the perfect crystal. In this work the selectivity was determined experimentally on dislocations for various defect etching chemistries. Dislocations were generated by damaging silicon substrates by controlled indentation with a diamond tip and subsequent annealing at 1000 °C. After preferential etching the depth of etch pits was measured by an atomic force microscope. The activation energy was evaluated via an Arrhenius plot of the temperature dependent etch rates. At the dislocations the activation energies are reduced by about 5%. For the various defect etching chemistries selectivities in the range of 1.5–2.5 were found.

A Novel Partial-Ground-Plane-Based MOSFET on Selective Buried Oxide: 2-D Simulation Study

A novel partial-ground-plane (PGP)-based MOSFET on a selective buried oxide (SELBOX), named PGP-SELBOX, is proposed. An extensive simulation study and the comparative analysis of the key characteristics of the PGP-SELBOX, the SELBOX, and the conventional silicon-on-insulator (SOI) devices has been performed using the 2-D device simulator Medici. The simulations have revealed that the PGP-SELBOX and the SELBOX structures are more thermally efficient than the conventional SOI device. Further, the magnitude of the short-channel effects (SCEs) is lower in the PGP-SELBOX in comparison to the SELBOX device. Though the SCE suppression is best in the thin-film SOI device, the PGP-SELBOX shows better improvement in SCE suppression in comparison to the SELBOX device. The suppression of self-heating effects and SCEs in the PGP-SELBOX results in a significant reduction in leakage current. An improved performance in terms of I ON/I OFF ratio is obtained in the PGP-SELBOX device. Further, the fT values of the PGP-SELBOX are comparable to those of the SELBOX and the SOI devices. A process flow in which a low-dose separation by implantation of oxygen technique can be employed for the fabrication of the PGP-SELBOX is also proposed.

An efficient numerical simulation method for a thin film SOI RESURF structure

In this paper, an efficient numerical simulation method, which combines the spline alternating direction implicit (SADI) method and the high-order compact (HOC) finite difference method, is presented to simulate the potential and electric field distributions along the semiconductor surface of thin film silicon-on-insulator (TFSOI) reduced surface field (RESURF) devices. The relative merit of HOC–SADI is compared with three other popular numerical simulation methods, Newton, Gummel and CGS. The numerical results obtained from the proposed scheme are compared to the simulator MEDICI. HOC–SADI is a faster algorithm than Newton, Gummel and CGS as is evident from the CPU times and the number of iterations.

Fabrication of thin-film silicon on insulator by separation by implanted oxygen layer transfer

In this article, the authors propose an improved approach—separation by implanted oxygen (SIMOX) layer transfer process—to fabricate thin-film silicon on insulator (SOI). The top Si layer, a low-dose SIMOX wafer, was transferred upside down onto a thermally oxidized Si handle wafer by a bonding technique and etch-stop thinning process. Spectroscopic ellipsometry indicated a thin-film SOI with the device layer of 147.5±3.1nm. An atomic-scale sharp interface between the device layer and buried oxide layer was observed by high-resolution transmission electron microscopy.

Chromium(VI)-free Defect Etching Solutions for Application on Engineered Silicon Substrates

New defect etching solutions for application on engineered silicon substrates are presented which are free of toxic hexavalent chromium. The "FS Cr-free SOI" was developed for revealing crystal defects in silicon-on-insulator (SOI) substrates and proved to be a highly suitable alternative to the Secco etching solution. Another defect etching solution ("thin SOI etch") especially developed for application on very thin SOI films is also characterized in detail. For strained silicon-on-insulator (sSOI) substrates a defect etching solution ("sSOI etch") is introduced which shows an enhanced sensitivity to such low strain fields produced by stacking faults, however, its correlation to the Secco etching solution has to be improved. Besides etching mechanisms and defect delineation processes will be discussed.

Electrical Behavior and Technology Optimization of Si/SiGeC HBTs on Thin-Film SOI

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A growing interest has been focused on silicon on insulator (SOI) technologies over the past years. Yet, few studies were carried out regarding the integration of vertical SiGe heterojunction bipolar transistors (HBTs) using such substrates. This paper deals both with the integration of a SiGeC HBT on thin-film CMOS-compatible SOI, and a comprehensive study of its electrical behavior based on physical simulation and electrical characterization. Various aspects of the optimization of device performances are described, considering process or layout improvements. </para>

Influence of Interface Recombination in Light Emission from Lateral Si-Based Light Emitting Devices

The influence of interface recombination on the electroluminescence profile of a lateral p+/p/n+ light emitting diode fabricated on Silicon On Insulator (SOI) materials has been experimentally investigated. Our device resembles a MOSFET fabricated on SOI, except that the source region has opposite doping to the drain. By controlling the voltage bias at the poly gate on top of active emitting region in association with a bias on the silicon substrate under the active region we were able to diminish the non-radiative recombination component at Si/SiO2 interface and therefore enhance the radiative recombination in the thin film SOI. When the diode is working under constant current condition, we observe an increased light output of ~ 20 % as the gate and/or the substrate are biased negatively. The intensity profile across the device is also strongly influenced. To understand the device thoroughly, the structure has also been simulated showing agreement with experimental results.

Feasibility Study of a Novel Four Transistor Silicon-on-Insulator Static Random Access Memory Cell Utilizing Partial Trench Isolation

A novel static random access memory (SRAM) cell composed of four thin film silicon-on-insulator (TFSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) intended for 0.5 V operation is proposed. The body regions of the cross-coupled transistor pair are utilized as load resistors. Transfer MOSFETs connecting each SRAM cell to a word line are dynamic threshold MOSFETs (DTMOSs). By utilizing partial trench isolation, the need of special gate shapes for realizing body contacts is eliminated in the proposed SRAM cell. A device simulator with circuit analysis capability reveals that the proposed SRAM cell can be operated properly under a supply voltage of as low as 0.5 V.

Three-Dimensional Self-Assembled Sensors in Thin-Film SOI Technology

A complementary metal-oxide-semiconductor (CMOS)-compatible one-mask process for the design and fabrication of three-dimensional (3-D) microelectromechanical systems (MEMS) sensors in thin-film silicon-on-insulator (SOI) technology is presented. The process relies on the control of the internal stresses in multilayered structures originating from thermal expansion mismatch between layers as well as on the control of the plastic yielding of a metallic layer. In contrast with techniques presented in the literature for the fabrication of 3-D MEMS, this process requires fabrication steps and machines fully compatible with a classical CMOS process and available in standard CMOS foundries. Preliminary characterization results of 3-D thermal and flow sensors based on capacitive sensing demonstrate the potential of this concept

Bulk and surface micromachined MEMS in thin film SOI technology

Silicon-on-insulator (SOI) technology is emerging as a major contender for heterogeneous microsystems applications. In this work, we demonstrate the advantages of SOI technology for building thin film sensors on membranes as well as three-dimensional (3D) surface micromachined sensors and actuators. The flatness and robustness of the thin membrane as well as the self-assembling of 3D microstructures rely on the chemical release of the microstructures and on the control of the residual stresses building up in multilayered structures undergoing a complete thermal process. The deflection of multilayered structures made of both elastic and plastic thin films results from the thermal expansion coefficient mismatches between the layers and from the plastic flow of a metallic layer. The proposed CMOS-compatible fabrication processes were successfully applied to suspended sensors on thin dielectric membranes such as gas-composition, gas-flow and pressure sensors and to 3D self-assembled microstructures such as thermal and flow sensors.

Influence of Interface Recombination in Light Emission from Lateral Si-Based Light Emitting Devices

The influence of interface recombination on the electroluminescence profile of a lateral p+/p/n+ light emitting diode fabricated on Silicon On Insulator (SOI) materials has been experimentally investigated. Our device resembles a MOSFET fabricated on SOI (1), except that the source region has opposite doping to the drain. By controlling the voltage bias at the poly gate on top of active emitting region in association with a bias on the silicon substrate under the active region we were able to diminish the non- radiative recombination component at Si/SiO2 interface and therefore enhance the radiative recombination in the thin film SOI. When the diode is working under constant current condition, we observe an increased light output of ~ 20 % as the gate and/or the substrate are biased negatively. The intensity profile across the device is also strongly influenced. To understand the device thoroughly, the structure has also been simulated showing agreement with experimental results.

New thin-film power MOSFETs with a buried oxide double step structure

A new silicon-on-insulator (SOI) power MOSFET structure is proposed, in which buried oxide step structure (BOSS) is replaced by a buried oxide double step (BODS). Numerical simulations are performed to demonstrate that higher breakdown voltages are obtained resulting from a higher electric-field peak introduced near the BODS, and higher impurity concentration is depleted due to thin-film SOI than that in the conventional SOI and BOSS structure.