Thin Film Metal Layers Research Articles

Characterization of a thin-film metal-coated fiber optical phase modulator based on thermal effect with a nonlinear control interferometer

In this work, an optical fiber was coated by a thin-film metal layer to work as a fiber optical phase modulator based on thermal effect. This device was assembled in one of the arms of an all-fiber Michelson interferometer stabilized by a nonlinear control system based on variable structure and sliding modes. The frequency response reached 200 Hz, which can be considered high for a device based on the thermal effect. Compared with a fiber optical phase modulator based on the piezoelectric effect, the thermal modulator presented a higher scale factor per meter of optical fiber, showing the potential to work as a simple, low-cost, small-sized, short length, lightweight, and low-voltage fiber optical phase modulator.

Method for forming a titanium-germanium contact layer for thermostabilization of transistors

Objective. The objective of the study is to obtain high-quality and reproducible electrophysical parameters of thin-film metal layers, the formation technology of which determines the reliability and quality of microelectronic products – silicon transistors.Methods. A method for forming a two-layer titanium-germanium metallization to create a contact and remove heat from the collector junction of high-power semiconductor transistors on the reverse side of plates with formed structures is proposed. The proposed method ensures the quality of the soldered connection and thermal stabilization of semiconductor devices, increasing the reliability of the studied devices in radio electronic equipment systems.Results. This combination of sprayed metals provides a reliable contact to the collector area when the crystal is placed on the base of the case, which reduces the resistance of the ohmic transition and increases the output of suitable devices.Conclusion. Based on the results of experimental procedures, the optimal thicknesses of metal layers deposited on the reverse side of transistor crystals were obtained during the formation of metallization to fit crystals on the base of the case. The Ti-Ge system stability is studied. The technical result of the research is to improve the quality of planting by obtaining a uniform distribution of the Ti-Ge layer in a single technological cycle at a given temperature with a certain thickness for each metal separately.

Mobile microrobotic cleaner in microfluidics

Miniaturized mobile microrobots have opened new applications from biomedical to environmental fields. Among various types of microrobots, recent progress on highly performing planar type microrobots could offer a good compromise between the manufacturability and the functionality promising for practical applications. The remaining challenges are to guarantee their sustainable operations in unclean and wet environments where most of microrobots could suffer from being immobilized due to the increased risk of surface stiction. Our proposed microrobots made of thin-film metal layers with open surface are able to enhance the robustness of propulsion and manipulation thanks to the multiple modes of propulsion and manipulation which can serve as a fail-safe solution in uncontrolled environments. We successfully demonstrated that they are able to navigate in unclean environments and able to clean the environments with manipulation functionalities. This will no doubt be able to open various other applications which need similar level of the performance.

Characterization and Analysis of Metal Adhesion to Parylene Polymer Substrate Using Scotch Tape Test for Peripheral Neural Probe.

This paper presents measurement and FEM (Finite Element Method) analysis of metal adhesion force to a parylene substrate for implantable neural probe. A test device composed of 300 nm-thick gold and 30 nm-thick titanium metal electrodes on top of parylene substrate was prepared. The metal electrodes suffer from delamination during wet metal patterning process; thus, CF4 plasma treatment was applied to the parylene substrate before metal deposition. The two thin film metal layers were deposited by e-beam evaporation process. Metal electrodes had 200 μm in width, 300 μm spacing between the metal lines, and 5 mm length as the neural probe. Adhesion force of the metal lines to parylene substrate was measured with scotch tape test. Angle between the scotch tape and the test device substrate changed from 60° to 90° during characterization. Force exerted the scotch tape was recorded as the function of displacement of the scotch tape. It was found that a peak was created in measured force-displacement curve due to metal delamination. Metal adhesion was estimated 1.3 J/m2 by referring to the force peak and metal width at the force-displacement curve. Besides, the scotch tape test was simulated to comprehend delamination behavior of the test through FEM modeling.

Heavily-Doped Bulk Silicon Sidewall Electrodes Embedded between Free-Hanging Microfluidic Channels by Modified Surface Channel Technology.

Surface Channel Technology is known as the fabrication platform to make free-hanging microchannels for various microfluidic sensors and actuators. In this technology, thin film metal electrodes, such as platinum or gold, are often used for electrical sensing and actuation purposes. As a result that they are located at the top surface of the microfluidic channels, only topside sensing and actuation is possible. Moreover, in microreactor applications, high temperature degradation of thin film metal layers limits their performance as robust microheaters. In this paper, we report on an innovative idea to make microfluidic devices with integrated silicon sidewall electrodes, and we demonstrate their use as microheaters. This is achieved by modifying the original Surface Channel Technology with optimized mask designs. The modified technology allows to embed heavily-doped bulk silicon electrodes in between the sidewalls of two adjacent free-hanging microfluidic channels. The bulk silicon electrodes have the same electrical properties as the extrinsic silicon substrate. Their cross-sectional geometry and overall dimensions can be designed by optimizing the mask design, hence the resulting resistance of each silicon electrode can be customized. Furthermore, each silicon electrode can be electrically insulated from the silicon substrate. They can be designed with large cross-sectional areas and allow for high power dissipation when used as microheater. A demonstrator device is presented which reached at a power of , limited by thermal conduction through the surrounding air. Other potential applications are sensors using the silicon sidewall electrodes as resistive or capacitive readout.

Low-cost and low-topography fabrication of multilayer interconnections for microfluidic devices

Multilayer interconnections are needed for microdevices with a large number of independent electrodes. A multi-level photolithographic process is commonly employed to provide multilayer interconnections in integrated circuit devices, but it is often too expensive for large-area or disposable devices frequently needed for microfluidics. The printed circuit board (PCB) can provide multilayer interconnection at low cost, but its rough topography poses a challenge for small droplets to slide over. Here we report a low-cost fabrication of low-topography multilayer interconnects by selective and controlled anodization of thin-film metal layers. The process utilizes anodization of metal (tantalum in this paper) or, more specifically, repetitions of a partial anodization to form insulation layers between conductive layers and a full anodization to form isolating regions between electrodes, replacing the usual process of depositing, planarizing, and etching insulation layers. After verifying the electric connections and insulations as intended, the developed method is applied to electrowetting-on-dielectric (EWOD), whose complex microfluidic products are currently built on PCB or thin-film transistor substrates. To demonstrate the utility, we fabricate a three metal-layer EWOD device with steps (surface topography) less than 1 micrometer (vs. > 10 micrometers of PCB EWOD devices) and confirm basic digital microfluidic operations.

Extremely Short Length and High Extinction Ratio Plasmonic TE Mode Pass Polarizer

Extremely short length and ultrahigh extinction ratio TE pass polarizer is proposed for wavelength $1.55\mu \text{m}$ . The polarizer section consists of an optical dielectric waveguide separated from the thin metal film plasmonic guide by a low index buffer layer. The thin film metal layer supports only Short Range Surface Plasmon Polariton (SRSPP) because effective indices below and above the metal film are different. Periodic coupling between the SRSPP mode and the optical waveguide mode takes place and varies with the length of the polarizer. It is shown that for a properly optimized metal and the buffer layer thicknesses, an extinction ratio of 223 dB can be achieved for a polarizer of length $4.6~\mu \text{m}$ . Dependence of polarizer length on the optimized buffer and metal layers is also discussed.

A 3D-printed polymer micro-gripper with self-defined electrical tracks and thermal actuator

This paper presents a simple fabrication process that allows for isolated metal tracks to be easily defined on the surface of 3D printed micro-scale polymer components. The process makes use of a standard low cost conformal sputter coating system to quickly deposit thin film metal layers on to the surface of 3D printed polymer micro parts. The key novelty lies in the inclusion of inbuilt masking features, on the surface of the polymer parts, to ensure that the conformal metal layer can be effectively broken to create electrically isolated metal features. The presented process is extremely flexible, and it is envisaged that it may be applied to a wide range of sensor and actuator applications. To demonstrate the process a polymer micro-scale gripper with an inbuilt thermal actuator is designed and fabricated. In this work the design methodology for creating the micro-gripper is presented, illustrating how the rapid and flexible manufacturing process allows for fast cycle time design iterations to be performed. In addition the compatibility of this approach with traditional design and analysis techniques such as basic finite element simulation is also demonstrated with simulation results in reasonable agreement with experimental performance data for the micro-gripper.

System level IC packaging - Integration of Key Technologies: TSVs, Interposers, and Advanced IC Packaging

New system level IC package integration requires a flexible assembly portfolio. A review of current wafer scale processing and assembly solutions and new development directions is warranted. 2.5D TSV System level IC packaging is not new, but the performance levels that are being attained today with memory stacking, interposers, advanced silicon nodes and advanced packaging are new and are unparalleled. Several key technologies have come together to create this bold shift to higher performance. The Thru-Silicon Via (TSV) technology has been foremost, whether in the interposer, memory or logic devices, the importance of the this electrical pass through connection in silicon cannot be overstated. To commercialize the TSV package constructions, IC packaging technology had to be developed to permit its use. This included TSV reveal on TSV-bearing interposers, new ways of controlling warpage due to the presence of large x-y interposers, new functional IC bumping technologies and attachment methods. This portfolio of advanced technologies are then combined to provide package constructions that are increasingly compelling as a result of the higher electrical performance attained, while at the same time minimizing unwanted die to die interface power requirements. 2.5D TSV bearing products have enabled an array of multi-die products and have a significant role to play in the semiconductor industry going forward. Examples include new economics for SOC-splitting, and especially for combinations of logic and high speed memory (HBM), with performance levels heretofore unachievable. With fine line damascene Cu Back End of Line (BEOL) typical of a 65nm Cu backend, the signal routing resources available for multi-die implementation is unparalleled. Functionally, the TSV is required to provide a suitable power deliver network (PDN), and to enable off-package IO signaling. 3D TSV The COS Chip last is a proven approach for 2.5D TSV packages and is already in early production. This process flow is also being developed for 3D packages applications as well. New technologies being developed for 3D applications include new UF processing technologies that will be used to extend this technology to a 2-die stack with the same die size top and bottom, as well as 50 um large die silicon handling. These will include logic on logic combinations and memory on logic configurations, as well as stacked memory offerings. SLIMTM Amkor's most advanced integrated modular based package development program is for SLIMTM (Silicon-Less Integrated Module). The roots of SLIM innovation were forged during the 2.5D TSV-bearing interposer package development. SLIMTM attempts to retain all the best features of a 2.5D TSV interposer approach, but without bulk silicon for TSVs. The objective of SLIM is to retain the very strong signal routing capability afforded by the damascene BEOL, and provide that benefit without the requirement for a TSV. This can enable a lower total cost than the 2.5D interposers, and some specific electrical performance improvements as well. The primary mechanical feature of the SLIMTM construction is the lack of TSVs. For SLIM, the TSV is not in the electrical path from the top die to the C4, providing electrical benefits. In the case of SLIM the bulk silicon has been removed from the interposer, so that only the thin-film metal and dielectric layers present in the BEOL construction are retained. Connection to the BEOL metal stack is made directly using thin film techniques developed for 2.5D TSV. The end result is a very thin package, with signal routing resources on par with the 2.5D interposer, and without bulk silicon or a TSV. This can have electrical signaling advantage, especially for very high speed IO off package signals which avoid bulk silicon dielectric losses that can be significant above 20 Gigabit/sec. The process flow developed for SLIM is essentially a truncated version of the 2.5D production line. Key steps not required are CVD deposition of inorganic dielectrics and CMP processing. In summary, the final system package construction can be derived with different process approaches as previously discussed, each with their own particular benefits. Amkor continues in its commitment to the development of these critical process modules to enable customers to achieve their ultimate system-in-module product designs.

Bulk substrate porosity verification by applying Monte Carlo modeling and Castaing’s formula using energy-dispersive x-rays

The leadframe fabrication process normally involves additional thin-metal layer plating on the bulk copper substrate surface for wire bonding purposes. Silver, tin, and copper flakes are commonly adopted as plating materials. It is critical to assess the density of the plated metal layer, and in particular to look for porosity or voids underneath the layer, which may reduce the reliability during high-temperature stress. A fast, reliable inspection technique is needed to assess the porosity or void weakness. To this end, the characteristics of x-rays generated from bulk samples were examined using an energy-dispersive x-ray (EDX) detector to examine the porosity percentage. Monte Carlo modeling was integrated with Castaing’s formula to verify the integrity of the experimental data. Samples with different porosity percentages were considered to test the correlation between the intensity of the collected x-ray signal and the material density. To further verify the integrity of the model, conventional cross-sectional samples were also taken to observe the porosity percentage using Image J software measurement. A breakthrough in bulk substrate assessment was achieved by applying EDX for the first time to nonelemental analysis. The experimental data showed that the EDX features were not only useful for elemental analysis, but also applicable to thin-film metal layer thickness measurement and bulk material density determination. A detailed experiment was conducted using EDX to assess the plating metal layer and bulk material porosity.

Theoretical Study of Hybrid Guided Modes in a Multilayer Symmetrical Planar Plasmonic Waveguide

We presented a comprehensive theoretical study of the hybrid guided mode in a multilayer symmetrical planar plasmoinc waveguide, which is constructed with a thin film metal layer symmetrically sandwiched by three dielectric low/high/low-index layers. The seven-layer planar plasmonic structure can support super long-range plasmonic modes with strong subwavelength confinement in the low-index gap layer. We derived the dispersion equations for the guided mode and characterized the hybrid guided mode based on our derived analytical expressions. We explained how the variations in the thickness of the low-index gap and high-index cladding could change the types of the hybrid mode from strong surface plasmon polariton (SPP)-like mode, to SPP-dielectric waveguide (DW)-like mode, and further to strong-DW-like mode. We also found that by tailoring the geometric dimensions of the waveguide, the plasmonic mode of the multilayer structure can be optimized with the strongest mode confinement at the nanoscale gap. The combination of tight light confinement and long-range propagation length makes the seven-layer plasmonic waveguide an excellent candidate for applications in chip-scale plasmonic integrated circuits. The presented theoretical analysis shall be very useful in the design and optimization of active and passive nanoplasmonic devices.

Towards MEMS Pellistor Spectrometers

We report on an innovative use of high-temperature MEMS heater platforms as micro pellistor spectrometers. MEMS heater elements, initially designed for use as thermal infrared emitters, were fitted with thin-film noble metal layers to enable catalytic combustion processes on the hotplate surface. The modified heater platforms were operated in a range of combustible gas ambients while applying saw-tooth-like heater waveforms. Measurements of this kind revealed the heat of reaction vs. hotplate temperature profiles for each individual gas. We find that different families of gases yield distinctly different heat of reaction vs. temperature profiles and that these profiles allow the different families, and members inside some of these families, to be distinguished.

Silicon-based Micro Direct Methanol Fuel Cell Stack to Power Portable Devices Using MEMS Technology

A design configuration is presented for integrated series connection of micro direct methanol fuel cells in a planar array. The series path is oriented in a “flip-flop” configuration with electrical interconnections made by thin-film metal layers that coat the flow channels etched on the silicon substrate, presenting the unique advantage of small connection space and low connecting resistance. To overcome the disadvantage of “flip-flop” interconnection that reactant chambers must alternate between fuel and oxidant, an innovative reactant feeding configuration was designed, providing a uniform reactant feeder and reliable hermetic seals for a multitude of unit cavities per cell. The MEMS fabrication process was adopted to fabricate the silicon plates. The elements of reactant feeder were mechanically carved from PMMA and were assembled with the cells by agglutinant. Application of μDMFC stacks as portable power sources were demonstrated using small electric devices powered by this stack.

J114035 薄膜導電性高分子材料を用いたマイクロ通電加熱システムの基礎検討([J114-03]次世代アクチュエータシステム(3))

Fundamental mechanical characteristics of a small actuator using thermal expansion of a conductive polymer have been investigated. The conductive polymer layer (t30 μm) of a polythiophene type (SEPLEGYDA, Shin-Etsu Polymer Co.) is coated on a thin film polyimide diaphragm (φ5 mm, t10 μm). The polyimide diaphragm is deflected by the thermal expansion of the conductive polymer when an electric current is applied to the polymer. Thin film metal layer such as aluminum has been used as a conductive layer in conventional thermal expansion actuators. Merits of using the conductive polymer are, for example, flexibility of the actuator, ease of the fabrication without using heat process; a diaphragm of a low heat-resistance material can also be used. The relationship between the temperatures and the displacements at the diaphragm center was measured and compared with those of the actuators using other conductive layers fabricated on the diaphragm such as vapor-deposited aluminum (t0.1 μm) and sputtered ITO (Indium Tin Oxide, t0.1μm). The results show that the actuator using the conductive polymer has the temperature-displacement characteristics almost similar to that using the aluminum layer.

Design and fabrication of light weight current collectors for direct methanol fuel cells using the micro-electro mechanical system technique

The direct methanol fuel cell (DMFC) is suitable for portable applications. Therefore, a light weight and small size is desirable. The main objective of this paper is to design and fabricate a light weight current collector for DMFC usage. The light weight current collector mainly consists of a substrate with two thin film metal layers. The substrate of the current collector is an FR4 epoxy plate. The thin film metal layers are accomplished by the thermo coater technique to coat metal powders onto the substrate surfaces. The developed light weight current collectors are further assembled to a single cell DMFC test fixture to measure the cell performance. The results show that the proposed current collectors could even be applied to DMFCs because they are light, thin and low cost and have potential for mass production.

Photolithographic patterning of polymer-encapsulated optical oxygen sensors

In this paper we show a novel fabrication process capable of yielding arbitrarily-shaped optical oxygen sensor patterns at micron resolution. The wafer-level process uses a thin-film sacrificial metal layer as intermediate mask, protecting the sensor material and enabling the use of conventional semiconductor patterning techniques. Feature sizes down to 3 μm are demonstrated and only limited by the lithographic process. Gaseous oxygen detection using the patterned sensors shows Stern–Volmer behaviour with a measured intensity ratio I 100/ I 0 of 10.8, the highest reported for a lab-on-a-chip compatible glass substrate. The process has the potential to enable the integration of multiple sensor patches underneath single cells for laterally registered oxygen sensing in cell-culture applications.

Near-field excitation and near-field detection of propagating surface plasmon polaritons on Au waveguide structures

The propagation of surface plasmon polaritons guided along Au metal waveguides fabricated by electron-beam lithography is experimentally investigated using simultaneous near-field excitation and detection of plasmon-polariton modes localized at the air/Au interface. The directly measured propagation characteristics of surface plasmon-polaritons agree well with simulation results obtained using full-vector calculations and the analytic dispersion of asymmetric plasmonic waveguides for thin Au films. Our results demonstrate that near-field excitation/detection schemes are well suited for direct imaging and characterization of propagating surface plasmon-fields bound to thin-film metal layers, and can be used for fast and reliable characterization of plasmonic waveguide elements and nanodevices.

Review of add-on process modules for high-frequency silicon technology

Add-on process modules as enhancements for standard high-frequency silicon integration processes are discussed. Such modules can cost-effectively be added without any interference with the core process before (pre-process modules), during (mid-process modules), or after (post-process modules) the circuit integration. In addition, layout options providing a most cost-effective means of enhancement are discussed. High-resistivity silicon substrates, ferromagnetic thin-film integration, bulk micromachining, saddle-add-on metallization, spacer-substrate integration, and metal layer shunting are presented as examples in those categories.

Microwave bonding of polymer-based substrates for potential encapsulated micro/nanofluidic device fabrication

Microwave-based bonding of polymer substrates is presented in this paper to illustrate a promising technique for achieving precise, localized, low temperature bonding. Microwave power can absorbed by a very thin film metal layer deposited on a polymer (PMMA) substrate surface. The intense thin-film volumetric heating promotes localized melting of refractory metals such as gold. One of the advantages of the process is that PMMA is relatively transparent to microwave energy in the 2.4 GHz regime. This makes it an excellent substrate material for microwave bonding. Selective heating and melting of the thin layers of metal also causes localized melting of the PMMA substrates and improves adhesion at the interface. We have shown that ∼1 μm of interfacial layer can be generated that is composed of the melted gold and PMMA, and which can hold two substrates together under applied tension greater than 100 lb/in. 2 (7 kg/cm 2). We also used lithographically patterned metal lines on a PMMA substrate to demonstrate that the PMMA remains optically transparent after microwave processing. A numerical simulation was also performed and validated with experimental results to show that globally the PMMA substrates indeed remained below its melting point during the microwave bonding process. The novel bonding process will open up possibilities for precise and total encapsulation of polymer-based micro/nanofluid devices—which are impossible to built using existing polymer bonding techniques.

Design and fabrication of a micro fuel cell array with “flip-flop” interconnection

A design configuration is presented for integrated series connection of polymer electrolyte fuel cells in a planar array. The design is particularly favorable for miniature fuel cells and has been prototyped using a variety of etch and deposition techniques adopted from microfabrication. The series path is oriented in a “flip-flop” configuration, presenting the unique advantage of a fully continuous electrolyte requiring absolutely no interconnecting bridges across or around the membrane. Electrical interconnections are made by thin-film metal layers that coat etched flow channels patterned on an insulating substrate. Both two-cell and four-cell prototypes have successfully demonstrated the expected additive performance of the integrated series, and peak power in a four-cell silicon assembly with hydrogen and oxygen has exceeded 40 mW/cm 2. Factorial experimentation has been applied to investigate the adequacy of metal film conduction over etched topology, and results conclude that film thickness dominates over other design parameters. The design effort and subsequent testing has uncovered new topics for extended study, including the possibility of lateral ionic conduction within the membrane as well as the effects of non-uniform reactant distribution.