Thin-body Devices Research Articles

A Threshold Voltage Definition Based on a Standardized Charge Versus Voltage Relationship

Threshold voltage defined by a band bending of twice the substrate intrinsic-to-Fermi level difference has been widely accepted. However, there are shortcomings with this analytical definition. Since the inversion condition is governed by the substrate Fermi level (i.e., majority carrier density per volume), inversion carrier density per area at threshold inadequately depends on substrate doping and temperature. Another problem is that the definition is not applicable to fully depleted thin body devices, such as FinFETs and silicon-on-insulator FETs, widely used today. To solve these problems, a new definition of threshold voltage is proposed, which is based on a standardized charge versus voltage relationship of ideal metal-oxide-semiconductor capacitors. Threshold voltage is specified by a threshold inversion carrier density per area, which is a simple function of gate oxide capacitance and thermal voltage. Dependence of the proposed threshold voltage on substrate doping, body thickness, and temperature for both bulk and double-gate FETs is discussed using semi-classical analytical equations.

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory.

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory's data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, "0" state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

Optimization Considerations for Short Channel Poly-Si 1T-DRAM

Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Generally, when the gate length of a silicon-on-insulator (SOI) structure metal-oxide-silicon field-effect transistor (MOSFET) is reduced, its body thickness is reduced in order to suppress the short-channel effects (SCEs). TCAD device simulations were used to investigate the transient performance differences between thin and thick-body poly-Si DRAMs to determine whether reduced body thickness is also appropriate for those devices. Analysis of the simulation results revealed that operating bias conditions are as important as body thickness in 1T-DRAM operation. Since a thick-body device has more trapped hole charge in its grain boundary (GB) than a thin-body device in both the “0” and “1” states, the transient performance of a thick-body device is better than a thin-body device regardless of the Write”1” drain voltage. We also determined that the SCEs in the memory cells can be improved by lowering the Write”1” drain voltage. We conclude that an optimization method for the body thickness and voltage conditions that considers both the cell’s SCEs and its transient performance is necessary for its development and application.

Multi-threshold voltages in ultra thin-body devices by asymmetric dual-gate structure

Control of threshold voltage (VT) by asymmetric dual-gate structure is investigated. Two separated gates are successfully fabricated through two-step chemical mechanical polishing (CMP) processes. Silicon fin width is determined as same as the thickness of oxide sidewall spacer. VT of the device is modulated by how many charges are trapped in the nitride layer of the second gate stack (G2) through applying programming pulses to G2. They affect the formation of electron channel on the first gate (G1) side. Additionally, the efficiency of this technique is analyzed by simple capacitance network. The thinner body is the more effective the proposed VT control method is. It is noteworthy that this method can be used without ultra thin buried oxide (BOX) structure and additional biasing scheme.

A new formulation for surface roughness limited mobility in bulk and ultra-thin-body metal–oxide–semiconductor transistors

This paper presents a new model for the surface roughness (SR) limited mobility in MOS transistors. The model is suitable for bulk and thin body devices and explicitly takes into account the non linear relation between the displacement Δ of the interface position and the SR scattering matrix elements, which is found to significantly influence the r.m.s value (Δrms) of the interface roughness that is necessary to reproduce SR-limited mobility measurements. In particular, comparison with experimental mobility for bulk Si MOSFETs shows that with the new SR scattering model a good agreement with measured mobility can be obtained with Δrms values of about 0.2 nm, which is in good agreement with several AFM and TEM measurements. For thin body III–V MOSFETs, the proposed model predicts a weaker mobility degradation at small well thicknesses (Tw), compared to the Tw6 behavior observed in Si extremely thin body devices.

PHYSICS BASED ANALYTICAL MODELING OF NANOSCALE MULTIGATE MOSFETs

Various physics based modeling schemes for multigate MOSFETs are presented. In all cases, the models are derived from an analysis of the device body electrostatics in terms of two- or three-dimensional Laplace's and Poisson's equations, where short-channel and scaling effects are implicitly accounted for. Thus a comprehensive modeling framework is derived for the subthreshold electrostatics of double-gate MOSFETs based on a conformal mapping analysis of the potential distribution in the device body arising from the inter-electrode capacitive coupling. This technique is also applied to the circular gate-all-around MOSFET by utilizing the symmetry properties of this device. For both these devices, the modeling is extended to include the strong inversion regime by a self-consistent procedure that simultaneously allows the calculation of the quasi-Fermi potential distribution, the drain current, and the intrinsic capacitances. In an alternative modeling framework, covering a wide range of multigate devices in a unified manner, the potential distribution is derived from a select set of isomorphic trial functions that reflect the geometry and symmetry properties of the devices. Modeling parameters used are self-consistently determined by imposing boundary conditions associated with Laplace's or Poisson's equation. Finally, the effects of quantum mechanical confinement are discussed for ultra thin body devices. The results of the modeling are in excellent agreement with numerical simulations.

Nano Scale Soi Mosfet Structures and Study of Performance Factors

This paper proposes a study related with the downscaling trend in CMOS devices. Some of the structural variants of the MOSFET have been explored and the key performance factors as gate tunneling current, transconductance and output conductance are discussed. The impact of energy quantization on gate tunneling current is studied for double-gate and ultra thin body MOSFETS. Reduced vertical electric field and quantum confinement in the channel of these thin-body devices causes a decrease in gate leakage. Very high transconductance, approaching the ballistic limit, can be achieved provided that technological improvements further increase the electron mobility in the silicon film. The output conductance and Early voltage are severely affected by length scaling as channel length-modulation (CLM) and drain-induced barrier lowering (DIBL) effects become more important, but they are acceptable for channel lengths above 15 nm. . Sanjeev Jain Ssvps Bsd College Of Engg. Vidyanagari Deopur, Dhule Prasad Vinchurkar Ssvps Bsd College Of Engg. Vidyanagari Deopur, Dhule The full text of the article is not available in the cache. Kindly refer the IJCA digital library at www.ijcaonline.org for the complete article. In case, you face problems while downloading the full-text, please send a mail to editor at editor@ijcaonline.org

Influence of the epitaxial growth and device processing on the overlay accuracy during processing of the d-DotFET

To maintain the development of MOSFET devices in the last three decades the lateral layout of this important device was scaled down into the sub-50 nm range. The challenge to maintain device performance was met by applying to scaling rules, which ensure a proper physical behaviour in the active area of the device. But nowadays new device architectures as Ultra Thin Body and Multi Gate devices have to be discussed. Furthermore new materials were introduced as high-κ gate dielectrics and metal gates. In recent years strained silicon has drawn increasing attention to enlarge carrier mobility in the MOSFET channel. In the d-DotFET approach locally strained silicon is formed by means of template-assisted self assembly of Ge-dots and silicon overgrowth. The silicon capping layer is strained on top of the dot and in its near vicinity, only. The accurate positioning of the dots on pre-patterned substrates enables the utilization of these substrates for further device processing. The crucial issue is to integrate the active area on top of the dot, which requires an overlay of ± 10 nm, which has to be assured over the whole process. In this paper we investigate the intrinsic overlay of a Vistec EBPG 5000 plus e-beam system using etched holes in silicon as markers. It was found, that the required overlay accuracy can be obtained, when the definition of the marker sites is adapted to the following process, already. The overlay is not affected by device processing, as long as the markers are affected symmetrically.

Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solution

This work proposes a planar fully depleted “folded” technology integrated on bulk substrate as an innovative solution for upcoming low power nodes to enhance drive current on narrow devices. We report a detailed fabrication method, combining advanced selective epitaxy faceting and SON (Silicon-On-Nothing) process, to provide ultra thin body and buried oxide (UTB 2) devices with improved drive current I on for a given designed footprint W design when scaling the device width . We compare the fabrication and electrical behavior between 〈1 1 0〉 channel, i.e. 0°-rotated wafer, and 〈1 0 0〉 channel, i.e. 45°-rotated wafer, for the same (1 0 0) surface orientation.

Quantum compact model for thin-body double-gate Schottky barrier MOSFETs

Nanoscale Schottky barrier metal oxide semiconductor field-effect transistors (MOSFETs) are explored by using quantum mechanism effects for thin-body devices. The results suggest that for small nonnegative Schottky barrier heights, even for zero barrier height, the tunnelling current also plays a role in the total on-state current. Owing to the thin body of device, quantum confinement raises the electron energy levels in the silicon, and the tradeoff takes place between the quantum confinement energy and Schottky barrier lowering (SBL). It is concluded that the inclusion of the quantum mechanism effect in this model, which considers an infinite rectangular well with a first-order perturbation in the channel, can lead to the good agreement with numerical result for thin silicon film. The error increases with silicon thickness increasing.

Ultra-thin fully-depleted SOI MOSFETs: Special charge properties and coupling effects

A standard characterization method in fully depleted SOI devices consists in biasing the back interface in the accumulation regime, and measuring the front-channel properties. In ultra thin body device however, it is sometimes no longer possible to achieve such an accumulation regime at the back interface. This unusual effect is investigated by detailed simulations and analytical modelling of the potential and electron/hole concentrations. The enhancement of the interface coupling effect in ultra thin body devices, called super-coupling, can explain previously published experimental data [Pretet J, Ohata A, Dieudonne F, Allibert F, Bresson N, Matsumoto T, et al. Scaling issues for advanced SOI devices: gate oxide tunneling, thin buried oxide, and ultra-thin films. In: 7th International symposium silicon nitride and silicon dioxide thin insulating films, Paris, France, 2003. Electrochemical Society Proceedings, vol. 2003-02, Pennington (USA); 2003. p. 476–87], and reveals new challenges in the characterization of advanced SOI devices.

Impact of device physics on DG and SOI MOSFET linearity

The influence of different physical mechanisms on MOSFET linearity is analyzed using 2D TCAD device simulations. In particular, the RF linearity performance of 50 nm gate length SOI and DG-MOSFETs are investigated and compared with traditional bulk MOSFETs. We employ the hydrodynamic (HD) transport model to account for non-equilibrium carrier dynamics and the density gradient approximation for quantum mechanical effects. Impact ionization of channel carriers and self-heating effect (SHE) are also accounted for in the thin-body devices. Our results disclose the relationship between various aspects of device physics and linearity. We show that linearity performance is particularly sensitive to non-local effects and are lowered due to SHE. Quantum mechanical effects appear to have a small positive impact on linearity. Drift-diffusion approximation is found to be unreliable for linearity analysis of DG MOSFETs due to large overestimation from this model. We also observe that linearity has an anomalous monotonous dependence on the ambient temperature.

Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs

Gate-induced drain leakage (GIDL) current is investigated in single-gate (SG) ultra-thin body field effect transistor (FET), symmetrical double-gate (DG) FinFET, and asymmetrical DG metal oxide semiconductor field effect transistor (MOSFET) devices. Measured reductions in GIDL current for SG and DG thin-body devices are reported for the first time. The thin-body devices exhibit much lower GIDL current than bulk-Si MOSFETs, and the GIDL is found to decrease with decreasing body thickness. These results can be explained by the reduction in transverse electric field at the surface of the drain and the increase in transverse effective mass with decreasing body thickness.

Direct-tunneling gate leakage current in double-gate and ultrathin body MOSFETs

The impact of energy quantization on gate tunneling current is studied for double-gate and ultrathin body MOSFETs. Reduced vertical electric field and quantum confinement in the channel of these thin-body devices causes a decrease in gate leakage by as much as an order of magnitude. The effects of body thickness scaling and channel crystallographic orientation are studied. The impact of threshold voltage control solutions, including doped channel and asymmetric double-gate structures is also investigated. Future gate dielectric thickness scaling and the use of high-/spl kappa/ gate dielectrics are discussed.

An experimental study on transport issues and electrostatics of ultrathin body SOI pMOSFETs

We present an experimental study of the transport properties (low field hole mobility /spl mu//sub h/) and electrostatics (threshold voltage V/sub th/, and gate-to-channel capacitance C/sub gc/) of ultrathin body (UTB) SOI pMOSFETs using a large RingFet structure. Body thicknesses were /spl sim/4.3 nm to 50 nm. We find that 1) hole mobility decreases significantly as T/sub Si/<10 nm, and tends to show negligible dependence on the transverse electric field for extremely thin T/sub Si/ (<6 nm) and 2) a V/sub th/ shift of /spl sim/150 mV occurs over the studied T/sub Si/ range, accompanied by enhancement of weak inversion capacitance in thin body devices. Simulations were performed to provide insight into the experimental observations.