Thick Silicon Wafer Research Articles

Fracture strength analysis of large-size and thin photovoltaic monocrystalline silicon wafers

Diamond wire slicing technology is the main method to manufacture the substrate of the monocrystalline silicon-based solar cells. With the development of technology, the size and thickness of monocrystalline silicon wafer are respectively getting larger and thinner, which cause an increase in silicon wafer fracture probability during wafer processing and post-processing. And the change of the sawing speed, saw wire diameter and abrasive size also affect the wafer’s surface characteristics, thereby affect its fracture strength. In this paper, monocrystalline silicon wafer with large size of 210 mm × 210 mm was taken as the research object, 4-point bending test was carried out on each series of silicon wafers. The load–displacement curves during bending test were collected, and the fracture stress values were calculated by finite element method. The characteristic fracture strength and Weibull modulus of each series of silicon wafers were obtained through the statistical analysis of the data using Weibull distribution function. The effect of the silicon wafer thickness, the position of the silicon wafer in the silicon brick (usage time of the saw wire varies), and the bending test direction on the fracture characteristics was analyzed. The results showed that the increase of thickness increase the characteristic fracture strength of silicon wafer. The characteristic fracture strength of the front wafers (sawn by the fresh wire) is the smallest, while the characteristic fracture strength of the middle wafers and the rear wafers (sawn by the worn wire) are similar. The characteristic fracture strength of bending in the direction of perpendicular to the saw marks is 2–3 times that of bending in the direction of parallel to the saw marks. The reason of the difference of characteristic fracture strength was analyzed based on the surface morphology, roughness, and the saw marks of silicon wafer. In this paper, the fracture characteristics of large size monocrystalline silicon wafer are studied to provide fracture data support for industry production. The mechanism and main effect factors of silicon wafer fracture are revealed, which provides directions for improving the sawing quality and reducing the fracture probability during wafer production process and post-processing.

A New Silicon Mold Process for Polydimethylsiloxane Microchannels.

As an alternative to SU-8 soft lithography, a new silicon mold process of fabricating PDMS microchannel chips was proposed. A picosecond laser is used to cut through a 550 μm thick silicon wafer and generate the original microchannel pattern with a 50 μm minimum feature size. This single-crystal silicon pattern, with the edge debris caused by laser cutting being trimmed off by a KOH solution and with the protection field oxide layer being removed by BOE afterwards, firmly resided on a glass substrate through the anodic bonding technique. Four-inch wafers with microchannel patterns as the PDMS mold cores were successfully bonded on Pyrex 7740 or Eagle XG glass substrates for the follow-up PDMS molding/demolding process. This new maskless process does not need a photolithography facility, but the laser cutting service must be provided by professional off-campus companies. One PDMS microchannel chip for particle separation was shown as an example of what can be achieved when using this new process.

Spray mist-assisted drilling of through silicon vias (TSV) using nanosecond laser: Influence of CNT nanofluid

Through Silicon Vias (TSV) are crucial in semiconductor technology for vertically connecting multiple stacks in 3D packaging. High aspect ratio, smooth and slightly tapered TSVs enhance layout efficiency and void-free filling. Being contact-less and dry-etching process, laser machining is a promising technique to fabricate TSVs. A percussion laser drilling approach was used to fabricate TSVs on a 500 μm thick silicon wafer with a 1064 nm ns laser. Four environments such as air, compressed air jet, water mist, carbon nanotube (CNT) fluid mist were employed to assess laser machining effects on TSV performance in terms of entrance and exit diameters, recast layer, side wall damage, and taper angle. Optimized process parameters (laser pulse energy and pulse number) were derived from an ANN prediction model. Laser drilling under CNT mist produced relatively circular (entrance diameter), straight, and clean TSVs. Reduced debris redeposition was observed under air jet, water mist, and CNT mist compared to air. Minimal sidewall damage occurred under water mist and CNT mist as compared to those machined in air and air jet. CNT mist yielded TSVs with less recast layer (∼7 μm), taper angle (∼1.05 deg.), and heat affected zone (HAZ) thickness (∼50 μm). Enhanced machining quality may be attributed to increased thermal conductivity of CNT nanofluid and pressurized mist flow rate, improving cooling and debris removal. Furthermore, a detailed investigation of TSV using SEM was performed and the findings were compared to those of other research groups.

An experimental investigation of spin-on doping optimization for enhanced electrical characteristics in silicon homojunction solar cells: Proof of concept

The pursuit of enhancing the performance of silicon-based solar cells is pivotal for the progression of solar photovoltaics as the most potential renewable energy technologies. Despite the existence of sophisticated methods like diffusion and ion implantation for doping phosphorus into p-type silicon wafers in the semiconductor industry, there is a compelling need to research spin-on doping techniques, especially in the context of tandem devices, where fabricating the bottom cell demands meticulous control over conditions. The primary challenge with existing silicon cell fabrication methods lies in their complexity, cost, and environmental concerns. Thus, this research focuses on the optimization of parameters, such as, deposition of the spin on doping layer, emitter thickness (Xj), and dopant concentration (ND) to maximize solar cell efficiency. We utilized both fabrication and simulation techniques to delve into these factors. Employing silicon wafer thickness of 625 μm, the study explored the effects of altering the count of dopant layers through the spin-on dopant (SOD) technique in the device fabrication. Interestingly, the increase of the dopant layers from 1 to 4 enhances efficiency, whereby, further addition of 6 and 8 layers worsens both series and shunt resistances, affecting the solar cell performance. The peak efficiency of 11.75 % achieved in fabrication of 4 layers dopant. By using device simulation with wxAMPS to perform a combinatorial analysis of Xj and ND, we further identified the optimal conditions for an emitter to achieve peak performance. Altering Xj between 0.05 μm and 10 μm and adjusting ND from 1e+15 cm−3 to 9e+15 cm−3, we found that maximum efficiency of 14.18 % was attained for Xj = 1 μm and ND = 9e+15 cm−3. This research addresses a crucial knowledge gap, providing insights for creating more efficient, cost-effective, and flexible silicon solar cells, thereby enhancing their viability as a sustainable energy source.

Fabrication of Ordered Macropore Arrays in n-Type Silicon Wafer by Anodic Etching Using Double-Tank Electrochemical Cell.

In this work, ordered macropore arrays in n-type silicon wafers were fabricated by anodic etching using a double-tank electrochemical cell. The effects of the wafer thickness, etching time and voltage on the quality of macropore arrays were investigated. Homogeneous macropore arrays could be achieved in 200 μm thick silicon wafers, but could not be obtained from 300 and 400 μm thick silicon wafers. Highly ordered macropore arrays with an aspect ratio of 19 were fabricated in 200 μm thick n-type silicon at 4.5 V. The etching current decreases in 200 μm thick silicon but increases in thicker silicon with an increase in time. It demonstrates that the minority carrier transportation capability from the illuminated surface to the reactive surface is different for silicon wafers with different thicknesses. The minority carrier concentration at the illuminated surface for stable macropore formation and the current under different etching voltages were calculated based on a hole transport model. The results show that appropriately decreasing wafer thickness and increasing voltage can help stable macropore array fabrication in the illumination-limited double-tank cell.

Design of back-contact interface of Cu(In,Ga)Se<sub>2</sub> solar cells by single-target magnetron sputtering

Thin-film solar cells provide an opportunity to reduce the cost of converting solar energy into electricity by replacing expensive and thick silicon wafers, which account for more than 50% of the total cost of photovoltaic (PV) modules. However, many thin-film solar cell materials result in low PV performance due to enhanced recombination through defect states. Cu(In,Ga)Se<sub>2</sub> (CIGS) is a promising thin-film solar cell material due to its direct tunable bandgap, high absorption coefficient, low effective electron and hole mass, and abundant constituent elements. Among them, magnetron sputtering or selenization technology is widely used to catch up with the development of preparing large-area CIGS thin-film solar cells because of its uniform film composition and simple process. However, the use of toxic gases such as H<sub>2</sub>Se and H<sub>2</sub>S and the difficulty in forming gradient bandgaps limit their development. In this work, the “V” Ga gradient classification of the absorbing layer of CIGS solar cells is realized by sputtering CuGaSe<sub>2</sub> (CGS) thin layers of different thickness values in the room temperature layer by sputtering and selenium-free methods of quaternary target sputtering. Firstly, the microstructure of the film is characterized by scanning electron microscope, X-ray diffraction, Raman and X-ray photoelectron spectroscopy, and when the CGS layer is located in the middle of the low-temperature layer, the grain size of the film is the largest, the crystallinity is the best, forming a “V-shaped” structure of CGI on the back of the absorbing layer. Subsequently, IV and external quantum efficiency (EQE) tests show that the optimized cell efficiency is as high as 15.04%, and the light response intensity is enhanced in the 300 －1200 nm band. Finally, the admittance spectrum(AS) test shows that the defect energy level of the solar cell changes from In<sub>Ga</sub> defect to <i>V</i><sub>Cu</sub> defect of lower energy level, and the defect density decreases from 7.04×10<sup>15</sup> cm<sup>–3</sup> to 5.51×10<sup>15</sup> cm<sup>–3</sup>. This is comparable to the recording efficiency of the current single-target magnetron sputtering CIGS solar cells, demonstrating good application prospects.

The Fabrication and Characterization of Silicon Surface Grooving Using the CV Etching Technique for Front Deep Metallic Contact Solar Cells

This study experimentally investigated the use of the chemical vapor etching method for silicon surface grooving for regular front deep metallic contact solar cell applications. The thickness of silicon wafers is a crucial parameter in the production of solar cells with front and back buried contacts, because silicon surface grooves result in a larger contact area, which in turn improves carrier collection and increases the collection probability for minority carriers. A simple, low-cost HNO3/HF chemical vapor etching technique was used to create grooves on silicon wafers with the help of a highly effective anti-acid mask. The thick porous layer of powder that was produced was easily dissolved in water, leaving patterned grooved areas on the silicon substrate. A linear dependence was observed between the etched thickness and time, suggesting that the etching process followed a constant etch rate, something that is crucial for ensuring precise and reproducible etching results for the semiconductor and microfabrication industries. Moreover, by creating shorter pathways for charge carriers to travel to their respective contacts, front deep contacts minimize the overall distance they need to traverse and therefore reduce the chance of carrier recombination within the silicon material. As a result, the internal quantum efficiency of solar cells with front deep metallic contacts improved by 35% compared to mc-Si solar cells having planar contacts. The use of front deep contacts therefore represents a forward-looking strategy for improving the performance of silicon solar cells. Indeed, this innovative electrode configuration improves charge carrier collection, mitigates recombination losses, and ultimately leads to more efficient and effective solar energy conversion, which contributes to sustainable energy development in the areas of clean energy resources. Further work needs to be undertaken to develop energy sustainably and consider other clean energy resources.

Research on silicon wafer surface phase under the Ultra-thin slicing process and its etching hindrance behavior during metal-assisted chemical etching

Ultra-thin silicon slicing technology plays a critical role in achieving high-efficiency and low-cost solar cells in the photovoltaic (PV) industry. However, the surface phase evolution of silicon wafers under an ultra-thin slicing process and resulting etching behavior remains unclear. In this study, the surface phase evolution of different surface thicknesses of silicon wafers was carefully studied. As the thickness of silicon wafers became relatively thin, the degree of surface stress-induced amorphous silicon (ST-α-Si) significantly increased. Moreover, the UPS test showed that the ST-α-Si layer had an orbital energy level relatively lower than that in monocrystalline silicon, thereby having lower reduction performance during metal-assisted chemical etching (MACE). A copper deposition experiment was conducted to study the etching hindering effect caused by silicon surface ST-α-Si phases. The result showed that the presence of ST-α-Si adversely affected copper deposition. To improve the MACE uniformity, a pretreatment involving the use of HF/H2O2 mixed solution to remove the surface ST-α-Si layer was investigated. After HF/H2O2 pretreatment, the uniformity of inverted pyramids formed through MACE on the silicon wafer surface was significantly improved. Moreover, the reflectance of the MACE-textured surface was reduced to 7.67 % from 10.1 % compared with that without pretreatment. Therefore, this study provides reference guidelines and useful approaches for preparing uniform inverted pyramid surfaces using MACE in ultra-thin silicon wafers.

VIS-NIR TMOKE enhanced dielectric-metal hybrid structure for high performance dual-channel sensing.

Magneto-plasmon sensors based on the transverse magneto-optical Kerr effect (TMOKE) have been extensively studied in recent years. In this paper, we theoretically propose a hybrid structure composed of a one-dimensional bismuth iron garnet: yttrium iron garnet (BIG: YIG) nanowire arrays and thin film stack, which is grown on an infinite thick silicon wafer. The thin film stack, from top to bottom, consists of the following layers: BIG: YIG, SiO2, and Au. By exciting the magnetic dipole resonance mode between the cylindrical nanowires and the SPP mode on the surface of the Au film, dual-channel sensing has been achieved in both visible and infrared spectra. The results demonstrate that the TMOKE response spectrum of the structure supports ultra-narrow linewidths of 0.03 nm in the visible light range and 1.54 nm in the infrared range. By changing the refractive index of the analyte, the detected sensitivity of the sensor system in visible and infrared bands is 553 nm RIU-1 and 285 nm RIU-1, and the Figure of merit (FOM) can reach up to 69125 RIU-1 and 303 RIU-1, respectively. This work provides a theoretical basis and a feasible approach for the design of dual channel gas sensors.

Simulation study and parameter optimization of laser TSV using artificial neural networks

Through-Silicon Vias (TSV) play an important role in the field of semiconductor 3D packaging by providing interconnections during layer-by-layer stacking. Laser machining of TSVs is advantageous over expensive photolithography steps in the DRIE process. It is environmentally friendly, reduces production costs, and increases throughput. In this study, a nanosecond laser (100 ns, 1064 nm) was used to produce TSVs on a 500 μm thick silicon wafer, and the effects on parameters such as drilling depth, aspect ratio, taper angle, and heat-affected zone (HAZ) were investigated in air. Furthermore, an optimized circle-packing design between pulse energy (E) and the number of pulses (N) was constructed. The developed computational model was employed to run simulations to predict the drilling depth, aspect ratio, taper angle, and HAZ. Subsequently, the obtained results were used to train surrogate models for all individual parameters in the given range. A final processing map was created by combining all the individual surrogate models and filtered with four criteria to obtain the optimized region with proper drilling depth, less taper angle, high aspect ratio, and comparatively less HAZ TSVs. Lastly, points were chosen from each region, and experiments were performed to validate the optimized zone, and full agreement was found with the simulation results. With this optimized zone, TSVs with a higher aspect ratio (11.72), less taper angle (1.37°), and comparatively less HAZ thickness (10.48 μm) were achieved for the combination of pulse energy at 0.3614 mJ and pulse number at 835.

One-channel time reversal focusing of ultra-high frequency acoustic waves on a MEMS

This Letter reports on a work performed to fabricate and characterize a silicon micro-machined cavity dedicated to micro-resolution Ultra-High Frequency imaging in microfluidics and microbiological applications using one-channel time reversal. Time reversal provides the means to spatially and temporally localize elastic energy on a receiver. Here, the arrays of zinc oxide micro transducers are coupled with a 400 μm thick silicon wafer containing micromachined structures for acoustical field confinement. Characterization of the diffused acoustic field and time-reversal retro-focusing are reported. The transducers are wideband in the 0.2–2 GHz range with a central frequency of 0.9 GHz.

Theory of dielectric photonic crystals sandwiched between parallel metal plates

Photonic crystals based on silicon-air-geometries sandwiched between parallel metal plates are studied theoretically. Compared with in-plane propagation in corresponding infinite-height photonic crystals, modes with one of the two possible polarizations are eliminated for small plate separations. Consequently, 2D photonic crystals that usually do not have a band gap for both polarizations possess a complete band gap in the sandwich geometry. A procedure for obtaining the maximum allowed photonic-crystal height between plates that preserves the in-plane band gap is described. The effect on the band gap of adding an air-gap or a silicon substrate to the photonic crystal structure between plates is also studied. Finally, it is shown that, for terahertz frequencies, a useful distance between metal plates is comparable to the thickness of thin silicon wafers, and that propagation losses are sufficiently small that the structures are of practical interest. We briefly discuss the numerical method that was used for calculating band diagrams and band gaps, which is based on a modification to the plane-wave-expansion method [R. D. Meade et. al., Phys. Rev. B 48, 8434 (1993)10.1103/PhysRevB.48.8434] based on an iterative search algorithm exploiting Fast Fourier Transforms for fast calculations.

Modeling and experimental investigation of monocrystalline silicon wafer cut by diamond wire saw

Diamond wire sawing is one of the key technologies in solar cell manufacturing process and semiconductor chip manufacturing process. The thinned of silicon wafer has become a development trend of semiconductor industry, and the reduction of silicon wafer thickness can improve the material utilization and reduce the manufacturing cost. Therefore, the minimum thickness analytical model of diamond wire saw cutting monocrystalline silicon wafer is proposed in this paper to study the processing mechanism of minimum thickness of monocrystalline silicon wafer. Firstly, based on the Kirchhoff’s thin plate theory, the theoretical equation of the maximum internal stress of single silicon wafer and the sawing thickness of the silicon wafer is derived from the sawing force model. Combined with the Mohr’s strength theory, the analytical model of minimum sawing thickness of monocrystalline silicon wafer is established. Then, the analytical model is verified by the finite element simulation. The average error between the simulation results and the calculation results of the analytical model about the minimum sawing thickness of silicon wafer is 9%. Finally, the monocrystalline silicon sawing verification experiments are conducted under some groups of processing conditions. The experimental results show that the minimum sawing thickness of the silicon wafer decreases with the increasing axial speed of the wire saw, increases with the increase of the feed rate of the wire saw, and decreases first and then increases with workpiece speed becoming large. The average error of the experimental results and the calculation results of the analytical model of the wafer minimum sawing thickness is 7.4%, which verifies corrections of the analytical model.

BULLKID: Monolithic array of particle absorbers sensed by kinetic inductance detectors

We introduce BULLKID, a phonon detector consisting of an array of dices acting as particle absorbers sensed by multiplexed Kinetic Inductance Detectors (KIDs). The dices are carved in a thick crystalline wafer and form a monolithic structure. The carvings leave a thin common disk intact in the wafer, acting both as holder for the dices and as substrate for the KID lithography. The prototype presented consists of an array of 64 dices of 5.4 × 5.4 × 5 mm3 carved in a 3˝ diameter, 5 mm thick silicon wafer, with a common disk of 0.5 mm thick, hosting a 60 nm patterned aluminum layer. The resulting array is highly segmented but avoids the use of dedicated holding structures for each unit. Despite the fact that the uniformity of the KID electrical response across the array needs optimization, the operation of eight units with similar features shows, on average, a baseline energy resolution of 26 ± 7 eV. This makes it a suitable detector for low-energy processes such as direct interactions of dark matter and coherent elastic neutrino-nucleus scattering.

Breakage Ratio of Silicon Wafer during Fixed Diamond Wire Sawing.

Monocrystalline silicon is an important material for processing electronic and photovoltaic devices. The fixed diamond wire sawing technology is the first key technology for monocrystalline silicon wafer processing. A systematic study of the relationship between the fracture strength, stress and breakage rate is the basis for thinning silicon wafers. The external vibration excitation of sawing machine and diamond wire lead to the transverse vibration and longitudinal vibration for silicon wafers. The transverse vibration is the main reason of wafer breakage. In this paper, a mathematical model for calculating breakage ratio of silicon wafer is established. The maximum stress and breakage ratio for as-sawn silicon wafers are studied. It is found that the maximum amplitude of the silicon wafers with the size of 156 mm × 156 mm × 0.2 mm was 160 μm during the diamond wire sawing process. The amplitude, maximum stress and breakage rate of the wafers increased with the increase of the cutting depth. The smaller the silicon wafer thickness, the larger of silicon wafer breakage ratio. In the sawing stage, the breakage ratio of the 156 mm × 156 mm section with a thickness of 0.15 mm of silicon wafers is 6%.

N-type diamane: An effective emitter layer in crystalline silicon heterojunction solar cell

In the presented work, cell's parameter of heterostructure silicon solar cell modelled as: ITO (front contact)/n-Dn/p-cSi/Ag under the illumination of monochromatic light at standard spectrum AM-1.5 G, has been optimized by using AFORS-HET v 2.5 software. We have used n-type diamane as an emitter layer and the nature of diamane has been considered 3D in spite of 2D as well as electronic nature of diamane is considered isotropic. To ensure that Schottky junction has been formed at interface, the electric contacts have been made along the c-axis so that maximum charge carriers get collected. To obtain the high efficiency, various parameters of n-type diamane as well as p-type c-Si layers have been optimized and the maximum efficiency of 16.84% has been obtained for single layer n-diamane at 100 µm thick silicon wafer. We also investigated the spectral response and dependency of temperature on the performance of exclusively designed solar cell and we obtained the best efficiency 16.84% at 300 K temperature. In order to check the performance on commercially available silicon we have optimized the same solar cell by considering the parameters of commercially available p-type crystalline silicon layer and maximum efficiency 10.41% was achieved. After getting the maximum efficiency 16.84% we further carried out the simulation by optimizing the layer numbers of n-diamane and found decrement in the efficiency up to 15.3% which indicates that, efficiency slightly decreases as layer number increases. We have demonstrated that n-type diamane might be used as an effective emitter layer in crystalline Si heterojunction solar cell.

Gross fracture pits at the intersection of two single scratches during grinding of silicon

Infeed grinding is used in the industry for grinding thick silicon wafers. The grinding process being a series of overlapping scratches, leaves behind the surface and sub-surface damages in the silicon. Continuous in-feed grinding of a thick wafer when used to produce thin wafer leads to breakage upon release from the fixture. This happens because of not only damage induced by a single scratch, but also due to cumulative damage induced as the grinding proceeds with several overlapping and intersecting scratches. In a single scratch, depths below a critical depth can cause material removal without gross fracture and pits; however, it is not clear if this applies to multiple intersecting scratches while grinding silicon. In this study, the grinding operation is performed for a very short period of time, gradually removing the material over only a partial region of the wafer surface while leaving the remaining portion unground. This produces multiple intersecting grinding scratches of increasing depth. Scanning electron microscopy and surface profile measurements of these scratches show that while in a single scratch, material is removed without gross fracture and pitting; when two such scratch intersects, it results in gross fracture at the site of their intersection. Such gross fractures at intersections can happen even at a very shallow depth of scratch as low as 28 nm. This gross fracture at the intersections act as local sites to initiate wafer damage and material removal. Based on the results, we attempted to redefine the critical depth of cut for grinding operation. The study paves the way to manufacture thin damage-free wafers needed for the next generation thin silicon solar cells.

Performance Measurements of Photodiodes for X-Ray Detection

The X-ray free-electron laser (XFEL) at the Pohang Accelerator Laboratory (PAL), Pohang, South Korea, provides X-ray energies of up to 15 keV depending on the experimental purpose. Silicon-based devices have been used as diagnostic devices and detectors for X-rays in experimental stations. Considering recent domestic and international circumstances, developing silicon-based detectors in-house is necessary. We developed a silicon p-intrinsic-n (PIN) photodiode (PD) for X-ray detection, and its performance was investigated and compared with that of a commercial PD used in the PAL-XFEL. The PD was designed to be 1 cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times1$ </tex-math></inline-formula> cm in size, and it used the junction side for signal readout and the ohmic side for X-ray entrance. Considering the absorption length of 12-keV X-rays suitable for crystallography, a 500- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ {\mu }\text{m}$ </tex-math></inline-formula> -thick silicon wafer with a high resistivity was used for PD fabrication. It has a guard ring, an n+ edge field shaper, and an antireflection coating (ARC) and is available in four different types based on the metal structure of the junction and ohmic sides. We present here the electrical characteristics of the PDs. The depletion voltage at which the bulk of the PD is fully depleted was determined to be 119.7 ± 8.2 V from bulk capacitance measurements, and the operation voltage of the PD was set to 200 V. PDs with leakage currents less than 30 nA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at the operation voltage were chosen for performance measurements. The signal-to-noise ratio (SNR) with a Sr-90 radioactive source corresponding to the minimum ionizing particle (MIP) and the quantum efficiency (QE) for wavelengths of 300–1000 nm were measured. Beam tests were conducted at the PAL-XFEL using 600-, 900-, and 1200-eV X-rays where the responses to ultrahigh brightness and ultrashort X-ray pulses were checked. The energy resolutions were measured using gamma-ray radioactive sources, Am-241 (59.5 keV), and Ba-133 (31.0 and 81.0 keV). The differences in performance among the PD types are presented herein in terms of the electrical characteristics, SNR, QE, response to X-ray pulses, and energy resolutions. The results of the fabricated PDs were also compared with those of a commercial PD.

Accurate characterization of surface recombination velocities of silicon wafers with differential nonlinear photocarrier radiometry

The surface recombination velocity (SRV), which reflects the fundamental characteristics of surface defects of semiconductor wafers, is an important parameter in evaluating the quality of surface passivation and electrical performance of surface devices. In conventional photocarrier radiometry (PCR) used for characterizing the electronic transport properties of electronically thick silicon wafers, the rear SRV usually cannot be determined directly due to the relatively low sensitivity of PCR signal to the rear SRV. On the other hand, the determination of front SRV is also very sensitive to the experimental measurement error, especially the measurement error of instrumental frequency response, which is not always easy to be accurately measured in the experiment. In this paper, the front and rear SRVs of silicon wafers are extracted simultaneously with high accuracy by a differential PCR via multi-parameter fitting of the experimental frequency dependences of amplitude ratio and phase difference of PCR signals obtained from the regular measurements and measurements with wafers being flipped respectively to a corresponding differential nonlinear PCR model. The comparison between the front and rear SRVs determined by the conventional and differential PCRs indicates that the differential PCR is highly accurate for the simultaneous determination of the front and rear SRVs of silicon wafers.

A novel metamaterial-based antenna for on-chip applications for the 72.5\u201381\xa0GHz frequency range

In this paper we present a novel metamaterial-based antenna simulated using HFSS. The unit cell parameters were extracted using periodic boundary conditions and wave-port excitation. The metamaterial is magnetically coupled to the CPW line, the induced current in the hexagonal ring gives rise to a field perpendicular to the incident one. The antenna can be modeled by an LC circuit. This design achieves a significant impedance bandwidth of 8.47 GHz (S11 = − 10 dB from 72.56 GHz to 81.03 GHz), and a minimum return loss of − 40.79 dB at 76.89 GHz, which clearly indicates good impedance matching to 50Ω. The proposed antenna offers gains from 4.53 to 5.25 dBi, with radiation efficiencies better than 74%. Compactness, simple design layout, a novel design, and good radiation characteristics for this antenna are the main contributions of this work. The antenna can be built on top of a 300 µm thick silicon wafer, for application on HR-SOI-CMOS technology. When compared to other antenna designs for the same frequency band, the proposed antenna achieves very good performance. This design is suitable for the reception stage of long-range automobile radar systems, due to its wide HPBW, as well as E-band applications, such as backhaul systems.