Research on silicon wafer surface phase under the Ultra-thin slicing process and its etching hindrance behavior during metal-assisted chemical etching

Abstract

Ultra-thin silicon slicing technology plays a critical role in achieving high-efficiency and low-cost solar cells in the photovoltaic (PV) industry. However, the surface phase evolution of silicon wafers under an ultra-thin slicing process and resulting etching behavior remains unclear. In this study, the surface phase evolution of different surface thicknesses of silicon wafers was carefully studied. As the thickness of silicon wafers became relatively thin, the degree of surface stress-induced amorphous silicon (ST-α-Si) significantly increased. Moreover, the UPS test showed that the ST-α-Si layer had an orbital energy level relatively lower than that in monocrystalline silicon, thereby having lower reduction performance during metal-assisted chemical etching (MACE). A copper deposition experiment was conducted to study the etching hindering effect caused by silicon surface ST-α-Si phases. The result showed that the presence of ST-α-Si adversely affected copper deposition. To improve the MACE uniformity, a pretreatment involving the use of HF/H2O2 mixed solution to remove the surface ST-α-Si layer was investigated. After HF/H2O2 pretreatment, the uniformity of inverted pyramids formed through MACE on the silicon wafer surface was significantly improved. Moreover, the reflectance of the MACE-textured surface was reduced to 7.67 % from 10.1 % compared with that without pretreatment. Therefore, this study provides reference guidelines and useful approaches for preparing uniform inverted pyramid surfaces using MACE in ultra-thin silicon wafers.