Thick Ge Research Articles

(Invited) Selective Epitaxial Growth of III-V Semiconductor Heterostructures on Si Substrates for Logic Applications

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. Such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices.

Local intermixing on Ge/Si heterostructures at low temperature growth

We report experimental investigation on a series of strained Ge/Si heterostructure with various Ge thicknesses (the order of nanometers) grown at low temperatures (260 °C). In addition to the conventional uniform intermixing at the Ge/Si interface for structures with thin Ge layer, local intermixing characterized by a pattern structure is observed for structures with thick Ge layer. The pattern is formed beneath the Ge layer with an island shape and exhibits a Ge concentration dependent profile. From the analysis, it shows that the growth temperature and the strain energy stored in the Ge layer play a dominated role for the observation. In comparison with the conventional high temperature growth, this investigation shows that the self-assembly process is suppressed at low growth temperatures and intermixing plays a dominant role for strain relaxation.

Neutron Bragg diffraction on a thick Ge single crystal excited by ultrasound

The intensities of neutron Bragg diffracted from the front- and back-faces of a 22 mm thick perfect Ge single crystal undergoing on ultrasound excitation has been measured and calculated theoretically. It is shown that at the same time as the acoustic wave amplitude is increased, the main Bragg peaks grow and the back-face peak becomes asymmetric and tends to disappear. Such a back-face scattering was observed for the first time and successfully described within frameworks of the dynamic theory of neutron scattering modified in the presence of ultrasound excitation and Kato’s quasiclassical approximation taking into account new ultrasonic extinction length appearance.

Fabrication, structural and electrical properties of compressively strained Ge-on-insulator substrates

Compressively strained germanium-on-insulator (c-GeOI) substrates with a definitely reduced defect density are expected to yield superior hole mobilities together with low off-state currents in p-type metal oxide semiconductor field effect transistors (MOSFETs). In order to fabricate c-GeOI wafers, we started with double-side polished Si(0 0 1) substrates and grew, by reduced pressure-chemical vapour deposition, Si0.15Ge0.85 virtual substrates (VS) on the front side. The wafer curvature was compensated thanks to the deposition of a thick Ge layer on the backside. We then grew, after a chemical mechanical polishing, various thickness (37–148 nm) Ge layers. They stayed smooth (root-mean-square roughness <5 Å) and pseudomorphically strained on the VS underneath (perpendicular lattice parameter: 5.681 Å ⇔ bulk Ge lattice parameter: 5.658 Å) up to a 74 nm thickness. These c-Ge layers were then bonded on oxidized Si substrates using the SmartCut™ process. The resulting c-GeOI substrates were of high crystalline quality, compressively strained and smooth. The threading dislocations density (8 × 105 cm−2 ⇔ 1.7 × 105 cm−2 for the SiGe VS template used to strain the c-Ge layers) was indeed 20 times less than the one associated with conventional GeOI substrates obtained from thick Ge epilayers. Pseudo-MOSFET measurements were performed to quantify the hole mobility gain in those c-GeOI substrates. A +150% enhancement compared to conventional silicon-on-insulator substrates was evidenced, validating the interest of these stacks.

Palladium-Induced Crystallization of Germanium with Varied Palladium Thicknesses

Palladium-induced crystallization of germanium at using different Pd thicknesses is carried out and the qualities of the poly-Ge films obtained are characterized. The crystal qualities of the Ge films are highly dependent on the thickness of Pd used, in which 55 Å is the optimal thickness to induce crystallization of a 418 nm thick Ge film. When a Pd layer thicker than 55 Å is used, it not only deteriorates the crystal quality of Ge but also increases the concentrations of PdGe and in the Ge layer. The sheet resistance of the poly-Ge film decreases with increasing crystalline fraction when the Pd layer is thinner than 70 Å because the amount of Pd germanides is low, and the opposite trend is observed when the Pd layer is thicker than 70 Å due to the high concentration of Pd germanides in the film. The complex dielectric constants of the poly-Ge films show not only the transition energy and peaks but also two other peaks at photon energies of 1.6 and 1.8 eV, which possibly are due to the presence of Pd germanides in the Ge layer.

The effects of low temperature buffer layer on the growth of pure Ge on Si(001)

We investigated the effects of low temperature (LT) Ge buffer layers on the two-step Ge growth by varying the thickness of buffer layers. Whereas the two-step Ge layers using thin (< 40 nm) Ge buffer layers were roughened due to the formation of SiGe alloy, pure and flat Ge layers were grown by using thick (> 50 nm) LT Ge buffer layers. The lowest threading dislocation density of 1.2 × 10 6 cm − 2 was obtained when 80-nm-thick LT Ge buffer layer was used. We concluded that the minimum thickness of buffer layer was required to grow uniform two-step Ge layers on Si and its quality was subject to the thickness of buffer layer.

Detection efficiency for an ultraviolet photon counting imaging system based on the Ge induction readout

The detection efficiency, assumed proportional to the count rate, of an ultraviolet photon counting imaging system based on the Ge induction readout is studied. For the Ge induction readout, the system count rate with different Ge layer resistances, Ge layer thicknesses and ceramic thicknesses are tested under different light intensities. The test results show that the system count rate with a high resistance in the Ge layer is lower than that with a low resistance in the Ge layer; further, the imaging area decreases as the Ge layer resistance increases under high photon flux. Moreover the system count rate with a thick Ge layer is lower than that with a thin Ge layer. In addition, the system count rate with 2-mm ceramic is higher than that with 1.5- and 3-mm ceramic. The above observation should be considered when designing an ultraviolet photon counting imaging detector based on the Ge induction readout.

Quantum-confined direct band transitions in tensile strained Ge/SiGe quantum wells onsilicon substrates

We directly demonstrate quantum-confined direct band transitions in the tensile strainedGe/SiGe multiple quantum wells grown on silicon substrates by room temperaturephotoluminescence. The tensile strained Ge/SiGe multiple quantum wells withvarious thicknesses of Ge well layers are grown on silicon substrates with a lowtemperature Ge buffer layer by ultrahigh vacuum chemical vapor deposition.The strain status, crystallographic, and surface morphology are systematicallycharacterized by high-resolution transmission electron microscopy, atomic forcemicroscopy, x-ray diffraction, and Raman spectroscopy. It is indicated that thephotoluminescence peak energy of the tensile strained Ge/SiGe quantum wellsshifts to higher energy with the reduction in thickness of Ge well layers. Thisblue shift of the luminescence peak energy can be quantitatively explained bythe direct band transitions due to the quantum confinement effect at theΓ point of the conduction band.

High efficiency thin-film crystalline Si/Ge tandem solar cell

We propose and simulate a photovoltaic solar cell comprised of Si and Ge pn junctions in tandem. With an anti-reflection film at the front surface, we have shown that optimal solar cells favor a thin Si layer and a thick Ge layer with a thin tunnel hetero-diode placed in between. We predict efficiency ranging from 19% to 28% for AM1.5G solar irradiance concentrated from 1 approximately 1000 Suns for a cell with a total thickness approximately 100 microm.

Selective epitaxial growth of Ge(1 1 0) in trenches using the aspect ratio trapping technique

The aim of this study was to assess the efficiency of aspect ratio trapping in improving the crystalline quality of relaxed Ge(1 1 0) layers selectively grown in trenches surrounded by SiO 2. The 400 °C growth of a few hundreds of nanometers thick Ge layers has first been studied on blanket Si(1 1 0) surfaces then in recessed areas of Si(1 1 0) patterned wafers. The influence of 1 min H 2 anneals (in-between 600 and 850 °C) on the surface morphology, crystalline quality and strain state of blanket Ge(1 1 0) layers has notably been quantified. Intermediate annealing temperatures (750 °C) have improved the crystalline quality and increased the macroscopic strain relaxation of those layers, without too high a surface roughening. (1 1 0) Si windows (surrounded by shallow trench isolation) of patterned wafers have then been recessed by ≈300 nm using gaseous HCl, with a definite faceting and a slight roughening of the resulting cavities. Epitaxial lateral overgrowth of Ge has then been implemented in those trenches, followed by 1' H 2 bakes at 750 °C. Chemical mechanical polishing has been used afterwards to get rid of the several hundreds of nm thick Ge layer overflowing on the SiO 2 areas (very reduced dishing and flat Ge(1 1 0) surfaces obtained in the end). The efficiency of aspect ratio trapping in reducing the defect density in those Ge(1 1 0) layers is not obvious. Indeed, some trapping of inclined defects in the SiO 2 sidewalls of narrow Ge(1 1 0) patterns (∼80 nm long) has been evidenced. However, the theoretically unexpected appearance of defects at 90° to the surface (i.e. normal to (1 1 0)) that were consequently not trapped was detrimental to defect density reduction. Those 90° defects may have arisen from interactions of inclined defects with one another. The reduction of the high defect density in relaxed (1 1 0) layers is thus still challenging and requires further investigations.

Impact of the H 2 anneal on the structural and optical properties of thin and thick Ge layers on Si; Low temperature surface passivation of Ge by Si

Using a low temperature/high temperature strategy, we have grown thin (0.27 μm) and thick (2.45 μm) Ge layers on Si(0 0 1) substrates that we have submitted to various constant temperature (750 °C) or cyclic (750 °C/890 °C) H 2 anneals, the objective being to identify those yielding the smoothest surfaces, the lowest threading dislocations densities (TDDs) and the highest near infra-red optical absorptions. The best trade-off for thin layers was 750 °C, 60 min H 2 anneals. Using longer duration 750 °C anneals and especially 750 °C/890 °C cyclic anneals indeed yielded rougher surfaces and vastly degraded optical absorption (deleterious formation of GeSi alloys). By contrast, short 750 °C/890 °C thermal cyclings yielded the best metrics in thick Ge layers (while being at the same time the best in terms of throughput): root mean square surface roughness around 0.8 nm, TDD around 10 7 cm −2, slightly tensily-strained layers (which a plus for optical absorption as the absorption edge is shifted to higher wavelengths), a limited penetration of Si into Ge (and thus absorption coefficients at 1.3 and 1.55 μm almost equal to those of as-grown layers), etc. We have also described the low temperature (450 °C/525 °C) process that we have developed to passivate Ge surfaces thanks to SiH 4 prior to gate stack deposition. Si layer thickness should be below 20 Å in order to have conformal deposition. A transition of the growth front to 3 dimensions has indeed been evidenced for 20 Å and higher.

Observation of a paramagnetic defect at the epitaxial Ge 3N 4/(111)Ge interface by electron spin resonance

A multifrequency electron spin resonance (ESR) study of Ge 3N 4/(111)Ge entities with nm thick epitaxial Ge 3N 4 layers, of subcritical thickness for mismatch relaxation, grown in a nitrogen plasma reveals the presence of an anisotropic paramagnetic interface center of trigonal symmetry. Building on the analysis of its specific ESR properties, including magnetic field angular mapping data and in the light of previous insight, the signal is tentatively ascribed to the interfacial •Ge N 3 center. The defect occurrence is discussed within the specific interface matching, without misfit dislocations. As an interfacial Ge dangling bond defect, it may operate as an inherent electrically detrimental trap.

Short-channel epitaxial germanium pMOS transistors

This work gives an overview of recent advances in IMEC's Ge pFET technology. Thin (330 nm) Ge epitaxial layers, selectively grown in Shallow-Trench Isolation (STI)-patterned wafers are presented. These thin layers show a 70% higher area junction leakage than thick Ge virtual substrates at 1 V bias, but the presence of STI reduces the leakage at the isolation perimeter by a factor of 5. Low-temperature epitaxial growth of silicon for gate dielectric applications is proposed as a solution to reduce the Equivalent Oxide Thickness (EOT). It is shown that a low-temperature (350 °C) recipe with a Si 3H 8 precursor leads to reduced Ge segregation towards the Si surface, and facilitates EOT scaling to 1 nm and below. Junction leakage generated under the transistor's spacer regions is analysed, and it is shown that this is the dominant junction leakage component in short-channel Ge technologies. As the leakage scales with electric field, reducing the supply voltage is suggested as a solution to keep this leakage component under control.

P+/n junction leakage in thin selectively grown Ge-in-STI substrates

This work analyses ultra-shallow pFET junctions in 330 nm-thin germanium virtual substrates, selectively grown in the active regions of Shallow Trench Isolation (STI) patterned silicon wafers. The area leakage is 5–10 times higher than similar junctions in thick Ge virtual substrates if a Post-Growth (PG) anneal is done to reduce the density of threading dislocations. On the other hand, there is a factor of 10 lower perimeter leakage, thanks to the presence of the STI. The dominant generation mechanism is Trap-Assisted Tunneling up to 1 V reverse bias, both for the area- and perimeter-generated leakage, as has been confirmed by measurements at elevated temperatures. Negligible frequency dispersion is found for reverse biases below 3 V. However, at high reverse bias, significant frequency dispersion of the junction capacitance is found, which can be attributed to a higher defect density near the Ge/Si interface.

Synthesis of strained SiGe on Si(100) by pulsed laser induced epitaxy

Pulsed laser induced epitaxy (PLIE), based on melting/solidification processes induced by nanosecond laser pulses, is used to synthesize pseudomorphic Si 1 − x Ge x epilayers from 20 to 80 nm thick Ge layers evaporated on a Si(100) wafer. Ge concentration and strain are characterized by transient reflectivity, energy dispersive X-ray analysis and X-ray diffraction from symmetric (004) and asymmetric (224) reflections. For a low Ge thickness or a high laser fluence, PLIE builds up only a pseudomorphic strained Si 1 − x Ge x layer with a graded Ge composition reaching x ≈ 19% near the surface. When the Ge amount is in excess to achieve this situation, PLIE forms additionally a relaxed Si 1 − x Ge x layer with x values up to ≈40% over the previous pseudomorphic layer.

Fabrication of high quality Ge virtual substrates by selective epitaxial growth in shallow trench isolated Si (001) trenches

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 10 7 cm − 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III–V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.

On the frequency dispersion of the capacitance-voltage behavior of epitaxial Ge on Si p+-n junctions

The electrically active defects in epitaxial germanium layers grown selectively on silicon-shallow trench isolation (STI) wafers have been investigated by means of p+-n junction characterization. The main focus is on the capacitance-voltage (C-V) analysis in reverse operation. A pronounced frequency dispersion in the C-V characteristics has been found for Ge Si-STI layers, while this is not the case for thick epitaxial Ge on Si layers, which contain a significantly lower density of threading dislocations. It is shown that the apparent free carrier density profile derived from the C-V plot at high frequency exhibits a pronounced overshoot in the vicinity of the Ge–Si heterointerface. However, this feature is not only determined by the band offset between the Ge and Si conduction band edges but also by the high density of extended defects and associated deep levels present near the interface. Finally, the impact of a postgrowth high-temperature annealing on the electrical properties of Ge Si-STI epitaxial layers will be discussed in view of the resulting change in extended defect density and profile.

Defect structure of Ge(111)/cubic Pr2O3(111)/Si(111) heterostructures: Thickness and annealing dependence

The defect structure of Ge(111) epilayers grown by molecular beam epitaxy on cubic Pr2O3(111)/Si(111) support systems was investigated by means of transmission electron microscopy and laboratory-based x-ray diffraction techniques. Three main types of defects were identified, namely, rotation twins, microtwins, and stacking faults, and studied as a function of Ge film thickness and after annealing at 825 °C in ultrahigh vacuum. Rotation twins were found to be localized at the Ge(111)/cubic Pr2O3(111) interface and their amount could be lowered by the thermal treatment. Microtwins across {111¯} were detected only in closed Ge films, after Ge island coalescence. The fraction of Ge film volume affected by microtwinning is constant within the thickness range of ∼20–260 nm. Beyond 260 nm, the density of microtwins is clearly reduced, resulting in thick layers with a top part of higher crystalline quality. Microtwins resulted insensitive to the postdeposition annealing. Instead, the density of stacking faults across {111¯} planes decreases with the thermal treatment. In conclusion, the defect density was proved to diminish with increasing Ge thickness and after annealing. Moreover, it is noteworthy that the annealing generates a tetragonal distortion in the Ge films, which get in-plane tensely strained, probably due to thermal mismatch between Ge and Si.

Shape transitions and island nucleation for Si/Ge molecular beam epitaxy on stripe-patterned Si (001) substrate

Si and Ge growth on the stripe patterned Si (001) substrates is studied using scanning tunneling microscopy. During Si buffer growth, the stripe morphology rapidly evolves from multifaceted ''U'' to ''V''-shaped forms. This involves successive transitions between different low energy (11n) side facets, where n continuously decreases from n=3 to 20. Ge growth on such stripes induces the formation of a pronounced side wall ripple structure when the Ge thickness exceeds three monolayers. This ripple structure consists of alternating (105) microfacets oriented perpendicularly to the stripes. Depending of the side wall geometry, Ge nanoislands subsequently nucleate either on the side walls or at the bottom of grooves. The latter only occurs for ''V''-shaped stripes, where the side wall ripples extend all the way from the top to the bottom of the grooves, allowing efficient downward mass transport. For multifaceted ''U'' stripes, the side wall ripples are interrupted by steeper side wall segments such that mounds and subsequently, pyramids and domes grow on the side walls instead of at the bottom of the grooves. The island shapes strongly depend on their position on the pattern topography, which also affects the critical coverage for island nucleation as well as for the transitionmore » from pyramids to domes. The mechanisms for nucleation at different positions are clarified by detailed analysis and the role of kinetic as well as energetic factors identified.« less

Nanoscale Pit Formation at 2D Ge Layers on Si: Influence of Energy and Entropy

The structural stability of two-dimensional (2D) SiGe nanostructures is studied by scanning tunneling microscopy. The formation of pits with a diameter of 2-30 nm in one atomic layer thick Ge stripes is observed. The unanticipated pit formation occurs due to an energetically driven motion of the Ge atoms out of the Ge stripe towards the Si terminated step edge followed by an entropy driven GeSi intermixing at the step edge. Using conditions where the pits coalesce results in the formation of freestanding 8 nm wide GeSi wires on Si(111).