TFT Structure Research Articles

26‐1: Embedded a‐Si Photo‐Transistor Sensors Integration in Remote Optical Touch‐input Panel Using Four‐Mask Process Architecture Technology

An optical type touch‐input flat panel is designed. The driving system is based on the passive pixel sensor (PPS) array with amorphous silicon (a‐Si) TFT technology. The embedded sensing structure of the optical sensor is using the a‐Si TFT phototransistor and four‐mask process architecture technology. This paper presents a primary optical pixel sensor circuit that utilizes hydrogenated amorphous silicon photo‐transistor sensor. The a‐Si TFT phototransistor sensor is high reliability by using Multi‐N+ layer in the a‐Si TFT structure.

33‐1: Development of Trasflective 54.5‐inch IGZO‐TFT LCD with Super‐low Refresh Rate Driving

We are developing transflective LCD displays for signage that have good outdoor visibility and super‐low power consumption. This panel adopts a design that incorporates our technologies such as TFT, twisted‐VA technology, and MRS structure that can be driven at super‐low frequencies using IGZO technology. We would like to report that we have developed a 54.5‐inch transflective LCD.

46‐1: 1218 ppi Quest 3 Display by Hybrid Backplane with Highly Reliable IGZO TFTs

A 2.48‐inch with 1218 ppi, LCD panel for Quest 3 using hybrid backplane technology with CMOS‐LTPS and IGZO TFTs were manufactured. The hybrid TFT structure achieves high resolution and high transmittance simultaneously, and also ensures high reliability. The fabricated LCD panel has proven to be highly reliable, enduring 1000 hours in aging tests, and has been successfully mass‐produced.

Superior performance of ZnGaO solar-blind photodetectors by Implementing TFT structure and tunable ZnO cycle ratio

In this study, plasma enhanced atomic layer deposition was used to prepare ZnGaO thin films with different ZnO cycle ratios from 0 % to 50 %, which were employed to fabricate the MSM-type and TFT-type solar-blind photodetector. The properties of the films and the performance of the solar blind photodetector are greatly affected by the ZnO cycle ratio. Appropriate Zn doping content decreases the ratio of oxygen vacancies and Zn interstitials in Ga2O3, while excessive Zn doping degrades the quality of the film. Compared to MSM-type photodetector, an obviously improved performance of ZnGaO TFT-type photodetector has been observed due to its self-amplified photocurrent and the reduced dark current controlled by gate voltage. At a ZnO cycle ratio of 40 %, a superior performance of TFT-type solar-blind photodetector with an ultra-low dark current ∼4.5 × 10−13 A, an excellent light switching ratio ∼2.2 × 107, and an outstandingly high sensitivity ∼34.31 A/W has been obtained. These results demonstrate that the incorporation of Zn dopants can effectively modulate the performance of Ga2O3 TFT-type photodetector providing a great perspective for cost-effective and high-performance solar-blind PDs.

TFT Structure Simulation with Various High K Dielectric Materials for Non-volatile Memory Device

TFT Structure Simulation with Various High K Dielectric Materials for Non-volatile Memory Device

Quantitative analysis of defect states in InGaZnO within 2 eV below the conduction band via photo-induced current transient spectroscopy

This work investigates the function of the oxygen partial pressure in photo-induced current measurement of extended defect properties related to the distribution and quantity of defect states in electronic structures. The Fermi level was adjusted by applying a negative gate bias in the TFT structure, and the measurable range of activation energy was extended to < 2.0 eV. Calculations based on density functional theory are used to investigate the changes in defect characteristics and the role of defects at shallow and deep levels as a function of oxygen partial pressure. Device characteristics, such as mobility and threshold voltage shift under a negative gate bias, showed a linear correlation with the ratio of shallow level to deep level defect density. Shallow level and deep level defects are organically related, and both defects must be considered when understanding device characteristics.

7‐4: Correction Algorithm for Under‐Display Camera Area on AMOLED Display

In this paper, we correct the necessary image algorithm such as sub‐pixel rendering (SPR) and de‐mura (DMR) for under‐display camera (UDC) area on AMOLED display. Because the wiring of TFT pixel circuit and structure are different between UDC and normal area, it results in color shifts and brightness nonuniformity in the UDC area. The new correction algorithms we propose are based on the existing architecture, distinguish the position coordinates of the two areas, and give a new correction method for the UDC area. The new algorithms have been integrated into the new DDIC NT37701 and have been mass‐produced for smartphone products.

P‐137: High Performance Coplanar IGZO TFT Image Sensor with Partial Passivation‐less Structure for Digital X‐ray Detector

Recently, digital X‐ray detector (DXD) technology is needed to implement high‐resolution and high‐definition images, and low‐dose exposure of X‐ray imaging systems. This technology requires the IGZO TFT structure with better mobility and lower leakage current than the a‐Si backplane. In order to supplement stability and improve PIN diode (photodiode) performance, when SiNx‐based insulating layers and thick photodiodes are applied, continuous damage due to high concentration impurities occurs in the plasma environment, and thus the threshold voltage (Vth) shift problem of the IGZO TFT transistor occurs. To solve this problem, a high performance partial passivation‐less structure (PPLS) was applied to prevent damage using 43×43 centimeter flat panel X‐ray detector, and we investigated the improvement of the IGZO TFT characteristics. Before PIN diode deposition, Vth was +0.24V and after PIN diode &amp; SiNx deposition, it moved slightly to Vth ‐0.17V, but the same characteristics as initial performance were guaranteed after TFT was completed.

P‐5.11: A Study on De‐multiplex Technology Based on IGZO Semiconductor for Notebook LCDs

We proposed a DEMUX (De‐multiple) technology based on IGZO BCE‐type TFT structure and produced the 13.3 inches FHD LCDs for notebook. The adoption of DEMUX 1:3 circuit on panels combing with TED (Tcon‐Embedded Driver) technology realized a narrow module bezel of less than 15mm for the LCDs. A slight horizontal streaks issue observed on RG/GB/RB mixed color image under middle and low grayscale display is analyzed and discussed. The modeling and simulation results indicate that the issue is related to the drive architecture of Zigzag‐column inversion under charging insufficient of source lines.

P‐4.2: A Study on De‐multiplex Technology Based on IGZO Semiconductor for Notebook LCDs

We proposed a DEMUX (De‐multiple) technology based on IGZO BCE‐type TFT structure and produced a 13.3 inches FHD LCD for notebook. The adoption of DEMUX 1:3 circuit on panels combing with TED (Tcon‐Embedded Driver) technology realized a narrow module bezel of less than 15mm for the LCDs. A slight horizontal streaks issue observed on RG/GB/RB mixed color image under middle and low grayscale display is analyzed and discussed. The modeling and simulation results indicate that the issue is related to the drive architecture of Zigzag‐column inversion under charging insufficient of source lines.

PZT Ferroelectric Synapse TFT With Multi-Level of Conductance State for Neuromorphic Applications

To fundamentally solve the bottleneck of Von Neumann’s computing architecture, a neuromorphic thin-film transistor (NTFT) employing Pb(Zr, Ti)O3 (PZT) was investigated. The indium gallium zinc oxide (IGZO) channel back gate TFT structure was chosen to solve the diffusion of atoms that form a channel layer during the annealing process for crystallization of PZT. A post-deposition process with IGZO after annealing PZT and using an oxide-based material as a channel structure can minimize the diffusion phenomenon of junction materials and oxygen together, which leads to a high and reliable performance of the NTFT. The basic operations of synapses short-term memory (STM) and long-term memory (LTM) were also analyzed to confirm the application of a neuromorphic device. The high dielectric constant and polarization properties of Pb(Zr, Ti)O3 (PZT) allow the power consumption of spike signals used in spike dependent plasticity change to be reduced to 10 pJ. Moreover, a wide dynamic range of $\text{G}_{\mathrm {max}}/\text{G}_{\mathrm {min}} \cong ~1000$ was obtained, and the channel conductance was maintained over 40000 seconds. The optimized pulse achieved multi-level states (>32), which made the learning process efficient. This study verified that the PZT-TFT structure has a high potential and merits for neuromorphic devices.

21‐2: Invited Paper: 1µm Pixel Pitch Spatial Light Modulator Panel for Digital Holography

Digital hologram images reconstructed through interference of the modulated light waves requires ultra high resolution display panel. BCE oxide TFTs with channel width of 0.5µm and channel length of 2µm were stacked on data line for the integration of 1µm pitch pixel. 1µm pixel pitch 16K spatial light modulator on glass substrate was successfully fabricated with vertically stacked TFT structure.

56.2: Embedded Fingerprint/Image Sensor Array Panel using a‐Si TFT photo‐sensor and Four‐Mask Halftone Process Technology

Fingerprint recognition is becoming a familiar technology. To further foster its use, it is important to make thinner sensors, adequate for embedding in various devices including display devices. An Optical type fingerprint scanning/touch‐input flat panel is designed. The driving system is based on the passive pixel sensor (PPS) array with amorphous silicon (a‐Si) TFT technology. The embedded sensing structure of the optical sensor is using the a‐Si TFT phototransistor and four‐mask process architecture technology. The pixel density is over 500 PPI and the a‐Si TFT phototransistor sensor is high reliability by using Multi‐N+ layer in the a‐Si TFT structure.

8.4: Invited Paper: Oxide devices for displays and low power electronics

Oxide semiconductors have been envisaged to find applications in flexible electronics in daily life such as wearable electronic gadgets to offer novel user experiences. However, there are still several bottlenecks to overcome in order to realise this goal, especially the lack of oxide‐semiconductor components fast enough for wireless communications, low power oxide transistors, and high‐performance p‐type oxide semiconductors for complementary circuits. Here we review our recent work to address these problems, including gigahertz operating IGZO Schottky diodes and TFTs, 1 V operating TFTs, complementary circuits using IGZO and SnO TFTs, and a novel TFT structure with unique performance.

Low-temperature poly Si TFTs via BLDA for a Ne-sputtered Si film using sputtered gate SiO2

ABSTRACTAmorphous SiO2 and amorphous Si films were deposited on glass using radio frequency (RF) sputtering, and were subsequently poly-crystallized using blue-laser diode annealing (BLDA) scanned by a CW beam. Ne, which has a smaller atomic radius than Ar, was used for the sputtering of the Si film. For the gate insulator, a small amount of O2 gas diluted with Ar was flown during the sputtering to optimize the SiO2 film with a low leakage current. A simple TFT structure with a metal source and drain (S/D) was adopted to realize a low-temperature process with a low fabrication cost. Furthermore, to confirm the effectiveness of the sputtered gate oxide, a poly-Si TFT adopting a Si film deposited using plasma-enhanced chemical vapor deposition (PE CVD) for the channel was fabricated and was compared with the TFT with a sputtered Si film for the channel. Reasonable Vg-Id characteristics were obtained for both poly-Si TFTs. The TFT structure with a metal S/D formed through a low-temperature sputtering-based process is expected to be applied to Si TFTs on an arbitrary flexible panel.

(Invited) Technology Trend of Poly-Si TFT from Viewpoints of Crystallization and Device Performance

TFTs utilizing the Low-Temperature Polycrystalline-Si (LTPS) are very crucial for the system-on-glass. The requirements for the LTPS are a high quality, a large grain size and a position control of the nucleation. To satisfy those requirements, the promising crystallization methods have been presented. In addition, the device structures such as the double gate TFT and the tunnel type TFT have been developed. The excimer laser annealing provided a large grained film with a high-quality. It was also clarified that hydrogens in a-Si film greatly accelerated the crystal velocity and improved the crystallinity of the poly-Si film. A soft X-ray crystallization (SXC) reduced the threshold temperature of crystallization for a-Si, Ge and SixGe1-x films by 100-150 oC as compared with the thermal crystallization. Although the high-performance TFT utilizing the large single crystalline grains has been intensively researched, it does not successfully operate from the productive viewpoint. Tunneling Dielectric Thin-Film Transistor (TDTFT) was proposed and fabricated. It reduced the gate-off current less than 1/10 in comparison with a conv. TFT. In addition, the TDTFT improved the hump effect. We conclude that TDTFT will be suitable as a promising candidate of the next generation poly-Si TFT structure.

76‐4: Late-News Paper: Flat Panel Fingerprint/Touch‐input Image Sensor Using a‐Si TFT Photo‐transistor and Four‐Mask Process Architecture Technology

An Optical type fingerprint scanning/touch‐input flat panel is designed. The driving system is based on the passive pixel sensor (PPS) array with amorphous silicon (a‐Si) TFT technology. The embedded sensing structure of the optical sensor is using the a Si TFT phototransistor and four‐mask process architecture technology. The pixel density is over 500 PPI and the a‐Si TFT phototransistor sensor is high reliability by using Multi‐N+ layer in the a‐Si TFT structure.

P‐59: Improving TFT Structure Uniformity in G8.5 LCDs

Methods for lessening the AS tail and N+ tail were systematically investigated in G8.5 glass for LCD product development including novel structure designs and matched 4‐Mask process. While matched 4‐Mask process had success in tails reducing, Ion keeping, stability improving and Ioff decreasing at higher negative voltage by optimized O2 ashing process, further efforts were still indispensable. Novel mask structure designs were provided using photoresist thickness modulation method for 4‐Mask process architecture to ulteriorly reduce the tails. Less amorphous silicon tail (AS tail) and heavy doped amorphous silicon tail (N+ tail) were attained in both inner and outline frame beside the second metal solely by structure design, which limited the scope of N+ tail within 0.5 um and AS tail about 1.2um, respectively. What’s more, the N+ tail could be further decreased by cooperating with the matched 4‐Mask process using the optimized recipe.

12‐3: A 5.5 inch FFS‐LCD Driven by Soluble ‐metal‐oxide and Implementation in Production Line through BCE TFT Structure

In this work, solution based metal‐oxide TFT with BCE structure is successfully implemented in TFT‐LCD production line. The well‐known slot‐die coating technology is used to deposit liquid phase semiconductor on Gen4.5 substrates. Finally, a 5.5 inch TFT LCD driven by solution metal oxide TFT was successfully demonstrated.

Concise Modeling of Amorphous Dual-Gate In-Ga-Zn-O Thin-Film Transistors for Integrated Circuit Designs**Supported by the National Key Research and Development Program of China under Grant No 2017YFA0204600, the National Natural Science Foundation of China under Grant No 61404002, and the Science and Technology Project of Hunan Province under Grant No 2015JC3041.

An analytical model for current–voltage behavior of amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) with dual-gate structures is developed. The unified expressions for synchronous and asynchronous operating modes are derived on the basis of channel charges, which are controlled by gate voltage. It is proven that the threshold voltage of asynchronous dual-gate IGZO TFTs is adjusted in proportion to the ratio of top insulating capacitance to the bottom insulating capacitance (CTI/CBI). Incorporating the proposed model with Verilog-A, a touch-sensing circuit using dual-gate structure is investigated by SPICE simulations. Comparison shows that the touch sensitivity is increased by the dual-gate IGZO TFT structure.