TFT Process Research Articles

Si ナノ密着層による高分子フィルム・ガラスの接合と分離

A method for debonding polyimide film and ultra-thin glass from glass substrate is proposed. The method is based on the surface activated bonding approach extended to a modified bonding process using Si nano-adhesion layer. The surfaces of both polyimide film and the glass substrate are activated by Si nano-adhesion layer deposited in vacuum and bonded in situ at room temperature whereas only the ultra-thin glass surface is treated with Si nano-adhesion layer, and bonded in vacuum to glass substrate after exposure to N2 gas. Even after a thermal treatment such as TFT process over 400 to 500°C, they can be debonded by mechanical peeling at room temperature.

Low Power and High Driving Capability of Amorphous Silicon Gate Driver Circuit

In this paper, we propose a novel amorphous silicon gate driver (ASG) circuit with useful driving methods in saving power consumption and improving driving capability as well. Unlike other driving methods that are used to improve the driving capability also increases the power consumption strikingly. In this paper, an ASG circuit with novel driving method is proposed and realized in standard 5-mask hydrogenated amorphous-silicon thin-film transistors (a-Si:H TFTs) process. The circuit consisting of 13 a-Si:H TFTs is used in portable flat-panel displays (FPDs) for the high driving capability and low power characteristic. By comparing other driving methods, the results of the definitive measurement show that the minimum driving high voltage is improved with 2 volts increment and the power consumption increases 9.7% slightly. Moreover, the other dynamic characteristics of the ASG, such as the rise time and fall time of the outputs, can be improved at the same time. To validate the results, the designate circuit is fabricated with 5- $\mu$ m a-Si:H TFT process and the experimental results confirm the practicability of achieved design. Three different driving methods are adopted in the same ASG circuit to respond three individual output characteristics.

TFT制程中高厚度ITO残留因素的研究

氧化铟锡(ITO)是薄膜晶体管工艺中最常用的透明导电薄膜,随着OLED技术的发展,ITO作为透明阳极材料也被广泛应用.在高厚度(尤其是大于70 nm)非晶ITO工艺过程中,由于多种因素的影响,很容易产生残留,发生残留后会严重影响产品质量和项目进度.本文通过多次实验测试,综合多种不同厚度,尤其是针对高厚度非晶ITO,分析了TFT制程中影响残留的多种因素,考察重点因素及影响规律,有效地修正工艺条件,为之后的项目和生产过程提供了很好的参考价值.

Submicron Particle Removal during FPD Oxide TFT Process

In panel manufacturing processes, cleaning process was not considered to be critical thus far. However, as pixel size is becoming smaller nowadays, the number of pixels per unit area is gradually increasing due to the high resolution. Consequently, an influence of submicron sized contaminated particles is increasing, and hence attention needs to be given to cleaning process. For a large area and high resolution panel with a good production yield, a research on an effective cleaning process which can remove the contaminated particles deposited on the Cu, SiO2 and ITO surfaces is required. Generally, physical cleaning processes are used to remove the submicron particles in FPD (Flat Panel Display) process. In this study, we have optimized these cleaning processes to remove the submicron particles from the substrate surface. Here, we achieved a high cleaning efficiency of above 95% in the EIW megasonic cleaning process on all the substrates.

LTPS TFT Process on Polyimide Substrate for Flexible AMOLED

For conventional active-matrix organic light-emitting diode (AMOLED) flat panel displays, low temperature poly-silicon thin-film transistor (LTPS TFT) on rigid glass substrate process has already been well established. However, this technology cannot be applied directly on polyimide (PI) substrate for flexible display. This is because PI has the different coefficient of thermal expansion (CTE) from the glass, which will result in PI film peeling-off and/or warpage issues under conventional LTPS-TFT process technology. In this paper, a process flow of LTPS TFT on PI substrate for flexible display application was discussed. A flexible display demo system was successfully made by optimizing the LTPS TFT process.

P‐59: 6‐inch Full Color AMOLED with Improved Bonding Strength of Laser Frit Encapsulations

Although laser seal frit encapsulation owns great ability of protecting OLED from moisture and oxygen oxidation, the bonding strength is too weak to resist machenical force, which is easy to result in peeling the top and bottom substrates of OLED display. In this paper, we improve the bonding strength and production yield ratio by optimizing TFT array structure and process.

(Gordon E. Moore Medal for Outstanding Achievement in Solid State Science and Technology) Research on Nano and Giga Electronics – Breakthroughs Along the Path

ICs and TFT LCDs are two largest semiconductor industries nowadays. The former is mainly driven by the Moore’s Law in the continuous shrinkage of the nano-size devices for improved speeds and functions. The latter has progressed toward the manufacture of high density devices on the ultra-large glass substrate. However, the most critical devices in both products, i.e., MOSFETs and TFTs, are operated based on the same principle. The success of these technologies is dependent on the thorough understanding and controlling of material properties, fabrication processes, and device physics. In this presentation, I will review some key breakthroughs achieved in my laboratory, such as the generalized material-process-device relationship for the large-area TFT array, the simplest 2-mask TFT process, the plasma radiation damage mechanism, the plasma-based room-temperature copper etch process, the doped metal oxide high-k gate dielectrics, the nanocrystals embedded high-k nonvolatile memories, the solid-state incandescent LEDs, and various new devices. Future developments of the technologies will be discussed.

P‐19: A New Pixel Circuit to Compensate Panel Non‐uniformity and OLED Degradation on Large IGZO AMOLED Panel

AbstractA new 4T2C pixel circuit is proposed in this study to compensate TFT process variations, Vth, mobility, power line IR‐drop, and OLED degradation in IGZO‐TFT process. Compensation performances show only from ±0.8% to ±1.74% panel non‐uniformity in average.

Application of Flexible OLED Display Technology for Electro-Optical Stimulation and/or Silencing of Neural Activity

This paper presents a new biophotonic application for large-area, high-resolution, flexible organic light-emitting diode (OLED) display technology currently used to manufacture low-cost color flexible displays on plastic substrates. The new concept uses a fully addressable high resolution flexible OLED pixel array on a thin, mechanically compliant biocompatible plastic substrate to selectively stimulate and/or silence small groups of neurons on either the cortical surface or, alternatively, within the deep brain. Optical measurements from a 455 nm blue flexible OLED test structure demonstrated the ability to emit 1 mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of instantaneous light intensity using a 13 V, 20 Hz pulse, which meets the minimum reported intensity at ~ 450 nm to induce optical stimulation in genetically modified neural tissue. Biocompatibility was successfully demonstrated by the ability to grow human epithelial cells on the surface of a full TFT process flow plastic flexible display substrate. Additionally, a new active matrix array display architecture was designed to support pulsed mode OLED operation. These preliminary results demonstrate the initial viability of extending flexible plastic substrate OLED display technology to the development of large-area, high-resolution emissive active matrix arrays for chronic optogenetic applications.

Critical point defect detection for small‐pixel thin‐film transistor array applied to medical display

AbstractThin‐film transistor (TFT) array testing technique has been used, which provides defect detection capability to control the yield of the TFT process. In the past, several defect inspection technologies have been developed and applied for the TFT array testing. When the TFT array pixel size is getting smaller and the resolution is higher, they also encounter the performance limitation on detecting the critical defect in this small‐pixel TFT array and facing a limited testing requirement. For medical display applications, the display pixels on an array panel are getting smaller and smaller; therefore, defect detection is getting more important and critical for managing yield with quality. In this study, a novel approach for defect detection was proposed. Here, the proposed voltage imaging technique is used for the TFT array test, and it provides better small‐pixel TFT array defect detection capability. The experimental results show that by using the voltage imaging technique, detecting critical point defect of TFT array can be effectively improved. And the detected small‐pixel size of TFT array panels can be smaller than 55 µm of an advanced medical display.

10.4: Improvement of Stability on a‐IGZO LCD

AbstractWe have developed 10‐inch 300PPI and 65‐inch ultra high‐definition FFS LCD using amorphous In‐Ga‐Zn‐O(IGZO) TFT. After improvement of TFT's process and structure, the TFT performance is good enough for TFT‐LCD. In this report, we discuss our IGZO TFT process, uniformity and reliability.

52.1: Invited Paper: High Performance Metal‐Oxide TFT on Flexible Plastic Substrates

AbstractActive Matrix displays on light weight, non‐fragile, plastic substrates are of great interests for portable applications. One of the challenges has been device performance processed at low temperature: in both carrier mobility and operation stability. Another challenge has been a TFT process flow without rigorous alignment among patterns in different layers. In this presentation, we present a MOTFT processed at low temperature, on PEN or PET substrates, with mobility above 50 cm2/Vsec and with bias stability sufficient for portable display products. TFT performance over large substrate size are guaranteed by a proprietary self‐aligned process which enables large size display backpanel be made in roll‐to‐roll process with a flexible substrate.

High-Performance Bottom-Gate Poly-Si Polysilicon–Oxide–Nitride–Oxide–Silicon Thin Film Transistors Crystallized by Excimer Laser Irradiation for Two-Bit Nonvolatile Memory Applications

High-performance bottom-gate (BG) poly-Si polysilicon-oxide-nitride-oxide-silicon (SONOS) TFTs with single grain boundary perpendicular to the channel direction have been demonstrated via simple excimer-laser-crystallization (ELC) method. Under an appropriate laser irradiation energy density, the silicon grain growth started from the thicker sidewalls intrinsically caused by the bottom-gate structure and impinged in the center of the channel. Therefore, the proposed ELC BG SONOS TFTs exhibited superior transistor characteristics than the conventional solid-phase-crystallized ones, such as higher field effect mobility of 393 cm2/V-s and steeper subthreshold swing of 0.296 V/dec. Due to the high field effect mobility, the electron velocity, impact ionization, and conduction current density could be enhanced effectively, thus improving the memory performance. Based on this mobility-enhanced scheme, the proposed ELC BG SONOS TFTs exhibited better performance in terms of relatively large memory window, high program/erase speed, long retention time, and 2-bit operation. Such an ELC BG SONOS TFT with single-grain boundary in the channel is compatible with the conventional a-Si TFT process and therefore very promising for the embedded memory in the system-on-panel applications.

15.4: Backplane Process Technology for AMOLEDs with Bottom‐Gate TFTs and Laser Annealing

AbstractTFT backplane process for AM‐OLED was developed by integrating a G8 compatible CW green laser annealing into conventional bottom‐gate TFT process. Novel coating channel‐etching‐stopper (CES) and contact doping processes achieved the same high TFT performance as LTPS without critically increasing extra process steps.

Improvement of Outdoor Readability Using Novel Switchable Transmissive and Reflective Twisted Nematic LCD

For the first time, we have fabricated a novel Switchable Transmissive and Reflective (STR) LCD based on dual gap TN (Twisted-Nematic) mode using a general a-Si TFT process. This new technology creates ultra low power LCD using reflective mode. This new device has no power consumption of backlight in ordinary room light environment. Moreover our new LCD offers superior outdoor visibility and enhanced portability to user. We will show vision as a future LCD mode for portable electronic devices.

6.3: Amplified Intrinsic Fringe‐Field MVA LCDs for WVGA Smart Phones, Full HD 1920 × 1080 Tablet PCs, and LC TVs

AbstractWe have successfully fabricated amplified intrinsic fringe field AIFF MVA LCDs for both smart phone and TV applications. We achieved a transmission of 4.2% in a 70% NTSC color 3.8‐in WVGA panel with 246 pixel per in using a standard 5‐mask TFT process. Using a 6‐mask process improved the transmission to 4.9%. These pixel designs may be used for full HD 1920×1080 tablet PCs displays. We transformed a 26‐in WXGA LC TV from TN mode to AIFF MVA mode using only one mask change from the TN masks. The measured transmission between 5.1 and 5.5% is greater than all published MVA and IPS LC TV displays. The AIFF MVA LCD design eliminates the need for any protrusions or ITO slits in both TFT and ITO substrates, as well as the need for special driving schemes and materials. The AIFF MVA is therefore a low‐cost, high transmission, high contrast‐ratio, and wide viewing‐angle solution for both small‐medium and large size LCD applications.

Dynamic Characteristic Optimization of 14 a-Si:H TFTs Gate Driver Circuit Using Evolutionary Methodology for Display Panel Manufacturing

For thin-film transistor liquid crystal display (TFT-LCD) panel manufacturing, a gate driver circuit with amorphous silicon TFT plays an important role. In this paper, an amorphous silicon gate (ASG) driver circuit is optimized to improve circuit's dynamic characteristics. The adopted simulation-based evolutionary method integrates genetic algorithm and circuit simulator on the unified optimization framework. The circuit consisting of 14 hydrogenated amorphous silicon TFTs (a-Si:H TFTs) used in a large panel is optimized for the given specifications of the rise time <; 1.5 μs, the fall time <; 1.5 μs, and the ripple voltage <;3 V with minimizing the total layout area. By optimizing the width and passive components of the 14 devices, the results of this study successfully meet the desired specifications, where the sensitivity analysis is further conducted to verify the characteristic variation with respect to the optimized parameters. To validate the results, the optimized circuit is fabricated with 4- μm a-Si:H TFT process, and the experimental result confirms the practicability of achieved design. The ripple voltage within 2.0 V is successfully obtained while the rise and fall times satisfy the required specifications for the fabricated sample. A 35% reduction of the optimized total devices width of a-Si:H TFTs is achieved.

P‐140: Novel Switchable Transmissive and Reflective Mode using Dual Gap Twisted Nematic Liquid Crystal Display

AbstractFor the first time, we have fabricated a novel Switchable Transmissive and Reflective(STR) LCD based on dual gap TN (Twisted‐Nematic) mode using a general a‐Si TFT process. This new technology makes ultra low powered LCD can be operated in reflective mode without power consumption of backlight in ordinary room light. Moreover our new LCD gives use superior outdoor visibility and enhanced portability than a normal TN mode. We will show vision as a future LCD mode with low power consumption for portable electronic devices.

24.1: A Vertical Common Electrodes Structure for High Aperture Ratio and Stable IPS Mode TFT‐LCD

AbstractWe developed In‐Plane‐Switching (IPS) mode structure with vertically aligned common electrodes for amorphous silicon (a‐Si) thin film transistor liquid crystal display (TFT‐LCD). We could improve an aperture ratio of the panel with this new structure by the elimination of storage area and compact design. The new vertical structure showed stabilized voltage ripple, DC charge and flicker variation by RC delay reduction and direct voltage driving from every driver IC. The panel was fabricated with the conventional a‐Si TFT process. We focused on making a new structure to get better quality of image compared to previous IPS mode TFT‐LCD.

P‐35: 5‐Mask PMOS TFT Process Architecture for Large Size AMOLEDs

AbstractA 5‐mask TFT process architecture has been developed for AMOLED backplanes. The new process has 3 less photo mask steps compared to a normal 8‐mask LTPS process architecture. When compared to a TV display based on the conventional process, the 5‐mask process resulted in a 14‐inch AMOLED display with picture quality of nearly identical performance. for reduction of the photo mask count, an IOS capacitor structure was designed as a storage capacitor, for which no additional photo mask is needed. C‐V behavior of the IOS capacitor was similar to that of an MIM C‐V plot over the range of 1kHz to 1MHz. Both the integrated scan circuit and 6T‐1C Vth compensation circuits have been verified to work well. A low‐resistance metal bus line was also developed in order to be able to drive a 55‐inch FHD AMOLED at 240Hz. It is expected that these developments will enable cost‐competitive large sized AMOLED TV in the future