Test Data Volume Research Articles

Dynamic Shift to Reduce Test Data Volume in Sequential Circuit Testing

Testing of VLSI circuits are normally a tedious process due to the test data volume. It leads to extra power dissipation along with minimum fault coverage.This project presents a test data volume (TDV) reduction method for designs utilizing extremely high compression configurations, and it enables reducing the pin count interfacing with the Automatic Test Equipment. Based on the encoding requirements for every test cube, the proposed test compression method changes the number of shift cycles used to load the test stimuli dynamically. No additional pins or modification of the existing scan chains is needed, making the proposed method work with standard benchmark sequential circuits. A modification is proposed to reduce the test access time ,that is single cycle access with hold mode and single cycle access without hold mode. Instead of a long scan chain ,if each of the scan cells are tested separately in a single clock will reduce the access time and hence the effective testing time of sequential circuits.

Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression

As technology processes scale up and design complexities grow, system-on-chip integration continues to rise rapidly. According to these trends, increasing test data volume is one of the biggest challenges in the testing industry. In this paper, we present a new test data compression method based on reusing a stored set with tri-state coding (TSC). For improving the compression efficiency, a twisted ring counter is used to reconfigure twist function. It is useful to reuse previously used data for making next data by using the function of feedback of the ring counter. Moreover, the TSC is used to increase the range information transmission without additional input ports. Experimental results show that this compression method improves a compression ratio and a test time on both International Symposium on Circuits and Systems’89 and large International Test Conference’99 benchmark circuits in most cases compared to the results of the previous work without a heavy burden on the hardware.

Test Data Compression and Power Reduction Using Similarity Based Reordering Technique for Wireless Systems

System-on-Chip is the major challenge for both design and testing engineers due to its increase in power consumption. The system consumes more power in test mode than the normal mode due to the switching activity that takes place between test data. Similarly, in test mode the volume of test data used is very high when compared to normal mode. This paper presents a novel test data compression approach which simultaneously reduces test volume, test power consumption with less decoder complexity. A test data compression when combined with efficient preprocessing such as filling and reordering of test patterns leads to efficient compression and power reduction. These are some preprocessing steps prior to the compression coding, affects the power. In this paper, the preprocessing steps proposed are column wise bit filling; Similarity based test vector reordering, difference vector techniques. This approach with Modified Golomb coding is proposed to improve the compression as well as to reduce the scan in peak power and average power. This approach efficiently decreases the switching activity and also very simple method to combine with run length based coding. The Power reduction is very efficient by this proposed method compared to other preprocessing methods. A careful analysis of bit filling is proposed that leads to significant reduction in peak and average power. Similarity based test vector reordering technique is also proposed to reorder the test data for reducing the switching activity that takes place in test data and reduces the power consumption. The difference vector is applied which leads to increase in the run length of 0s.The modified Golomb algorithm proposed next can efficiently compress the test set that composed of both 0s and 1s.The decompression architecture is also presented in the paper. Experimental results on ISCAS'89 benchmark circuits show that the proposed approach efficiently reduces the volume of test data and the peak, average power consumption.

LFSR-Based Generation of Multicycle Tests

This paper describes a procedure for computing a multicycle test set whose scan-in states are compressed into seeds for a linear-feedback shift register, and whose primary input vectors are held constant during the application of a multicycle test. The goal of computing multicycle tests is to provide test compaction that reduces both the test application time and the test data volume. To avoid sequential test generation, the procedure uses a single-cycle test set to guide the computation of multicycle tests. The procedure optimizes every multicycle test, and increases the number of faults it detects, by adjusting its seed, primary input vector, and number of functional clock cycles. Optimizing the seed instead of the scan-in state avoids the computation of scan-in states for which seeds do not exist. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of the procedure.

System-on-Chip Test Data Compression Based on Split-Data Variable Length (SDV) Code

System-on-a-chips with intellectual property cores need a large volume of data for testing. The large volume of test data requires a large testing time and test data memory. Therefore new techniques are needed to optimize the test data volume, decrease the testing time, and conquer the ATE memory limitation for SOC designs. This paper presents a new compression method of testing for intellectual property core-based system-on-chip. The proposed method is based on new split- data variable length (SDV) codes that are designed using the split-options along with identification bits in a string of test data. This paper analyses the reduction of test data volume, testing time, run time, size of memory required in ATE and improvement of compression ratio. Experimental results for ISCAS 85 and ISCAS 89 Benchmark circuits show that SDV codes outperform other compression methods with the best compression ratio for test data compression. The decompression architecture for SDV codes is also presented for decoding the implementations of compressed bits. The proposed scheme shows that SDV codes are accessible to any of the variations in the input test data stream.

MVL-based Test Access Mechanism for Big Data Interface

As the complexity of semiconductors grows rapidly, the volume of test data for them also increases enormously. Multi-Valued Logic(MVL) is one of solutions to meet test economics. MVL-based ATE can transmit several test data bits concurrently in a line, because MVL can have more than two values. Thus, even if the test clock speed is the same as DUT's, the test data can be expanded in proportional to the MVL bit steps. Moreover, the test accessories like a socket is easy to make due to lower test clock than binary TAM's one and the power consumption will be smaller too.However, MVL interface is vulnerable to noise for the small noise margin and needs decoders to convert MVL to binary data. In this paper, we simulate previous quaternary decoders if they are suitable for MVL decoder. After the simulation, an efficient decoder structure for MVL interface is proposed to improve the performance as well as the size.

Two-Dimensional Static Test Compaction for Functional Test Sequences

A restoration based static test compaction procedure removes unnecessary test vectors from a functional test sequence in order to reduce its length. To allow the procedure to reduce the storage requirements of the sequence further, this paper introduces a new approach where a single stored sequence is used for applying several different functional test sequences. Under this approach, the stored sequence is considered as two-dimensional arrays with different dimensions. Each array yields a different test sequence, which is a permutation of the stored sequence. When the permutations are effective in detecting target faults, an existing static test compaction procedure, with certain modifications, can reduce the length of the stored sequence, and rely on the application of the permutations to detect all the target faults. Simulation results show significant reductions in the input test data volume. The cost of increased numbers of clock cycles for test application can be utilized for increasing the fault coverage of non-target faults.

A novel two-fold state skip logic Built-In Self-Test scheme for digital circuits

Recent developments in the field of very-large-scale integration (VLSI) testing have led to a demand for fault diagnosis in very-large-scale integration circuits. However, the problem of test pattern generation becomes very difficult as the size of circuits increases. Proficient techniques for test pattern generation are necessary to reduce the test sequence length and testing time. In conventional methods, Automatic Test Pattern Generation (ATPG) and Design for Test (DFT) are used for test pattern generation and fault insertion in netlist files. The complexity faced in Automatic Test Pattern Generation exponentially increases with respect to the circuit size. In circuits with a large number of stuck-at-fault errors, the conventional verification sequence fails to provide acceptable fault coverage and low power consumption. A twofold state skip (TFSS) logic is developed to achieve a low scan power by skipping long scan chains to reduce switching activities. This work addresses the above-mentioned issues faced in Automatic Test Pattern Generation in VLSI circuits and examines all detectable faults using a twofold state skip logic. The proposed approach is efficient and verified on ISCAS 89 & 85 benchmark circuits; the results indicate a considerable reduction in the test data volume and thus a significant reduction in power consumption.

A Power Efficient Test Data Compression Method on Count Compatible PRL Coding

A realistic test sets compression method is proposed to effectively reduce test data volume and test application time during system-on-chip (SoC) scan testing, count compatible pattern run-length (CCPRL) coding method counts the consecutive number of the equal to or contrary to the retained patterns, it modifies the compatible code of variable-length pattern run-length (VPRL) coding rules and adds a count code block to replace original rules for increasing compression ratio. Next, the decoder architecture and the state diagram of finite state machine (FSM) are designed. In addition, the power model of test vectors is analyzed, and the power consumption of scanned-in vectors is roughly evaluated. The six largest ISCAS'89 benchmark circuits verify the proposed coding method has a shorter codeword. Experiment results shows that all compression ratios have been increased as much as possible, test data decompression is lossless, less test application time is consumed, yet the peak power and average power consumption of scanned-in test vector needs to be further improved for modern circuit scan testing.

Failure behaviors of reinforced concrete beams subjected to high impact loading

To attain a better understanding of the failure behavior of reinforced concrete (RC) beams under impact load, series of high speed impact experiments were performed using an instrumented drop-weight impact machine. The test program was successful in providing a substantial volume of test data including impact loads, mid-span deflections, crack profiles and strains. These data was analyzed, focusing on the impact load characteristics and the impact behaviors of RC beams. Various characteristic values and their relationships were investigated such as the drop height, the static flexural load-carrying capacity, the input impact energy and the beam response values. Two empirical formulas were proposed to estimate the maximum and residual deflection of the beam based on the static flexural load-carrying capacity and the input impact energy. The applicability of the proposed equations was confirmed by comparison with the experimental results obtained by other researchers.

Reduced-code test method using sub-histograms for pipelined ADCs

The measurement of static test parameters for an analog-todigital converter (ADC) requires a large volume of test data, especially for a high-resolution ADC. This paper proposes a reduced-code test method for pipelined ADCs that does not compromise test accuracy. The proposed method calculates fault information at each stage by using sub-histograms. The simulation results based on 12-bit pipelined ADCs show a maximum integral nonlinearity error of 0.590 LSB with only 3.92% of the codes required for the conventional histogram-based method.

A Novel Architecture for Scan Cell in Low Power Test Circuitry

Over the past decade VLSI manufacturing industry flourishing very rapidly. Now a days hundreds and thousands of millions of transistors that are incorporated on a chip. As the circuit complexity increasing design for test circuitry also became more complex. These complex test circuitry heavily stressed to check the functionality of the CUT (Circuit under Test). Compared with normal functional mode, Power dissipation during test mode is much higher. Power dissipation during testing is more than twice compared with normal functional mode. Large Test data volume and High power consumption are the main problems in Design for Testability. This excessive power consumption is mainly due to switching of the scan cells. The technique proposed in this paper reduces switching activity in the scan cells there by the power consumption during testing can be reduced. In the proposed scan cell architecture some of the idle flip-flops are disabled during scanning using a control signal. By disabling idle flip-flops can be possible by an external control signal or with any internal signal. Excessive power consumption during testing may cause performance degradation and high system cost. These problems can be eliminated with the proposed scan cell architecture.

On System-on-Chip Testing Using Hybrid Test Vector Compression

This paper presents a comprehensive hybrid test vector compression method for very large scale integration (VLSI) circuit testing, targeting specifically embedded cores-based system-on-chips (SoCs). In the proposed approach, a software program is loaded into the on-chip processor memory along with the compressed test data sets. To minimize on-chip storage besides testing time, the test data volume is first reduced by compaction in a hybrid manner before downloading into the processor. The method uses a set of adaptive coding techniques for realizing lossless compression. The compaction program need not to be loaded into the embedded processor, as only the decompression of test data is required for the automatic test equipment (ATE). The developed scheme necessitates minimal hardware overhead, while the on-chip embedded processor can be reused for normal operation on completion of testing. This paper reports results on studies of the problem and demonstrates the feasibility of the suggested methodology with simulation runs on the International Symposium on Circuits and Systems (ISCAS) 85 combinational and ISCAS 89 full-scan sequential benchmark circuits.

三维扫描树叶子节点和TSVs数量的优化方法

Scan tree architecture can effectively reduce test data volume, test time and test cost for integrated circuits. To reduce the number of leaf nodes and TSVs(through silicon vias）in scan tree for three dimensional integrated circuits, this paper firstly draws the conclusion that the minimum number of leaf nodes is the number of scan cells contained in the maximal compatible group. Then, the necessary and sufficient condition achieving the minimum number of leaf nodes is presented. On the basis above, a heuristic algorithm is proposed, which can minimize the number of leaf nodes and reduce consumed TSVs as many as possible. Experimental results demonstrate the effectiveness of the proposed technique.

ACI-DAfStb Databases for Shear Tests on Slender Reinforced Concrete Beams with Stirrups

Nearly all code provisions for the shear capacity of structural concrete members without shear reinforcement have been empirically derived and some were calibrated decades ago. Since then, a significant volume of new test data has been generated that can aid in understanding. To address this issue, a database of 439 shear test results had been created in 2003 that contained the data of beams without shear reinforcement subjected to point loads. The 2003 database was considerably expanded in recent years by a joint ACI-DAfStb (American Concrete Institute - Deutscher Ausschuss fur Stahlbeton, German Committee for Structural Concrete) Group, with new test data including 40 tests on beams with uniformly distributed loads. The newly extended database now contains 784 tests that can be used for the evaluation of shear design provisions. A comparison of ACI 318-11 Eq. (11-3) with this extended database has revealed that current code provisions can be unconservative for large, lightly reinforced members and that the influences of important parameters are not adequately captured.

Scan power-aware deterministic test scheme using a low-transition linear decompressor

Growing test data volume and excessive testing power are both serious challenges in the testing of very large-scale integrated circuits. This article presents a scan power-aware deterministic test method based on a new linear decompressor which is composed of a traditional linear decompressor, k-input AND gates and T flip-flops. This decompression architecture can generate the low-transition deterministic test set for a circuit under test. When applying the test patterns generated by the linear decompressor, only a few transitions occur in the scan chains, and hence the switching activity during testing decreases significantly. Entire test flow compatible with the design is also presented. Experimental results on several large International Symposium on Circuits and Systems’89 and International Test Conference’99 benchmark circuits demonstrate that the proposed methodology can reduce test power significantly while providing a high compression ratio with limited hardware overhead.

Concurrent Core Test Based on Partial Test Set Reusing

A novel concurrent core test approach is proposed to reduce the test cost of SoC. Before test, a novel test set sharing strategy is proposed to obtain a minimum size of merged test set by merging the test sets corresponding to cores under test (CUT).Moreover, it can be used in conjunction with general compression/decompression techniques to further reduce test data volume (TDV). During test, the proposed vector separating device which is composed of a set of simple combinational logical circuit (CLC) is designed for separating the vector from the merged test set to the correspondent test core. This approach does not add any test vector for each core and can test synchronously to reduce test application time (TAT). Experimental results for ISCAS’ 89 benchmarks have been rproven the efficiency of the proposed approach.

Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique

Power consumption during scan testing operations can be significantly higher than that expected in the normal functional mode of operation in the field. This may affect the reliability of the circuit under test (CUT) and/or invalidate the testing process increasing yield loss. In this paper, a scan chain partitioning technique and a scan hold mechanism are combined for low power scan operation. Substantial power reductions can be achieved, without any impact on the test application time or the fault coverage and without the need to use scan cell reordering or clock and data gating techniques. Furthermore, the proposed design solution for scan power alleviation, permits the efficient exploitation of X-filling techniques for capture power reduction or the use of extreme (power independent) compression techniques for test data volume reduction.

Input Test Data Volume Reduction for Skewed-Load Tests by Additional Shifting of Scan-In States

Test data compression methods reduce the input test data volume by allowing compressed tests to be stored on a tester. Additional reductions in the input test data volume can be achieved if each stored test is used for producing several different tests. Skewed-load tests create a unique opportunity to expand a stored test into several different skewed-load tests by continuing to shift the scan-in state for one or more additional clock cycles. This opportunity for test data volume reduction beyond test data compression is introduced in this paper. The paper describes a procedure that starts from a given skewed-load test set. The procedure removes tests from the test set and recovers the fault coverage by applying several tests based on every stored test.

Selective Compression Technique using Variable-to-Fixed and Fixed-to-Variable Codes

In this paper, we propose two code based techniques: Variable-to-Fixed codes and Fixed-to-Variable codes for power efficient test data compression. The proposed scheme with the aim of achieving high compression ratio and low power consumption relies on reducing, the number of bits for representing the original test vector and the number of transitions per second. Simulation results on ISCAS‟89 benchmarks demonstrate that this optimization methodology helps achieve reduced test data volume and power than previous schemes for cases where the number of specified bits in the test set is relatively few.