三维扫描树叶子节点和TSVs数量的优化方法

Abstract

Scan tree architecture can effectively reduce test data volume, test time and test cost for integrated circuits. To reduce the number of leaf nodes and TSVs(through silicon vias）in scan tree for three dimensional integrated circuits, this paper firstly draws the conclusion that the minimum number of leaf nodes is the number of scan cells contained in the maximal compatible group. Then, the necessary and sufficient condition achieving the minimum number of leaf nodes is presented. On the basis above, a heuristic algorithm is proposed, which can minimize the number of leaf nodes and reduce consumed TSVs as many as possible. Experimental results demonstrate the effectiveness of the proposed technique.