Development of a high-yield via-last through silicon via process using notchless silicon etching and wet cleaning of the first metal layer

Abstract

A high-yield via-last through silicon via (TSV) process has been developed using notchless Si etching and wet cleaning of the first metal layer. In this process, the notching was suppressed by optimizing the deep Si etching conditions and wet cleaning was performed using an organic alkaline solution to remove reaction products generated by the etchback step on the first metal layer. By this process, a number of small TSVs (TSV diameter: 6 µm; TSV depth: 22 µm; number of TSVs: 20,000/chip) could be formed uniformly on an 8-in. wafer. The electrical characteristics of small TSVs formed by this via-last TSV process were investigated. The TSV resistance determined by four-terminal measurements was approximately 24 mΩ. The leakage current between the TSV and the Si substrate was 2.5 pA at 5 V. The TSV capacitance determined using an inductance–capacitance–resistance (LCR) meter was 54 fF, while the TSV yield determined from TSV chain measurements was high (83%) over an 8-in. wafer.