Scan Tree Design for 3-D ICs with Constraint of Leaf Nodes Number

Abstract

To reduce the test time and test cost of 3-D ICs, this paper proposed a design method of building three-dimensional scan tree, which can optimize the number of through silicon via (TSV) when limit the leaf nodes number. The proposed technique partitioned compatible groups in every layer based on test vectors, and listed requirements for building three-dimensional scan tree, which should be translated to integral linear programming model. Integer linear programming tool sort compatible groups order to build three-dimensional scan tree with minimum number of TSV. Experimental results indicate the proposed method can effectively reduce the number of TSV compared to the existing method under the condition of the same leaf nodes number.