Test Access Port Research Articles

Forensic imaging of embedded systems using JTAG (boundary-scan)

This paper describes how to use JTAG (JTAG: Joint Test Action Group, also called boundary-scan) for producing a forensic image (image: an one-on-one copy of data found on an exhibit) of an embedded system. A JTAG test access port is normally used for testing printed circuit boards or for debugging embedded software. The method described in this paper uses a JTAG test access port to access memory chips directly. By accessing memory chips directly, the risk of changing data in the exhibit is minimized. Also user level passwords can be omitted.

Measurement of electrical parameters using mixed-signal test bus, IEEE Std. 1149.4

Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1, was developed to ease the test of printed circuit board assemblies (PCBAs). The development of packaging technology and the increasing functionality of a circuit have made traditional testing methods, such as in-circuit tests and functional testing through edge connectors much more difficult or even impossible. Mixed-Signal Test Bus, IEEE Std. 1149.4, which is a further development of IEEE Std. 1149.1 has been developed to enable the testing of analog components and analog interconnects on PCBAs. IEEE Std. 1149.4 compliant circuits contain an analog bus and analog switches. Techniques applicable to the measurement of impedances via IEEE Std. 1149.4 compliant circuits are presented. A filter has been tested and the results are promising. It has been shown by both measurement and simulation that switching impedances can be managed in such a manner that the influence of deviations from their nominal value can be estimated.

Clock generation and distribution for the first IA-64 microprocessor

The clock design for the first implementation of the IA-64 microprocessor is presented. A clock distribution with an active distributed deskewing technique is used to achieve a low skew of 28 ps. This technique is capable of compensating skews caused by within-die process variations that are becoming a significant factor of the clock design. The global, regional and local clock distributions are described. A multilevel skew budget and local clock timing methodology are used to enable a high-performance design by providing support for intentional clock skew injection and time borrowing. By providing a test access port interface to the deskew architecture and the incorporation of the on-die-clock-shrink, this design is equipped with two very powerful post-silicon timing debug tools that are critical to high-performance microprocessor design and enabled quick time-to-market.

Hierarchical system test by an IEEE 1149.5 MTM-bus slave-module interface core

An IEEE 1149.5 module test and maintenance (MTM) bus slave module interface core is presented, which is used for direct access from the system bus to the IEEE 1149.1 chip-level or on-chip buses to facilitate hierarchical system test and diagnosis. The hierarchical test methodology also is presented, which is applicable to the system-on-chip environment, All the standard 1149.1 instructions, such as SAMPLE/PRELOAD, EXTEST, BYPASS, and even RUNBIST, can be performed within three 1149.5 read/write-data message cycles. The messages are transmitted between the MTM-bus master module (Ill-module) and the slave module (S-module). We adopt the full test access port control method to activate the 1149.1 boundary-scan paths via the 1149.5 MTM-bus. Our S-module interface circuit implements 16 CORE commands and one read/write-data command. It has been prototyped using a field-programmable gate array chip and implemented by a full-custom chip. Hierarchical test of multiple 1149.1 compatible boards has been experimentally verified.

A 96-channel, 500 ps resolution TDC board for the BaBar experiment at SLAC

A TDC board has been designed and built to complete the readout of the Instrumented Flux Return of the BABAR experiment at the Stanford Linear Accelerator Center. The board has 96 input channels and makes use of 3 general purpose TDC chips designed at CERN, with time resolution up to 500 ps and configurable via a Test Access Port (IEEE standard 1149). Data are stored before readout in a multievent buffer. Communication with BABAR DAQ system is realized through 3 serial lines on the backplane connector. All the logic, including internal registers and the interfaces with the BABAR protocol and the TAP controller, is implemented in two fast FPGAs. The board is designed to work at 59.5 MHz clock frequency.

Synchronizing the IEEE 1149.1 test access port for chip level testability

IEEE STD 1149.9 is a widely accepted testability standard in the industry. Although its mandatory provisions focus narrowly on board level assembly verification testing, primarily via the boundary-scan register, its test access port (TAP) and many optional provisions make the standard usable for a much broader range of applications. Since its inception, numerous extensions and applications have been proposed that allow the standard's TAP to be used at the system level for general system-level test and maintenance tasks and at the chip level for accessing chip-level testability features. Chip-level applications thus far have used the port for accessing the chip's scan design or for simple triggering of on-chip built-in self-test features via the RUNBIST instruction. Applications requiring general access to chipwide testability features that operate at the full chip-clock rate have been rare, primarily because of one of the standard's basic tenets-namely, its dedicated test clock. This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features.

Diagnosis of clustered faults and wafer testing

A probabilistic diagnosis algorithm is presented for constant degree structures. The performance of the algorithm is analyzed under a negative binomial failure distribution to account for fault clustering. It is shown that the algorithm can correctly identify almost all units even when the yield is low (much lower than 50%) and when faults are clustered. A wafer test structure is proposed, which utilizes the test access port of each die to perform comparison tests on its neighbors and incorporates a localized version of the diagnosis algorithm to determine the status of each die. Both the test time and the diagnosis time are invariant with respect to the number of dies on the wafer. The saving of test costs could be significant as compared with probe testing, because with probe testing dies are probed one at a time while they are tested in parallel with this scheme. The scheme is unique in that it is shown to work well when faults are clustered and when the yield is low.

Designing “Dual Personality” IEEE 1149.1 Compliant Multi-Chip Modules

The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture Standard can be used at many different levels in the integration hierarchy of a product. However there is one level where using the standard poses some difficulty. Multi-Chip Modules (MCM) belong to this level. This paper explores the problem and proposes a set of solutions for various classes of MCMs.

Off-chip I ddq monitor with standardtest interface

Off-chip current testing is being considered as an efficient mechanism for improving the quality of electronic systems at the printed circuit board level. This well known fact is linked with the industry accepted testing interface standard IEEE P1149.1 (‘Standard test access port and boundary-scan architecture’). A specific integrated circuit with the capability of concurrently measuring the quiescent current level for two integrated circuits under test (ICCUT) is presented with its basis, architecture and implementation details. All the functions of the monitors are accessible via the standard test access port.

The boundary scan

Miniaturization trends in integrated circuit (IC) technology have caused many testing problems. As bigger packaged ICs with higher pin counts are more densely packed onto a printed circuit board (PCB), accessing an IC's pins is harder. No longer are the pins mechanically accessible to probes or a bed-of-nails fixture. Therefore, determining which IC or interconnect is faulty is difficult or impossible. Because each IC's input pins cannot be controlled, and each IC's output pins cannot be observed. The boundary scan method was developed with the goal of improving this controllability and observability problem. A shift-register is included next to each IC pin so that input and output values can be serially shifted in and out. This reduces the need to use probes to control and observe. Also, the output of each IC's scan register can be connected with the input of another IC's scan register. This effectively creates one big scan chain per PCB, further reducing points that must be mechanically probed. The inclusion of a scan-register on each IC allows: 1) the observation of each IC during normal operation; 2) the test of interconnects between ICs, and 3) the isolation of the IC from others so it can test itself. The IEEE Standard 1149.1 Test Access-Port and Boundary Scan defines the test logic for implementing a boundary scan test architecture. Example circuits were designed in CMOS. A boundary scan cell is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Boundary-Scan Testing for Electronic Subassemblies and Systems

Since 1990, an important change in electronic design and test methodologies has been under way. The change is facilitated by ANSI/IEEE 1149.1, which is known as the Test-Access Port and Boundary-Scan Architecture standard. AT&T Bell Laboratories played a major role in the promulgation of this standard, and AT&T design and manufacturing engineers have been implementing its provisions for several years. This paper reports on the ways in which the standard has been employed in developing AT&T products, the benefits that have been achieved, and the future opportunities available using the technology it details.

Case study of 1149.01 microprocessor implementations

This paper describes selected implementation issues of IEEE 1149.1 Std. Test Access Port and Boundary-Scan Architecture for three Motorola VLSI CMOS microprocessors. Problems and solutions that arose during implementation of standard features and additional public instructions are discussed.

Testability guidelines for multichip modules

Because of the advantages that they offer in clock rates, real-estate savings, power dissipation savings, weight etc., multichip modules are rapidly becoming a reality in commercial electronics. Solutions to the problems of handling and testing module components and to the fabrication of the modules themselves have pretty much been solved. However, before MCMs can become a reality, it will be necessary to solve the problems associated with the testing and repairing of modules. This article suggests a set of design guidelines which will minimize the probability of undetectable defects and maximize the probability of diagnosing detectable defects. The guidelines revolve mainly around the IEEE 1149.1-1990 Test Access Port and Boundary-Scan Architecture standard as adopted by the IEEE.

A D&amp;T special report-boundary scan: and end-of-term report-IEEE Std 1149.1 survey results

The level of commercial support for and the extent to which manufacturers are using IEEE Std 1149.1 Standard Test-Access Port and Boundary-Scan Architecture in their products are described. The author's involvement in the IEEE 1149.1 Working Group is discussed. >

An implicitly testable boundary scan TAP controller

The design of a test access port controller conforming to the boundary scan standard is described, which is implicitly tested while it is working. It is based on a novel self-test technique also applicable to other controller designs. This technique uses a signature register as state register, such that no reconfiguration of that register is necessary during self-test. This way the test of the test access port can be efficiently incorporated into the system self-test. No additional I/O pins beyond those of the boundary scan standard are necessary, neither does the test program have to be changed to incorporate the test of the controller. The solution only requires moderate hardware overheads, nevertheless it guarantees a high fault coverage.

Testability on TAP

A new approach to testing based on boundary scan is discussed. This technique gives access to individual chip pins by including a little standardized circuitry and a test access port (TAP) on every IC. Boundary scan basics are reviewed, and three principal types of tests that can be performed with the boundary-scan register are described. They are: interconnect tests, using the EXTEST (external test) instruction; chip tests, using the INTEST instruction; and sampling, using the SAMPLE instruction. >

Testing interconnections to static RAMs

A method for testing the interconnections of ordinary static RAMs with a processor that has a boundary-scan register and an IEEE 1149.1 test-access port is described. The method uses an enhanced boundary-scan-register design that manipulates the test-access-port controller states to meet the static RAM's timing constraints. The implementation is more economical than a boundary-scan register that strictly conforms to IEEE 1149.1. Test operation is more efficient, requiring a third of the number of scan operations. A test-pattern set and a method for detecting and diagnosing the interconnection faults on RAMs are also described. The test-pattern set can be enhanced as necessary to increase coverage and diagnosing ability and to handle any RAM configuration. The implementation of the proposed boundary-scan register is independent of the test algorithm used. It is believed that the methodology is extendable to RAMs that use an access protocol different from the one described, for example dynamic RAMs and synchronous RAMs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A low-cost tester for boundary scan

This paper describes the architecture and implementation of a controller for the test access port (TAP) of the standard test access port and boundary-scan architecture as defined in IEEE Std. 1149.1–1990. This controller allows any PC to be used for testing chips, boards and/or systems provided with boundary scan test facilities.