Ternary Logic Research Articles

Note on Probability of Logical Sentencesand the Linda Problem

This paper presents a logical concept of probability which seems to be obvious, as it is, but the author is not aware of any elaboration of a developed studies on the issue or of any special philosophical application of it. Such a probability of the formula A, of the language of the propositional logic, is the quotient of the number of Boolean valuations of formula A of the classical propositional calculus, which takes the logical value 1, to the number of all Boolean valuations of such a formula A. An application of this concept of logical probability to the solution of the Linda problem is given.

A reconfigurable binary/ternary logic conversion-in-memory based on drain-aligned floating-gate heterojunction transistors

A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before.

Design of CNTFET-based Ternary Ring and Up–Down Counter Cells

In recent times, the multi-valued logic (MVL) design has been widely explored in the designing of digital computing circuits as the goals of enhanced processing capability with reduced interconnect complexity and small chip area are achieved. Hence, this work describes the design methodology of ternary logic-based asynchronous and synchronous up-counter, down-counter, and ring-counter designs using D-flip-flops in carbon nanotube technology. Carbon nanotube-field-effect transistors (CNTFETs)’ unique feature of altering the device threshold voltage by making variations in CNT diameter is exploited for the realization of multiple voltages in ternary logic design. Here the principle of the master-slave scheme is adopted for the designing of Dual shift-single shift and Single shift-dual shift-D-flip-flop circuits using the cyclic property of shifting operators. These flip-flop designs are further extended to construct multiple-digit counter structures which are suitable for realizing the logic functionality of up-counter, down-counter, and ring-counter designs. To exploit ternary logic increased computation capability benefit, a mode control up/down counter circuit is designed in which a single module is generating up and down-counting sequence based on applied mode input. To investigate the performance of the proposed designs, the simulations are performed using the Synopsys HSPICE simulator considering the 32 nm Stanford CNTFET model. According to the simulation results, a maximum energy consumption reduction up to 55% is obtained compared to the counterpart. Hence, the increased computational capability of three-valued logic is exploited in the presented work to achieve energy enhancements in designing ternary sequential circuits.

Analysis of Ternary logic arithmetic circuits

Analysis of Ternary logic arithmetic circuits

Novel approach for implementing ternary value logic devices showing negative differential transconductance characteristics by Fowler–Nordheim tunneling

Ternary value logic (TVL) devices are gaining attention owing to the limitations of binary devices in handling the increasing amount of information. However, the development of ternary devices has been hindered by the complex structures and use of materials lacking CMOS compatibility. This study presents a novel approach to develop ultra-simple TVL devices using thin-tunnel gate dielectrics of AlOx films and TiO2 channel layer. TVL devices are obtained by employing TiO2-based transistors with AlOx films as an oxide tunneling dielectric layer. The device exhibits typical transistor switching characteristics at low gate voltage (VG) and negative differential transconductance owing to Fowler−Nordheim tunneling current at high VG. The reversible implementation of three states, namely, ON, intermediate (INT), and OFF, with the same probability, is demonstrated with excellent reproducibility even after 200 cycles. A circuit is constructed to demonstrate the three output voltage states with respect to the input voltage by connecting the TVL device to a resistor. Additionally, the value and width of the plateau region of the INT output voltage state can be tuned by adjusting the variable resistance values. These highly simplistic TVL devices have the potential for application in low-power, highly integrated, and ultra-miniature electronic devices, thanks to their high level of CMOS compatibility.

Conceptualising critical thinking and its research in teacher education: A systematic review

ABSTRACT Pre-service teachers play a crucial role in fostering critical thinking among students to enhance their effectiveness in the 21st century. This systematic review examines 43 empirical studies to gain deeper insights into the concept of critical thinking in teacher education. We identified two primary definitions of critical thinking: the logical sense and value sense, both rooted in a discipline-oriented framework. The findings indicate that the logical sense, particularly the philosophical approach, predominantly informs research conducted on pre-service teachers. However, when it comes to critical thinking disposition, research results often fall short in demonstrating significant development, underscoring the contextual nature of critical thinking. Critical thinking is a sociological research method used to logically evaluate a problem by creating awareness of problematic knowledge and social situations. After analysing the influence of the relationship between critical thinking and research on critical thinking development in pre-service teachers, our findings suggest that there are limitations to cultivating critical thinking; further verification is needed regarding pre-service teachers’ ability to transfer critical thinking among various contexts or situations. This review emphasises the significance of embracing the multifaceted and context-bound aspects of critical thinking and good judgment for thinking quality in pre-service teacher education research.

A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

The Conventional Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) design techniques have limitations in designing the Integrated Circuit (ICs), especially with memories of multiple valued logic (MVL) in nanotechnologies. FinFET technologies provide the possibilities of low logic gates and small chip areas with high speed. Memories play an essential role in all types of devices. This paper aims to optimize the power and increase the speed of the SRAM Cell and Array using different techniques in 18nm FinFET technology. The presence of a ternary input provides an additional degree of freedom for the operation of the memory cell. The SRAM cells are also implemented at a Quantum level to improve the results in terms of area, energy, and speed. Simulation and Analysis of the design is done using Cadence Virtuoso Analog Design Environment Tool and Quantum Dot Cellular Automata Designer Tool. The proposed Multi-Threshold Complementary MOS (MTCMOS) based SRAM Array design exhibits an improvement of 4.56% in power consumption and 19.29% in speed as compared to a Conventional CMOS SRAM Array. The proposed ternary implementation of the MTCMOS-based SRAM cell is found to have a 24.9% reduction in power consumption and a 39% improvement in speed as compared to the proposed conventional ternary CMOS SRAM array while SRAM cell latency is 1 clock cycle. It occupies an area of 0.04 µm2 and consists of 33 quantum cells. The average energy dissipation of this SRAM cell is found to be 40% better than the latest existing literature for the design.

The Value of Unity

The Value of Unity

RECURSIVE TERNARY-BASED ALGORITHM FOR COMPUTING PRIME IMPLICANTS OF MULTI-OUTPUT BOOLEAN FUNCTIONS

The problem of computing the set of prime implicants to represent a Boolean function is a classical problem that is still considered a running problem for research because all known approaches have limitations. The article reviews existing methods for computing prime implicants and highlights their limitations, particularly for multi-output functions and limited scalability due to the growth in memory required to complete the computation. Then it proposes a recursive ternary-based minimization algorithm to compute the prime implicants of multi-output Boolean functions. The algorithm is based on the concept of Programmable Logic Array (PLA) tables, which provide a structured and efficient representation of Boolean functions. The algorithm takes advantage of the ternary logic system to efficiently compute the prime implicants while maintaining scalability for large and complex functions, which has significant implications for digital circuit design and optimization.

A Power Efficient 32 nm Ternary Multiplier using Graphene Nanoribbon Field-Effect Transistor Technology

As circuit complexity grows, designers are exploring ternary logic as an alternative to binary logic to solve interconnection and energy problems. One effective approach to implementing ternary logic-based circuits is to use a multiple-threshold voltage (multi-V th ) design. In particular, graphene nanoribbon (GNR)-based field-effect transistors (GNRFETs) are a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology for sub-32 nm feature sizes, as GNRs have excellent properties that can overcome scaling issues in CMOS. This paper introduces a ternary multiplier implemented with 32 nm GNRFET technology, which demonstrates high efficiency with only 26 transistors. Simulation results show that the proposed multiplier improves power dissipation and product-delay-power (PDP) by at least 37.30% and 22.22%, respectively, compared to existing multiplier designs when run at 0.9 V. Moreover, our proposed design is implemented with a carbon nanotube-based FET (CNTFET) technology. The GNRFET-based multiplier improved power and PDP by 41.77% and 30%, respectively in the cost of increasing the delay by 25%, compared to its CNTFET-based equivalent. Finally, we analyze the proposed multiplier under the process and environmental parameters variations of GNRFET technology. Overall, our results demonstrate the advantages of using GNRFET technology for implementing ternary logic-based circuits and provide insight into the impact of different design choices on performance.

A GM-Based Energy Management Strategy of Hybrid Power System for Hydrogen Fuel Cell Buses

Hydrogen energy is a clean, carbon-free, flexible, efficient, and widely used secondary energy source, which is an ideal alternative to promote the clean and efficient use of traditional fossil fuels. Hydrogen fuel cell bus has the advantages of a high-energy conversion rate, absolute pollution-free, sufficient raw materials, and convenient filling. The hybrid power system, composed of fuel cell and auxiliary energy source, is one of the key technologies to promote the development of hydrogen fuel cell vehicle. This study aims to propose an energy management strategy by analyzing the output characteristics and power allocation of fuel cell and power battery in the hybrid power mode with fuel cell as the main and battery as the auxiliary. A GM (1, N) power prediction strategy was proposed and compared with other strategies as an on-off control strategy and logical threshold value strategy in this study. The variation curves of the battery SOC and fuel cell output power under two working conditions of CCBC and real vehicle conditions were analyzed by using these three strategies, when the initial SOC of power battery is 30%, 70%, and 90%, respectively. Results showed that the power prediction strategy based on GM (1, N) has a better performance in output efficiency and fuel economy when compared to the other two strategies by analyzing the aspects of the battery in the SOC variation and equivalent hydrogen consumption and the fuel cell in the output power variation and hydrogen consumption. This research can be helpful to provide the suggested solution for energy management of the hybrid power system for hydrogen fuel cell buses.

A Logical Modeling of Severe Ignorance

In the logical context, ignorance is traditionally defined recurring to epistemic logic. In particular, ignorance is essentially interpreted as “lack of knowledge”. This received view has - as we point out - some problems, in particular we will highlight how it does not allow to express a type of content-theoretic ignorance, i.e. an ignorance of φ that stems from an unfamiliarity with its meaning. Contrarily to this trend, in this paper, we introduce and investigate a modal logic having a primitive epistemic operator I, modeling ignorance. Our modal logic is essentially constructed on the modal logics based on weak Kleene three-valued logic introduced by Segerberg (Theoria, 33(1):53–71, 1997). Such non-classical propositional basis allows to define a Kripke-style semantics with the following, very intuitive, interpretation: a formula φ is ignored by an agent if φ is neither true nor false in every world accessible to the agent. As a consequence of this choice, we obtain a type of content-theoretic notion of ignorance, which is essentially different from the traditional approach. We dub it severe ignorance. We axiomatize, prove completeness and decidability for the logic of reflexive (three-valued) Kripke frames, which we find the most suitable candidate for our novel proposal and, finally, compare our approach with the most traditional one.

Design and modeling of novel TSV for ternary logic applications

In this paper presents the TSVs are made of conducting material which is implanted in silicon substrate with dielectric liner coated around the metal line. The study of ternary logic signal propagation in through silicon vias is more important since the ternary signals have small noise margins. Moreover, due to the crosstalk noise the fault switching probability is increases in logic circuits. In this work, a novel TSV structure named as metal semiconductor TSVs for the propagation of ternary logic signals has been proposed. Using the proposed model, the probability of occurring the fault tolerance has been reduced and also the performance is enhanced. The proposed model is developed with an analytical RLGC model where the parasitic values are extracted from electromagnetic field solvers. The simulation results of proposed structures are compared with conventional metal–insulator-semiconductor TSVs to show improvements.

Signal Integrity Assessment of GNRFET-Based Ternary Logic for Multi Layered GNR Interconnects with Dielectric Insertion

In this paper, signal integrity assessment is carried out for graphene nanoribbon field effect transistor (GNRFET) based ternary logic with dielectric inserted multi-layered GNR (MLGNR) interconnects. The analyses are carried out for crosstalk effects and eye diagrams with and without shielding lines. In this paper firstly, it is observed that the dielectric inserted MLGNR interconnects show better than copper (Cu) and multiwall carbon nanotube (MWCNT) interconnects. Secondly, active shield technique is adopted, and observed that it exhibits better performance than without shield and passive shield techniques. Also, the power-delay product performance parameter is evaluated and envisaged that active shield technique outperforms passive technique. Further, the eye diagram analysis is carried out for different bit rates. The different performance analyses in the paper have been carried out for 10 nm technology node.

An Alternative Definition of Stable Models Via Łukasiewicz Logic

Extensions of G3 (3-valued Godel logic) were studied as tools for knowledge representation and nonmonotonic reasoning. One of these extensions was studied and baptized as G′ 3 by Osorio et al. as a tool to define semantics of logic programming. In this work, we will explore the possibility to use another fuzzy logic for knowledge representation. In particular, we show that Łukasiewicz 3-valued logic (for short, Ł3) can be used for knowledge representation based on logic programming. Firstly, we prove that the definition of stable model for Ł3 is equivalent to the obtained through G3 for augmented programs, but when we consider more general programs we obtain more answers for stable models on Ł3 than G3. Finally, we present and explore a new definition of stable model based on Lukasiewicz n-valued logic via the use of Monteiro-Baaz ∆ operator.

A 4-Valued Logic that Extends the Paraconsistent Logic G’3

We introduce a new 4-valued logic that we call M4M4. We show that M4M4 is conservative extensión of the 3-valued logic G′ 3, which serves as the formalism to define the p-stable semantics of logic programming. M4M4 possesses two negation operators. The weak negation operator that corresponds to the negation operator of G′ 3. In addition, M4M4 also includes a strong negation operator that is the new feature of this logic with respect to G′ 3. It is well known that allowing these two negations is very useful in knowledge representation. M4M4 can be used as the formalism to define the p-stable semantics as well as the stable semantics. We also present other suitable properties of M4M4.

Ternary SRAM circuit designs with CNTFETs

SummaryStatic random‐access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect.

Modelling of AGM-style doxastic operations in three-valued setting

The goal of our work is to show how a theoretical approach to modeling of reasoning can be analyzed to identify controversial issues that reveal prospects for further research. We will consider one of the basic approaches to modeling of reasoning based on the concept of belief revision AGM, which is viewed as classical because it formulates the basic concepts of belief, introduces the main ways of representing beliefs, cognitive actions, systems of postulates for cognitive actions and the basic principles for constructing epistemic systems. However, this conceptual foundation raises many controversial issues that require further research, such as the problem of purity of the doxastic operations, the problem of primacy of the doxastic operations and the problem of connection between the doxastic operations. To find a possible solution to these controversial points, we will attempt to model the main ideas of AGM within the framework of standard consistent, and complete logic \L{}3. The basic principle of our translation is the scheme for constructing an epistemic theory proposed by G\"ardenfors, which is considered the basis of AGM. We use a strict three-valued logic formalism to constrain the functioning of doxastic operators and to test how they will function when trying to express the corresponding AGM postulates in a given system. It will allow us to approach the solution of the classical AGM problems or at least to present them from a different perspective. We consider the fundamental possibility of obtaining other doxastic operators in this way and also show how we can implement the minimality criterion for the contraction operator by combining several theorems of three-valued logic. The presented method of translating an informal conceptual scheme into formal logic is convenient for teaching students the basics of modeling and makes it possible to demonstrate the relationships and limitations of the modeled objects and processes.

The Value Evolution of Labor Education in the Perspective of "Three Guarantees and Five Educations"

"Three Guarantees and Five Educations" means "All staff, All process and All aspects of Education and Simultaneous Development of Five Educations". Based on the research perspective of "Three Guarantees and Five Educations", this paper explores the value evolution of labor education in the past hundred years from the perspective of the generation logic, change process, evolution characteristics, original return, and creation path of labor education value, in order to deeply understand the development impact of labor education, enhance the value identification of labor education, promote the healthy development of students' physical and mental quality, improve students' innovative spirit and practical ability, and promote the development of labor education practice. Theoretical analysis shows that the value implication of labor education in different historical periods is also of great significance for correctly guiding students to understand and form correct labor education concepts, promoting their mastery of labor technology knowledge and skills, and empowering career development.

Demonstration of p-type stack-channel ternary logic device using scalable DNTT patterning process

A p-type ternary logic device with a stack-channel structure is demonstrated using an organic p-type semiconductor, dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene (DNTT). A photolithography-based patterning process is developed to fabricate scaled electronic devices with complex organic semiconductor channel structures. Two layers of thin DNTT with a separation layer are fabricated via the low-temperature deposition process, and for the first time, p-type ternary logic switching characteristics exhibiting zero differential conductance in the intermediate current state are demonstrated. The stability of the DNTT stack-channel ternary logic switch device is confirmed by implementing a resistive-load ternary logic inverter circuit.