A Power Efficient 32 nm Ternary Multiplier using Graphene Nanoribbon Field-Effect Transistor Technology

Abstract

As circuit complexity grows, designers are exploring ternary logic as an alternative to binary logic to solve interconnection and energy problems. One effective approach to implementing ternary logic-based circuits is to use a multiple-threshold voltage (multi-V th ) design. In particular, graphene nanoribbon (GNR)-based field-effect transistors (GNRFETs) are a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology for sub-32 nm feature sizes, as GNRs have excellent properties that can overcome scaling issues in CMOS. This paper introduces a ternary multiplier implemented with 32 nm GNRFET technology, which demonstrates high efficiency with only 26 transistors. Simulation results show that the proposed multiplier improves power dissipation and product-delay-power (PDP) by at least 37.30% and 22.22%, respectively, compared to existing multiplier designs when run at 0.9 V. Moreover, our proposed design is implemented with a carbon nanotube-based FET (CNTFET) technology. The GNRFET-based multiplier improved power and PDP by 41.77% and 30%, respectively in the cost of increasing the delay by 25%, compared to its CNTFET-based equivalent. Finally, we analyze the proposed multiplier under the process and environmental parameters variations of GNRFET technology. Overall, our results demonstrate the advantages of using GNRFET technology for implementing ternary logic-based circuits and provide insight into the impact of different design choices on performance.