Ternary Gates Research Articles

Design of ternary reversible Feynman and Toffoli gates in ternary quantum-dot cellular automata

The use of reversible logic gates leads to a reduction in energy loss in logic circuits by preventing information loss. New computing methods, such as quantum-dot cellular automata (QCA), have been offered by nanotechnology emerging with nanoelectronics to make more comprehensive logic circuits. In nanotechnology-based systems, some bits are erased when the system performs any computation, and this causes heat dissipation and energy loss in systems. Adder circuits are the basis of any arithmetic operation and one of the main parts of many circuits for creating complex hardware; therefore, the use of enhanced adder circuits leads to high performance in logic circuits. In irreversible logic, the energy that is transferred from the power supply to the circuit is converted into heat, and energy loss occurs. Power management plays a vital role in modern computational systems, and using ternary logic instead of previous technologies leads to better performance. The main purpose of our study is to design ternary quantum-dot cellular automata (TQCA) reversible logic gates based on ternary quantum-dot cellular technology. Reversible gates are the basis of creating a reversible circuit. In this paper, the Muthukrishnan-Stroud (M-S) gate, which is the basis of all other reversible ternary gates, is implemented in ternary QCA technology, and then, reversible ternary Feynman and Toffoli (C2NOT) gates are designed. More optimal adder circuits can be realized in three-valued technology using Feynman and Toffoli gates. The area, delay, and cell count of the proposed TQCA designs are compared with those of other related works, and the effect of fault on the designs in the presence of cell omission defect is determined. The occupied areas of the proposed Feynman and Toffoli gate designs are 0.069 μm2 and 0.073 μm2, respectively. Moreover, the fault tolerance levels of these TQCA gates are 77% and 92%, respectively.

Improved homomorphic evaluation for hash function based on TFHE

Homomorphic evaluation of hash functions offers a solution to the challenge of data integrity authentication in the context of homomorphic encryption. The earliest attempt to achieve homomorphic evaluation of SHA-256 hash function was proposed by Mella and Susella (in: Cryptography and coding—14th IMA international conference, IMACC 2013. Lecture notes in computer science, vol 8308. Springer, Heidelberg, pp 28–44, 2013. https://doi.org/10.1007/978-3-642-45239-0_3.) based on the BGV scheme. Unfortunately, their implementation faced significant limitations due to the exceedingly high multiplicative depth, rendering it impractical. Recently, a homomorphic implementation of SHA-256 based on the TFHE scheme (Homomorphic evaluation of SHA-256. https://github.com/zama-ai/tfhe-rs/tree/main/tfhe/examples/sha256_bool) brings it from theory to reality, however, its current efficiency remains insufficient. In this paper, we revisit the homomorphic evaluation of the SHA-256 hash function in the context of TFHE, further reducing the reliance on gate bootstrapping and enhancing evaluation latency. Specifically, we primarily utilize ternary gates to reduce the number of gate bootstrappings required for logic functions in message expansion and addition of modulo 232\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$2^{32}$$\\end{document} in iterative compression. Furthermore, we demonstrate that our optimization techniques are applicable to the Chinese commercial cryptographic hash SM3. Finally, we give specific comparative implementations based on the TFHE-rs library. Experiments demonstrate that our optimization techniques lead to an improvement of approximately 35–50% compared with the state-of-the-art result under different cores.

Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder

Designing conventional circuits present many challenges, including minimizing internal power dissipation. An approach to overcoming this problem is utilizing quantum technology, which has attracted significant attention as an alternative to Nanoscale CMOS technology. The reduction of energy dissipation makes quantum circuits an up-and-coming emerging technology. Ternary logic can potentially diminish the quantum circuit width, which is currently a limitation in quantum technologies. Using qutrit instead of qubit could play an essential role in the future of quantum computing. First, we propose two approaches for quantum ternary decoder circuit in this context. Then, we propose a quantum ternary multiplexer and quantum ternary demultiplexer to exploit the constructed quantum ternary decoder circuit. Techniques to achieve lower quantum cost are of importance. We considered two types of circuits, one in which the output states are always restored to the initial input states and the other in which the states of the output are irrelevant. We compare the proposed quantum ternary circuits with their existing counterparts and present the improvements. It is possible to realize the proposed designs using macro-level ternary gates that are based on the ion-trap realizable ternary 2-qutrit Muthukrishnan–Stroud and 1-qutrit permutation gates.

Performance Comparison of CMOS and NMOS GNRFET Full Adder

Transistor makes up the cornerstone of modern computing. In this work, a SPICE model of GNRFET was used to simulate the performance of a NMOS and CMOS binary full adder. The performance of this adder was evaluated in terms of its average power consumption and propagation delay. Three variables, namely the resistance value, dimer lines and channel length were manipulated and the impact on its performance was assessed. It was observed that a linear improvement in propagation delay was accompanied by an exponential increase in power consumption and only a small range of values of resistance was able to deliver a relatively reasonable trade-off between power consumption and propagation delay. These values range from approximately 110 kΩ to 130 kΩ. When the dimer lines were varied from 12 to 8 and channel length was varied from 32 nm to 16 nm, the results showed that a channel length of 16 nm was superior to that of a channel length of 32 nm as it showed 25.25 % of improvement in propagation delay at approximately similar power consumption. On the other hand, the choice of dimer lines and circuit architecture was required to be evaluated on a case-by-case basis. For a compute-intensive application with a controlled environment, NMOS logic with 8 dimer lines should be chosen, while for less compute-intensive applications and portable devices, CMOS logic with 12 dimer lines should be utilised. A NMOS logic was chosen for the former due to a reasonable trade-off of 30.94 % of power consumption for a 35.03 % of propagation delay was established When the performance of these full adders are compared to that of a MTGB based ternary gate in terms of their performance, it was found that the CMOS and NMOS logic full adder performed better than a MTGB based ternary full adder.

Symmetric ternary quantum Fourier transform and its application

The research of ternary quantum system has gradually come into the attention of scholars in recent years. In $2018$, Guangcan Guo and his colleagues showed that in a qutrit-qutrit system they can observe quantum nonlocality and quantum contextuality at the same time. In $2019$, international cooperation team led by Anton Zelinger of Austrian Academy of Sciences and Jianwei Pan of University of science and technology of China, they have succeeded in teleporting complex high-dimensional quantum states. The work of the above scholars makes us clearly realize the importance of the study of ternary quantum system, but there is a few research results on this aspect. Furthermore, the quantum Fourier transform (QFT) offers an interesting way to perform arithmetic operations on a quantum computer. So, the paper extends the QFT to symmetric ternary quantum system and gives its applications. First, a set of quantum gates is defined for symmetric ternary quantum system. It is worth noting that in binary system, qubit flipping is realized by Not gate. Therefore, we need to extend Not gate to symmetric ternary system to realize qutrit flipping, which is called M-S gate. And then, by decomposing single-qutrit unitary gate in symmetric ternary quantum system, the universal gates are given. It means that any unitary operation on $n$ qutrits can be accurately implemented by single-qutrit symmetric ternary quantum gates and two-qutrit symmetric ternary M-S gates. By extending the QFT to the symmetric ternary quantum system, the paper successfully use some symmetric ternary quantum gates to construct the circuit which can realize symmetric ternary quantum Fourier transform (STQFT). Finally, the circuit of adder in symmetric ternary quantum system are designed based on the STQFT and the universal quantum gates. ternary quantum Fourier transform and its application (pp733-754) Hao Dong, Dayong Lu, and Xiaoyun Sun doi: https://doi.org/10.26421/QIC22.9-10-2 Abstracts: The research of ternary quantum system has gradually come into the attention of scholars in recent years. In $2018$, Guangcan Guo and his colleagues showed that in a qutrit-qutrit system they can observe quantum nonlocality and quantum contextuality at the same time. In $2019$, international cooperation team led by Anton Zelinger of Austrian Academy of Sciences and Jianwei Pan of University of science and technology of China, they have succeeded in teleporting complex high-dimensional quantum states. The work of the above scholars makes us clearly realize the importance of the study of ternary quantum system, but there is a few research results on this aspect. Furthermore, the quantum Fourier transform (QFT) offers an interesting way to perform arithmetic operations on a quantum computer. So, the paper extends the QFT to symmetric ternary quantum system and gives its applications. First, a set of quantum gates is defined for symmetric ternary quantum system. It is worth noting that in binary system, qubit flipping is realized by Not gate. Therefore, we need to extend Not gate to symmetric ternary system to realize qutrit flipping, which is called M-S gate. And then, by decomposing single-qutrit unitary gate in symmetric ternary quantum system, the universal gates are given. It means that any unitary operation on $n$ qutrits can be accurately implemented by single-qutrit symmetric ternary quantum gates and two-qutrit symmetric ternary M-S gates. By extending the QFT to the symmetric ternary quantum system, the paper successfully use some symmetric ternary quantum gates to construct the circuit which can realize symmetric ternary quantum Fourier transform (STQFT). Finally, the circuit of adder in symmetric ternary quantum system are designed based on the STQFT and the universal quantum gates.

Design of New Ternary Inverter Gate Based on the Nanowire Transistor

Design of New Ternary Inverter Gate Based on the Nanowire Transistor

Ternary Logic with Stateful Neural Networks Using a Bilayered TaOX -Based Memristor Exhibiting Ternary States.

A memristive stateful neural network allowing complete Boolean in‐memory computing attracts high interest in future electronics. Various Boolean logic gates and functions demonstrated so far confirm their practical potential as an emerging computing device. However, spatio‐temporal efficiency of the stateful logic is still too limited to replace conventional computing technologies. This study proposes a ternary‐state memristor device (simply a ternary memristor) for application to ternary stateful logic. The ternary‐state implementable memristor device is developed with bilayered tantalum oxide by precisely controlling the oxygen content in each oxide layer. The device can operate 157 ternary logic gates in one operational clock, which allows an experimental demonstration of a functionally complete three‐valued Łukasiewicz logic system. An optimized logic cascading strategy with possible ternary gates is ≈20% more efficient than conventional binary stateful logic, suggesting it can be beneficial for higher performance in‐memory computing.

Polyadic Braid Operators and Higher Braiding Gates

A new kind of quantum gates, higher braiding gates, as matrix solutions of the polyadic braid equations (different from the generalized Yang–Baxter equations) is introduced. Such gates lead to another special multiqubit entanglement that can speed up key distribution and accelerate algorithms. Ternary braiding gates acting on three qubit states are studied in detail. We also consider exotic non-invertible gates, which can be related with qubit loss, and define partial identities (which can be orthogonal), partial unitarity, and partially bounded operators (which can be non-invertible). We define two classes of matrices, star and circle ones, such that the magic matrices (connected with the Cartan decomposition) belong to the star class. The general algebraic structure of the introduced classes is described in terms of semigroups, ternary and 5-ary groups and modules. The higher braid group and its representation by the higher braid operators are given. Finally, we show, that for each multiqubit state, there exist higher braiding gates that are not entangling, and the concrete conditions to be non-entangling are given for the obtained binary and ternary gates.

Novel low-complexity and energy-efficient fuzzy min and max circuits in nanoelectronics

Ultra-efficient fundamental fuzzy Min and Max circuits are proposed in this paper using 3 CNTFETs. These are much energy-efficient compared to the state-of-the-art previous designs of Min and Max circuits, which are vastly superior to other models. This is due to the lack of a direct current path (between the inputs and GND /VDD) and the low output resistance. The superiority of the proposed Min and Max Circuits are technically described and proved. At the next step, an applied circuit, the ternary half-adder is developed based on the proposed Min and Max circuits. In these suggestions, all parts of half-adder, successor, and predecessor circuits are introduced based on ternary gates. The simulation results, as obtained through extensive simulations using Synopsys HSPICE and the 32 nm Stanford comprehensive CNTFET model, demonstrate that proposed Min and Max circuits are 22 times (%95.5) and 38 times (%97.39) more energy-efficient with a 0.5fF load compared to the best previous work, respectively. Furthermore, the proposed half-adder is %39 more energy-efficient with a 0.5fF load, compared to the previous work.

Ultra-Compact Ternary Logic Gates Based on Negative Capacitance Carbon Nanotube FETs

Ternary logic has been studied for several decades as it can offer significant advantages to reduce the number of interconnects and the complexity of operations. However, the excessive transistor count of the existing ternary logic gates can diminish these advantages in practice. In this brief, based on the negative capacitance (NC) feature of the ferroelectric materials and the well-proven electronic properties of the carbon nanotube field-effect transistor (CNTFET), we have proposed ultra-compact ternary logic gates. After developing a NC-CNTFET model, we have designed a 2-transistor ternary inverter, a 4-transistor ternary NAND, and a 4-transistor ternary NOR with the structures and transistor counts similar to the binary complementary metal-oxide-semiconductor (CMOS) logic. The simulation results ascertain the correct and robust functionality of the proposed ternary gates, even in the presence of process variations. Our proposed ternary inverter, NAND, and NOR gates lead to on average 65%, 60%, and 60% improvements in transistor count, 79%, 83%, and 77% improvements in the area, and 34%, 61%, and 54% improvements in energy-delay product (EDP) as compared to the previous state-of-the-art ternary gates. Our approach accentuates that the proposed ternary gates are the potential candidates for demonstrating more complex multi-valued arithmetic-logic units.

Carbon Nanotube and Resistive Random Access Memory Based Unbalanced Ternary Logic Gates and Basic Arithmetic Circuits

In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed. Ternary logic has emerged as a very promising alternative to the existing binary logic systems owing to its energy efficiency, operating speed, information density and reduced circuit overheads such as interconnects and chip area. The proposed design employs active load RRAM and CNTFET instead of large resistors to implement ternary logic gates. The proposed ternary logic gates are then utilised to carry out basic arithmetic functions and is extendable to implement additional complex functions. The proposed ternary gates show significant advantages in terms of component count, chip area, power consumption, energy consumption and dense fabrication. The results demonstrate the advantage of the proposed models with a reduction of 50% in transistor count for the STI, TNAND and TNOR logic gates. For THA and THS arithmetic modules 65.11% reduction in transistor count is observed while for TM design, around 38% reduction is observed. In this work, we aim to demonstrate the viability of RRAM in the design of ternary logic systems, thus the focus is mainly on obtaining the proper functionality of the proposed design. Also the proposed logic gates show a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency. For simulations, HSPICE tool is used to verify the authenticity of the proposed designs. The ternary half adder, ternary half subtractor and ternary multiplier circuits are then implemented utilising the proposed gates and validated through simulations.

Comments on “High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits”

In the above article [1] , R. A. Jaber et al. present the designs of ternary logic circuits based on CNTFET technology. The motivation for designing ternary gates is based on the following assumption quoted in the abstract: “Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption.”

Novel Ternary Logic Gates Design in Nanoelectronics

In this paper, standard ternary logic gates are initially designed to considerably reduce static power consumption. This study proposes novel ternary gates based on two supply voltages in which the direct current is eliminated and the leakage current is reduced considerably. In addition, ST-OR and ST-AND are generated directly instead of ST-NAND and ST-NOR. The proposed gates have a high noise margin near V_(DD)/4. The simulation results indicated that the power consumption and PDP underwent a~sharp decrease and noise margin showed a considerable increase in comparison to both one supply and two supply based designs in previous works. PDP is improved in the proposed OR, as compared to one supply and two supply based previous works about 83% and 63%, respectively. Also, a memory cell is designed using the proposed STI logic gate, which has a considerably lower static power to store logic ‘1’ and the static noise margin, as compared to other designs.

Quantum Ternary Multiplication Gate (QTMG): Toward Quantum Ternary Multiplier and a New Realization for Ternary Toffoli Gate

The designs using ternary logic exploit its logarithmic reduction in the number of qudits compared with the binary circuits. In this paper, we propose quantum ternary multiplication gate. We term it as QTMG. Then we present the symbol and the realization of QTMG. Researchers will be able to use this gate as well as its symbol and realizations in their future studies. We also present a new realization of ternary Toffoli gate in specific state. Moreover, in this paper, we propose 1-qutrit multiplier circuit. The symbol and the realization of the proposed 1-qutrit multiplier circuit are also provided. Afterward, we proposed ternary partial products generation circuit (TPPG) and summation network circuit in order to design quantum ternary 2-qutrit multiplier circuit. Overall, the proposed design of QTMG in this paper is suggested for the first time. In addition, the proposed realization of ternary Toffoli gate, TPPG, summation network and 2-qutrit multiplier circuits are compared with the existing designs and the improvements are reported. The proposed gate and circuits are realized using macro-level ternary gates which are built on the top of the ion-trap realizable 1-qutrit gates and 2-qutrit Muthukrishnan–Stroud gates.

A Ternary Decision Diagram (TDD)-Based Synthesis Approach for Ternary Logic Circuits

Ternary reversible logic synthesis has started gaining the attention of researchers in recent years because of its distinct advantages over binary reversible logic synthesis. However, the existing methods for the synthesis of ternary reversible logic circuits are applicable only to smaller benchmarks. The present paper proposes an efficient synthesis approach in this regard using ternary decision diagrams (TDDs). A TDD is first generated for the function that is to be synthesized. Then, using a gate library of ternary reversible gates, each TDD node is mapped to a sequence of ternary reversible gates that are finally merged together to form the required netlist. The ternary gate library consists of ternary reversible gates such as multi-polarity ternary Feynman gate and multi-polarity ternary Toffoli gate. To estimate the quantum cost, we propose a decomposition approach to represent a ternary reversible gate in terms of ternary elementary gates. We have carried out experimental evaluation on two types of benchmarks. The first type consists of binary reversible benchmarks converted into ternary reversible benchmarks using a transformation approach. The second type is based on ternary non-reversible benchmarks. We have reported the results for benchmarks with up to 13 inputs with a longest runtime of 7 min, which compares favourably with the existing works in the literature.

High-Performance and Energy-Efficient CNFET-Based Designs for Ternary Logic Circuits

Recently, the demand for portable electronics and embedded systems has increased. These devices need low-power circuit designs because they depend on batteries as an energy resource. Moreover, multi-valued logic (MVL) circuits provide notable improvements over binary circuits in terms of interconnect complexity, chip area, propagation delay, and energy consumption. Therefore, this paper proposes new ternary circuits aiming to lower the power delay product (PDP) to save battery consumption. The proposed designs include new ternary gates [standard ternary inverter (STI) and ternary NAND (TNAND)] and combinational circuits [ternary decoder (TDecoder), ternary half-adder (THA), and ternary multiplier (TMUL)] using carbon nano-tube field-effect transistors (CNFETs). This paper employs the best trade-off between reducing the number of used transistors, utilizing energy-efficient transistor arrangement such as transmission gate, and applying the dual supply voltages (V dd and V dd /2). The five proposed designs are compared with the latest 15 ternary circuits using the HSPICE simulator for different supply voltages, different temperatures, and different frequencies; 180 simulations are performed to prove the efficiency of the proposed designs. The results show the advantage of the proposed designs in reduction over 43% in terms of transistors' count for the ternary decoder and over 88%, 99%, 98%, 86%, and 78% in energy consumption (PDP) for the STI, TNAND, TDecoder, THA, and TMUL, respectively.

A versatile DNA-supramolecule logic platform for multifunctional information processing

DNA-based logic units are rapidly being developed in molecular computation. However, because DNA cannot produce detectable signals, suitable signal reporters must be carefully selected, which is challenging, especially in advanced, multifunctional devices. By introducing a supramolecular reporter MTC [3,3’-di(3-sulfopropyl)-4,5,4’,5’-dibenzo-9-methyl-thiacarbo-cyanine triethylammonium salt], we developed a simplified DNA-supramolecule platform. Owing to the multiple assembly states of MTC, the platform contains only one reporter block but can provide multiple parallel outputs and easily implement several types of information processing functions, including data filtration (binary and ternary INHIBIT gates), selection (multiplexer and demultiplexer) and verification (parity checker and comparator). In addition to combinational circuits, a fundamental sequential logic circuit, counter, has also been fabricated at the molecular level. With the advantages of high reconfigurability, flexibility and enormous parallelism, this DNA-supramolecule prototype may have a promising future in the field of molecular computing and multiplex chemical analysis.

A novel design of a ternary coded decimal adder/subtractor using reversible ternary gates

In recent years, an outstanding amount of interest has been given to reversible circuits. Their applications in distinctive fields that include digital circuit design with low-power consumption, computational circuit design in quantum computer and DNA-based computations are of high significance. Because of advantages of ternary circuits over binary circuits, such as reducing the complexity of interconnects, smaller chip area and reducing the number of quantum cells for the quantum circuit, ternary logic is suggested to construct new compact circuits. Also, in quantum technology, without any restrictions with the same physical phenomena that binary circuits are implemented, new circuits can be implemented in ternary logic. Circuit design for decimal calculations, which includes addition and subtraction of decimal numbers, has continually been the interest of digital circuit designers. In reversible ternary computation, the reversible circuits for decimal calculations have been less studied. In this paper, a reversible ternary adder/subtractor circuit for the addition/subtraction of decimal digits in radix three is proposed. Ternary Coded Decimal (TCD) codes are used to display decimal inputs and outputs. In circuit implementation, first by removing the unused inputs and outputs in the required ternary adders in the TCD Adder, three blocks of reversible 3-qutrit ternary adder with the quantum cost of 29, 22, 14 and constant inputs of 0, 1, and 0 were presented, then an optimal circuit for the TCD detector with a quantum cost of 16 was introduced. The proposed TCD detector has 23% improvement in quantum cost as compared to the existing design. By applying these in the design of the reversible TCD Adder, a more optimal reversible TCD Adder circuit than the existing design was presented resulting in a 31% improvement in quantum cost and 58% improvement in the number of constant inputs. Finally, decimal 9's complement circuit for the subtraction of two decimal numbers was proposed. In the proposed TCD Adder/Subtractor, the new proposed TCD Adder and decimal 9's complement circuits were used. To realize all proposed circuits, 1-qutrit shift gates and 2-qutrit Muthukrishnan-Stroud gates, which are realized in ion-trap technology in quantum computers, were used.

Implement and Analysis of a 1-Bit Ternary SRAM Cell Using Tanner Tools

Binary logic dominates present day digital systems. Today the complexity of binary systems is on the rise because of increasing number of gates per chip and more complex circuit schematics. To upkeep Moore’s law, gate count per chip is exponentially increasing leading to more complex circuits and greater number of interconnections, which cover almost 70 percent of chip area. More gates also increase power consumption and dissipation per chip. Under such circumstances, multivalued logic approach provides several advantages over existing binary digital system and research has concluded ternary system to be the most efficient in terms of logic computations. Using existing mathematical models of basic Ternary gates, the schematics is obtained for the same. In this paper the focus is on implementation of this Ternary inverter and application of the ternary inverter to design a 1-bit ternary Static Random-Access Memory (SRAM) cell having low power consumption on the basis of Simple, Positive and Negative Ternary Inverter.

Compact 2D threshold voltage modeling and performance analysis of ternary metal alloy work-function-engineered double-gate MOSFET

The present work aims to ameliorate the recently popular innovative gate engineering concept of continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction and realize a ternary metal alloy gate electrode. Based on this, a new ternary metal alloy (TMA) double-gate MOSFET has been proposed and a detailed two-dimensional analytical modeling has been presented to make an overall performance comparison of this proposed TMA double-gate MOSFET with that of its binary metal alloy gate counterpart in terms of surface potential, electric field, threshold voltage roll-off, drain-induced barrier lowering and current in order to establish the superiority of a ternary metal alloy gate electrode over its binary metal alloy equivalent. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.