Ternary Full Adder Research Articles

An efficient design of reversible ternary full-adder/full-subtractor with low quantum cost

One of the major challenges of VLSI circuits is heat caused by energy loss. One of the successful solutions to this challenge is to design circuits in a reversible manner. Hence, the design of reversible circuits has attracted the attention of many researchers in the fields of low-power circuits design, DNA computing and quantum computing. Due to the benefits of ternary logic over binary logic such as reducing the complexity of interconnecting circuits, decreasing the occupied surface and reducing the number of quantum cells in quantum circuits, the ternary logic has been proposed for the design of VLSI circuits. In this paper, we first propose a new reversible ternary full-adder, called comprehensive reversible ternary full-adder, using the ternary logic capabilities. In the following, an efficient reversible ternary full-subtractor is provided. Finally, using the two proposed circuits, a new reversible ternary full-adder/full-subtractor is introduced. The results of the comparisons show that the proposed circuits have lower quantum cost and are more efficient than the other previous circuits.

Design of low power multi-ternary digit multiplier in CNTFET technology

This work introduces the method to implement energy efficient designs of arithmetic units such as a ternary full adder, ripple carry adder, single-trit multiplier and multi-trit multiplier using carbon nanotube field effect transistors (CNTFETs). A CNTFET unique feature of the threshold voltage variation by changing the CNT diameter, make it a suitable alternative for being employed in ternary logic designs. In designing the proposed circuits, decoder circuit functionality is realized by various threshold detector circuits tuned to a specific logical threshold voltage value. The multiplier circuit is designed by combing the capacitive logic and the minority function. In order to test the practicability of proposed circuits in cascaded circuits, multi-digit adder and multiplier circuits are constructed. The proposed multi-digit multiplier structure is based on classical Wallace multiplier and includes various optimized versions of adder and multiplier circuits. Extensive simulation has been done to examine the competency of proposed designs under different test conditions. The design of 3-trit multiplier formed by combing the proposed adder and multiplier circuits shows 16 times reduction in power consumption as well as energy consumption in comparison to previous multiplier design.

Two novel inverter-based ternary full adder cells using CNFETs for energy-efficient applications

ABSTRACTCarbon nanotube field effect transistors (CNFETs) exhibit great promise and extensions to silicon MOSFET due to their excellent electronic properties and extremely small size. Implementable CNFET circuits have operational characteristics to approach the advantage of using multiple-valued logic (MVL) in voltage mode. In MVL implementation computation for the system will be faster than the binary system with improved density of digital circuits. This paper presents two novel 1-bit inverter-based ternary full adder cells which second design cell uses only 37 CNFET transistors in its structure. These designs have been proposed using a new definition of Majority-not based full adder, and are compared to the other adders based on power consumption, speed and power-delay product (PDP). Proposed designs are evaluated using simulation run on HSPICE with 32 nm CNFET standard technology under various operational conditions, including different supply voltages, output load variation and different operating temperatures. According to simulation results, all proposed ternary full adder designs in compare to the state of the art circuits in literature have been demonstrated up to 81% and 80%, respectively, improvement in power consumption and PDP.

High performance, variation-tolerant CNFET ternary full adder a process, voltage, and temperature variation-resilient design

Multiple-valued logic (MVL) decreases interconnection requirement and power consumption by realizing more data transmission over an interconnection wire. This paper investigates the carbon nanotube field effect transistors (CNFETs) using in the design of a ternary full adder cell. The proposed design takes advantage of the exceptional properties of CNFETs such as setting the desired threshold voltages by adjusting the carbon nanotubes (CNTs) diameters. We use Synopsys HSPICE simulator with a 32 nm Stanford CNFET model to simulate the ternary adders. We evaluate and examine the proposed design under different operational conditions such as different supply voltages (V), and different temperatures (T). Also, we investigate the designs under process variations (P) sensitivity. The simulation results show that the proposed design reduces the delay and energy consumption by up to 3.7X and 1.2X compared to the best state-of-the-art methods while being tolerant to process, voltage and temperature (PVT) variations.

Ternary Full Adder Using Multi-Threshold Voltage Graphene Barristors

Ternary logic circuit has been studied for several decades because it can provide simpler circuits and subsequently lower power consumption via succinct interconnects. We demonstrated a ternary full adder exhibiting a low power-delay-product of ~10−16 J, which is comparable to the binary equivalent circuit. The ternary full adder was modeled using device parameters extracted from the experimentally demonstrated multi-Vth ternary graphene barristors.

A Ternary Full Adder Cell Based on Carbon Nanotube FET for High-Speed Arithmetic Units

A Ternary Full Adder Cell Based on Carbon Nanotube FET for High-Speed Arithmetic Units

High Performance CNFET-based Ternary Full Adders

ABSTRACTThis paper investigates the use of carbon nanotube field effect transistors (CNFETs) for the design of ternary full adder cells. The proposed circuits have been designed based on the unique properties of CNFETs such as having desired threshold voltages by adjusting diameter of the CNFETs gate nanotubes. The proposed circuits are examined using HSPICE simulator with the standard 32 nm CNFET technology. The proposed methods are simulated at different conditions such as different supply voltages, different temperature, and operational frequencies. Simulation results show that the proposed designs are faster than the state of the art CNFET-based ternary full adders.

An Energy- and Area-Efficient Approximate Ternary Adder Based on CNTFET Switching Logic

Nowadays, portable multimedia devices have been widely used in low-power structures. Additionally, using approximate computing and multiple-valued logic (MVL) can lead to lower power consumption. Carbon nanotube field effect transistor (CNTFET), with a determinable threshold voltage, is an appropriate choice for designing MVL circuits. In this study, a new approximate ternary full adder is presented based on CNTFET switching logic with the aim of reducing area and energy consumption. The results obtained by the Synopsys HSPICE simulator with the Stanford 32 nm CNTFET technology show that the average power consumption, delay, and energy consumption of the proposed designs are significantly lower than the other conventional and state-of-the-art CNTFET-based ternary circuits. In addition, the proposed ternary full adder is applied to reduce the steps of a ternary multiplier structure and some important metrics such as normalized error distance and energy-error trade-off are calculated to evaluate the efficiency of the proposed circuits. The layout of the proposed design is also plotted to estimate area consumption. Moreover, the approximate design is used for image processing applications such as image multiplying and image blending and the results are accordingly compared with the exact outputs. Similarly, the evaluated peak signal-to-noise ratio and mean structural similarity index metric indicate that the proposed approximate full adder has a proper accuracy for image processing applications.

A Synthesis Methodology for Ternary Logic Circuits in Emerging Device Technologies

Automatic synthesis of digital circuits has played a key role in obtaining high-performance designs. While considerable work has been done in the past, emerging device technologies call for a need to re-examine the synthesis approaches, so that better circuits that harness the true power of these technologies can be developed. This paper presents a methodology for synthesis applicable to devices that support ternary logic. We present an algorithm for synthesis that combines a geometrical representation with unary operators of multivalued logic . The geometric representation facilitates scanning appropriately to obtain simple sum-of-products expressions in terms of unary operators. An implementation based on Python is described. The power of the approach lies in its applicability to a wide variety of circuits. The proposed approach leads to the savings of 26% and 22% in transistor-count, respectively, for a ternary full-adder and a ternary content-addressable memory (TCAM) over the best existing designs. Furthermore, the proposed approach requires, on an average, less than 10% of the number of the transistors in comparison with a recent decoder-based design for various ternary benchmark circuits. Extensive HSPICE simulation results show roughly 92% reduction in power-delay product (PDP) for a $12\times 12$ TCAM and 60% reduction in PDP for a 24-ternary digit barrel shifter over recent designs.

Low‐power consumption ternary full adder based on CNTFET

This paper presents low-power circuits to implement ternary full adder (TFA) using carbon nanotube field-effect transistors (CNTFETs). Besides the unique characteristics of the CNTs, the threshold voltage simple control is the best property to implement ternary logic circuits. Low-complexity, low-power consumption and low-power delay product (PDP) are the benefits of the proposed circuits in comparison with all previous presented designs of TFA. The final proposed TFA is robust and has proper noise margins. The structure of the final proposed TFA is more appropriate to use in ripple adders, since the first ternary half sum generators (THSGs) in all cells produce their outputs in parallel (in the final proposed TFA, the output of the first THSG of the sum-generation unit is also used in the carry-generation unit). The proposed circuits are simulated using HSPICE with 32 nm-CNTFET technology. According to simulation results, the final proposed TFA has reduced the power consumption significantly and results in 86.92 and 97% reductions in terms of the PDP in comparison with two recent proposed designs.

CNFET-based approximate ternary adders for energy-efficient image processing applications

Nowadays, low power design has attracted more attentions. This purpose is achieved through some techniques such as low-power design methods, multiple valued logic and more recently by approximate computing. Carbon nanotube field-effect transistor (CNFET) is an appropriate candidate device for low-power multiple valued logic applications. In approximate computing, reducing the precision of arithmetic blocks leads to reduction in power consumption. In this paper, two approximate CNFET-based ternary full adder cells are proposed. The proposed designs considerably reduce the design complexity and the number of transistors by utilizing the unique properties of CNFETs as well as the switching logic style. The simulation results demonstrate that the proposed approximate designs improve the delay, power and energy dissipation by about 90% as compared to their exact counterparts. Also, as the adder cells are commonly used in the reduction step of multiplier circuits, the efficiency of the proposed cells is investigated in the structure of ternary multipliers through the normalized error distance and power-error tradeoff metrics. Moreover, as the approximate circuits are used in image processing applications, an inexact ternary multiplier is utilized for pixel by pixel image multiplying and the results are compared with the exact ones. According to the simulation results, the proposed inexact methods enhance the performance of arithmetic circuits while maintaining the required accuracy for such applications.

Design of all optical ternary logic based half adder circuit and it’s applications

Ternary Half adder circuit with optical nonlinear material (OPNLM) based switch is proposed and discussed. The designing of Ternary incrementer / decrementer circuits and Ternary full adder circuit with the proposed Ternary half adder circuit are also described here. Polarized lights of different states are considered as the inputs of the logical operations.

A Novel Design of Ternary Full Adder Using CNTFETs

This paper proposes a novel design of pass transistor-based ternary full adder (TFA) cell using inherent binary nature (0, 1) of input carry in carbon nanotube field effect transistor (CNTFET) technology. A buffer circuit is added to get high performance without sacrificing the overall energy efficiency of the design. The use of pass transistor logic style leads to low power consumption. The proposed TFA is examined exhaustively, using Synopsys HSPICE simulator with 32 nm Stanford CNTFET model in various test conditions and at different supply voltages. The proposed design has high driving capability and is robust. At 0.9 V power supply, the proposed design shows 69 % reduction in power–delay product in comparison with its counterpart, recently published in the literature.

Design and Evaluation of an Efficient Carbon Nano-Tube Field Effect Transistor-Based Ternary Full Adder Cell for Nanotechnology

Design and Evaluation of an Efficient Carbon Nano-Tube Field Effect Transistor-Based Ternary Full Adder Cell for Nanotechnology

A Novel CNTFET-based Ternary Full Adder

The Full Adder is one of the most important and basic units of mathematic circuits that is the basic structure of many complex systems. Moreover, serial and serial-parallel mathematic processes can be carried out faster and more operative error-detection and error-correction codes can be employed in ternary logic implementations. In this work, we presented a new high-performance Ternary Full Adder (TFA) based on Carbon Nanotube Field-Effect Transistor (CNTFET) technology. The proposed design is well-matched with the Carbon Nanotube Field-effect Transistor knowledge and ternary logic value. The presented structure reduces the delay of the Ternary Full Adder and has high driving capability. The proposed Ternary Full Adder is simulated at varying supply voltages and temperatures using different frequencies by the Synopsys HSPICE circuit simulator. Simulation results determine improvement in terms of delay and Power-Delay Product (PDP) in comparison with the state-of-the-art designs. Simulations show that the proposed Ternary Full Adder cell shows approximately more than 53 % improvement in PDP compared to its counterparts.

Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics

This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFET-based ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.

Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics

Abstract This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFET-based ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-V th structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.

Quantum ternary parallel adder/subtractor with partially-look-ahead carry

Multiple-valued quantum circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum circuits. Binary parallel adder/subtractor is central to the ALU of a classical computer and its quantum counterpart is used in oracles - the most important part that is designed for quantum algorithms. Many NP-hard problems can be solved more efficiently in quantum using Grover algorithm and its modifications when an appropriate oracle is constructed. There is therefore a need to design standard logic blocks to be used in oracles - this is similar to designing standard building blocks for classical computers. In this paper, we propose quantum realization of a ternary full-adder using macro-level ternary Feynman and Toffoli gates built on the top of ion-trap realizable ternary 1-qutrit and Muthukrishnan-Stroud gates. Our realization has several advantages over the previously reported realization. Based on this realization of ternary full-adder we propose realization of a ternary parallel adder with partially-look-ahead carry. We also show the method of using the same circuit as a ternary parallel adder/subtractor.

Design and Implementation of a Low Power Ternary Full Adder

In this work, the design and implementation of a low power ternary full adder are presented in CMOS technology. In a ternary full adder design, the basic building blocks, the positive ternary inverter (PTI) and negative ternary inverter (NTI) are developed using a CMOS inverter and pass transistors. In designs of PTI and NTI, W/L ratios of transistors have been varied for their optimum performance. The ternary full adder and its building blocks have been simulated with SPICE 2G.6 using the MOSIS model parameters. The rise and fall times of PTI show an improvement by a factor of 14 and 4, respectively, and that of the NTI by a factor of nearly 4 and 17, respectively over that of earlier designs implemented in depletion-enhancement CMOS (DECMOS) technology. The noise margins improve by a factor of nearly 2 in PTI and NTI, respectively.The ternary full adder has been fabricated in MOSIS two micron n-well CMOS technology. The full adder and its building blocks, NTI and PTI have been tested experimentally for static and dynamic performance, compared with the SPICE simulated behavior, and close agreement is observed.The ternary-valued logic circuits designed in the present work which do not use depletion mode MOSFETS perform better than that implemented earlier in DECMOS technology. The present design is fully compatible with the current CMOS technology, uses fewer components and dissipates power in the microwatt range.

Performance of CMOS ternary full adder at liquid nitrogen temperature

We have designed, implemented and studied the performance at liquid nitrogen temperature (77 K) of a CMOS ternary full adder and its building blocks, the simple ternary inverter (STI), positive ternary inverter (PTI) and negative ternary inverter (NTI), and compared the corresponding performance at room temperature (300 K). The ternary full adder has been fabricated in 2 μm, n-well CMOS through MOSIS. In a ternary full adder, the basic building blocks, the PTI and NTI, have been developed using combinations of a CMOS inverter and transmission gate(s). There is close agreement between the simulated and measured voltage transfer characteristics and noise margins of ternary-valued devices. The measured transient times for the NTI, PTI and ternary full adder at 77 K show an improvement by a factor of ≈1.5–2.5 over the corresponding values at 300 K. The present design does not use linear resistors and depletion-mode MOSFETs to implement the ternary full adder and its building blocks, and is fully compatible with current CMOS technology.