Abstract
This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFET-based ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.
Highlights
Complementary Metal Oxide Semiconductor (CMOS) process has been the dominant technology, which provides the needed size scaling for implementing low-power, high-performance and high-density VLSI circuits and systems
The proposed circuits are designed based on the unique properties of CNFETs, such as the capability of Carbon Nanotube (CNT), to be configured to have the desired threshold voltages depending on their diameter, which is not feasible in CMOS technology
It is worth mentioning that the proposed method of designing ternary structures significantly reduces the number of the transistors of the ternary Full Adder cell and do not require any additional power supplies
Summary
Complementary Metal Oxide Semiconductor (CMOS) process has been the dominant technology, which provides the needed size scaling for implementing low-power, high-performance and high-density VLSI circuits and systems. The proposed circuits are designed based on the unique properties of CNFETs, such as the capability of CNTs, to be configured to have the desired threshold voltages depending on their diameter, which is not feasible in CMOS technology These novel designs have less complex structures and much less number of transistors, compared to the conventional ternary arithmetic circuits. The number of the CNTFETs of the proposed ternary Full Adder cell could be reduced by utilizing a direct ternary buffer [4], instead of two cascaded ternary inverters, as the threshold detector for generating the Sum signal As an another instance the state-of-the-art CNTFET-based ternary Full Adder cell, which can be considered as two cascaded CNTFET-based ternary Half Adders [6] is composed of 190 CNTFETs and requires an extra voltage supply
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