Ternary Circuits Research Articles

Displacement analysis in three configurations of Si0.5Ge0.5/Si junctionless gate-all-around FET: a study from device to binary and ternary circuit applications

Displacement analysis in three configurations of Si0.5Ge0.5/Si junctionless gate-all-around FET: a study from device to binary and ternary circuit applications

Qutrit representation of quantum images: new quantum ternary circuit design

Quantum computation is growing in significance and proving to be a powerful tool in meeting the high real-time computational demands of classical digital image processing. However, extensive research has been done on quantum image processing, mainly rooted in binary quantum systems. In this paper, we propose a new quantum ternary image circuit based on the analysis of the existing qutrit representation of quantum images. The proposed design utilizes ternary shift gates and ternary Muthukrishnan–Stroud gates, with the belief that this circuit can be used for ternary quantum image processing. This study makes a significant improvement compared to the existing counterpart in terms of quantum cost, the number of constant inputs, and garbage outputs, which are all essential parameters in quantum circuit design.

CNTFET-based digital arithmetic circuit designs in ternary logic with improved performance

Ternary logics are more desirable than the binary logic because it offers high speed operations and large density of information in digital logic systems. The carbon nanotube field-effect transistors (CNTFETs) are considered as better option for designing the ternary circuits because it provides the multiple threshold voltages by changing nanotube diameter. The complex arithmetic schematics such as adders and multipliers are important circuits in many VLSI applications. The ternary half-adder (THA) and multiplier (TMUL) designed using the Stanford 32 nm CNTFET are proposed in this study. The proposed THA and TMUL uses 41 and 33 CNTFETs and that resulting in a 54.44 % and 45 % reduction in transistor count, which plays major role for delay and power optimization. As a result, the proposed THA shows 37.01 %, 14.07 %, and 45.87 % improvement in delay, power, and energy, whereas TMUL shows 30.48 %, 6.64 %, and 36.74 % improvement in delay, power and energy, respectively, compared to existing circuits. The proposed THA and TMUL are developed using HSPICE with 0.9 V as a supply voltage.

Ternary encoder and decoder designs in RRAM and CNTFET technologies

A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied.

2D van der Waals Vertical Heterojunction Transistors for Ternary Neural Networks.

Compared with binary systems, ternary computing systems can utilize fewer devices to realize the same information density. However, most ternary computing systems based on binary CMOS circuits require additional devices to bridge binary processing and ternary computing. Exploring new device architectures for direct ternary processing and computing becomes the key to promoting ternary computing systems. Here, we demonstrated a 2D van der Waals vertical heterojunction transistor (V-HTR) with three flat conductance states, which can be the basic cell in ternary circuits to perform ternary processing and computing, without additional devices. A ternary neural network (TNN) and a ternary inverter were demonstrated based on the V-HTRs. The TNN can eliminate fuzzy data and output only clear data by building a ternary quantization function. By demonstrating both ternary logic and a TNN on the same device architecture, the 2D V-HTR shows potential as a basic hardware unit for future ternary computing systems.

Ternary combinational logic gate design based on tri-valued memristors

Traditional binary combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and complicated wiring. In contrast to the binary logic circuit design in this method, ternary combinational logic circuit implementation is more complicated. In this paper, a ternary circuit design method that does not require cascading basic ternary logic gates is proposed based on a tri-valued memristor, which can directly realize specific logic functions through a series connection of memristors. The ternary encoder, ternary decoder, ternary comparator, and ternary data selector are implemented by this method, and the effectiveness of the circuits is verified by LTspice simulations.

Design of ternary full-adder and full-subtractor using pseudo NCNTFETs

Now-a-days, the binary logic system has intensified by scaling the field effect transistor (FET). However, due to the effectiveness of scaling the FET, ternary logics became more popular. Out of numerous ternary logic devices, carbon nanotube (CNT) FET (CNTFET) is considered a good candidate over silicon FETs. Hence, in this study, ternary schematics are developed based on Pseudo N-type CNTFETs. The ternary basic designs such as standard ternary inverter (STI), AND and OR gates are presented. Then, using the proposed basic logic gates, the complex designs such as full adder and full subtractor are also proposed. The HSPICE simulator is utilized to design proposed circuits and analyze different performance parameters. The performance such as delay, power and power delay product (PDP) are analyzed for the proposed circuits. Moreover, the proposed schematics performances are also compared to complementary schematics. It investigated that Pseudo N-type CNTFET schematics improved the overall performance on an average up to 65.82% over the complementary ternary circuits.

High-performance ternary designs using graphene nanoribbon transistors

Considering the issues emerging because of shrinking silicon field effect transistors (FETs), various post-silicon, post-binary logics are investigated by the researchers. The design of ternary schematics utilizing graphene nanoribbon FET (GNRFET) circuits is one alternate option. Since different threshold voltages are obtained by employing GNRFETs by varying its physical dimension, GNRFET is an ideal option for designing ternary circuits. The ternary circuit designs such as adder, subtractor and multiplier using GNRFETs are proposed in this study. These designs are developed using the ternary based decoder circuit. The proposed circuits are developed and executed in Synopsys based HSPICE simulator for functional verification. Additionally, the performances such as delay, power, power-delay-product (PDP) and energy-delay-product (EDP) of the proposed circuits are investigated and compared to CNTFET based ternary designs. The GNRFET ternary designs improved the performance on an average up to 30.96% than the CNTFET based designs.

Simultaneous Switching Noise Effects in Graphene-Based Power Distribution Networks

The simultaneous switching noise (SSN) effects in graphene nanoribbon field effect transistor (GNRFET) based ternary circuits are presented in this study. The performance in terms of SSN induced peak noise and propagation delay on power and ground rails are investigated in multilayer graphene nanoribbon (MLGNR) bundled power interconnects using Hewlett simulation program with integrated circuit emphasis (HSPICE) simulator. Furthermore, these investigations are compared to the copper (Cu) and multiwalled carbon nanotubes (MWCNT) based power interconnects. From the results, it is noticed that the proposed MLGNR interconnects shows performance improvements up to 74.9% and 33.8% over the Cu and MWCNT interconnects. Moreover, the SSN peak noise and delay are investigated for different interconnect lengths from 200 μm to 500 μm. It is observed that the SSN noise on power and ground rail is reduced and propagation delay is increased as interconnect length is increased.

Novel qutrit circuit design for multiplexer, De-multiplexer, and decoder

Designing conventional circuits present many challenges, including minimizing internal power dissipation. An approach to overcoming this problem is utilizing quantum technology, which has attracted significant attention as an alternative to Nanoscale CMOS technology. The reduction of energy dissipation makes quantum circuits an up-and-coming emerging technology. Ternary logic can potentially diminish the quantum circuit width, which is currently a limitation in quantum technologies. Using qutrit instead of qubit could play an essential role in the future of quantum computing. First, we propose two approaches for quantum ternary decoder circuit in this context. Then, we propose a quantum ternary multiplexer and quantum ternary demultiplexer to exploit the constructed quantum ternary decoder circuit. Techniques to achieve lower quantum cost are of importance. We considered two types of circuits, one in which the output states are always restored to the initial input states and the other in which the states of the output are irrelevant. We compare the proposed quantum ternary circuits with their existing counterparts and present the improvements. It is possible to realize the proposed designs using macro-level ternary gates that are based on the ion-trap realizable ternary 2-qutrit Muthukrishnan–Stroud and 1-qutrit permutation gates.

Dual-channel P-type ternary DNTT–graphene barristor

P-type ternary switch devices are crucial elements for the practical implementation of complementary ternary circuits. This report demonstrates a p-type ternary device showing three distinct electrical output states with controllable threshold voltage values using a dual-channel dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]-thiophene–graphene barristor structure. To obtain transfer characteristics with distinctively separated ternary states, novel structures called contact-resistive and contact-doping layers were developed. The feasibility of a complementary standard ternary inverter design around 1 V was demonstrated using the experimentally calibrated ternary device model.

Energy Efficient Tri-State CNFET Ternary Logic Gates

Power consumption and especially leakage power are the main concerns of nano MOSFET technology. On the other hand, binary circuits face a huge number of interconnection wires, which results in power dissipation and area. Researchers introduced emerging nanodevices and multiple-valued logic (MVL) as two feasible solutions to overcome the challenges mentioned above. Carbon nanotube field-effect transistor (CNFET) is one of the emerging technologies that has some unique properties and advantages over MOSFET, such as adjusting the carbon nanotube (CNT) diameters to have the desired threshold voltage and have the same mobility as P-FET and N-FET transistors. In this paper, we present a novel method for designing ternary logic circuits based on CNFETs. Each of our designed logic circuits implements a logic function and its complementary via a control signal. Also, these circuits have a high impedance state, which saves power while the circuits are not in use. Moreover, we designed a two-digit adder/ subtractor and a power-efficient ternary logic arithmetic logic unit (ALU) based on the proposed gates. The proposed ternary circuits are simulated using HSPICE via standard 32 nm CNFET technology. The simulation results indicate the designs’ correct operation under different process, voltage, and temperature (PVT) variations. Also, simulation results show that the two-digit adder/ subtractor using our proposed gates has 12X and 5X lower power consumption and power-delay product (PDP), respectively, compared to previous designs.

Circuit-Level Exploration of Ternary Logic Using Memristors and MOSFETs

In recent decades, the performance of binary computers has escalated through transistor scaling. However, due to the impotent forecasts of transistor scaling, ternary systems are regaining attention. Among many ternary device candidates, a passive device called memristor that is based on resistance switching is considered a good candidate when integrated with MOSFETs. Therefore, in this paper, we design various terna-ry logic based on memristors and MOSFETs from primitive logic to sequential logic and perform a thorough diagnosis for circuit design. We highlight design issues that should be resolved (e.g., signal distortion and high static current) and present practical solutions such as “Strength Design.” Then, we report a proper design methodology of sequential circuits considering the spike phenomena of memristor-based gates. We present 16 novel ternary logic cells and circuitry, including the design of the first balanced ternary full-adder (TFA) and memristor-based ternary pulsed-latch (MTPL). By our TFA, we emphasize that it is possible to design the most practical ternary circuits using memristors and MOSFETs. Our TFA uses 97 transistors and 87 memristors, which is the most reasonable TFA design that has the highest potential to be implemented in the near future. Besides, the proposed MTPL uses 16 transistors and 10 memristors, and it occupies only 72.7% of the silicon area, compared to the master-slave ternary flip-flop.

Performance Evaluation of Scaled ZnO Stacked Nanosheet Channel Ternary Field Effect Transistor

Ternary logic device technologies have been actively researched due to the potential benefits such as lower power consumption, smaller device count, smaller area, and higher data processing density, compared to their binary counterparts. In this work, scaling prospect of ZnO stacked nanosheet channel ternary field effect transistor has been investigated. The benefits of scaling geometric parameters such as gate dielectric thickness, channel length, and source/drain charge injection area are examined. 90 % lower power consumption in the intermediate state is achieved at Vdd = 1 V with a noise margin of 130 mV, compared to other emerging ternary logic devices. The feasibility for stable ternary circuit operation is confirmed as well.

Leveraging Negative Capacitance CNTFETs for Image Processing: An Ultra-Efficient Ternary Image Edge Detection Hardware

Recently, integrating ferroelectric materials with nanotransistors such as carbon nanotube field-effect transistors (CNTFETs) has opened new doors for demonstrating a new generation of ultra-miniature circuits and systems. Utilizing the negative differential resistance effect in negative capacitance CNTFETs (NC-CNTFETs) has spurred the efforts for designing ultra-compact ternary circuits and systems similar to their binary structures. This paper presents an ultra-efficient ternary image edge detection hardware using NC-CNTFET technology. The proposed hardware is endowed with a noise reduction circuitry to mitigate the noise effects. Using four <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\times 3$ </tex-math></inline-formula> kernels and concatenating the image pixels, the proposed ternary hardware has been designed using only 50 transistors. The proposed ternary hardware at the circuit level shows, on average, 74% improvements regarding power delay-product (PDP) compared to the CNTFET-based counterparts. Our comprehensive simulations indicate that the proposed NC-CNTFET-based hardware shows a 40% improvement in data loss, 2.2 times improvement in performance ratio, and 1.14 times improvement in Pratt’s figure-of-merit, respectively, compared to the related designs. Our results accentuate that the proposed NC-CNTFET-based ternary hardware is a breakthrough achievement in demonstrating ultra-efficient and noise-immune ternary image processing circuits beyond the conventional binary counterparts.

Design of ternary subtractor using multiplexers

PurposeThe purpose of this paper is to design multiplexers (MUXs) based on ternary half subtractor and full subtractor using carbon nanotube field-effect transistors.Design/methodology/approachConventionally, the binary logic functions are developed by using the binary decision diagram (BDD) systems. Each node in BDD is replaced by 2:1 MUX to implement the digital circuits. Similarly, in the ternary decision diagram, each node has to be replaced by 3:1 MUX. In this paper, ternary transformed BDD is used to design the ternary subtractors using 2:1 MUXs.FindingsThe performance of the proposed ternary half subtractor and full subtractor using the 2:1 MUX are compared with the 3:1 MUX-based ternary circuits. It has been observed that the delay, power and power delay product values are reduced, respectively, by 67.6%, 84.3%, 94.9% for half subtractor and 67.7%, 70.1%, 90.3% for full subtractor. From the Monte Carlo simulations, it is observed that the propagation delay and power dissipation of the proposed subtractors are increased by increasing the channel length due to process variations. The stability test is also performed and observed that the stability increases as the channel length and diameter are increased.Originality/valueThe proposed half subtractor and full subtractor show better performance over the existing subtractors.

Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM).

Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of multiple resistance states within a single cell. This article presents the 2-trit arithmetic logic unit (ALU) design using CNTFETs and RRAM as the design elements. The proposed ALU incorporates a transmission gate block, a function select block, and various ternary function processing modules. The ALU design optimization is achieved by introducing a controlled ternary adder–subtractor module instead of separate adder and subtractor circuits. The simulations are analyzed and validated using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions (supply voltages) to test the robustness of the designs. The simulation results indicate that the proposed CNTFET-RRAM integration enables the compact circuit realization with good robustness. Moreover, due to the addition of RRAM as circuit element, the proposed ALU has the advantage of non-volatility.

Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs

ABSTRACT This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser power and can be implemented with 10–40% lesser number of transistors, as compared to the other corresponding circuits available in the literature. The reduction in power and transistor count has been achieved through improved multiplexer designs and judicious use of pass transistor logic. CNFETs have low gate capacitance and hence are ideal devices for ultra-low-power VLSI applications; however, CMOS technology is presently the most preferred technology, because of the easy and low-cost fabrication option made available by the well-established CMOS fabrication labs. Keeping this in view, the proposed mux-based ternary half adder has been designed with both 45 nm MOSFETs and CNFETs. The performance of the proposed HA design has been benchmarked with other CNFET HA reported in the literature. The proposed mux-based CNFET ternary HA, FA and 1-bit multiplier have 10–30% lesser propagation delays than the other designs available in the literature. The reduction in the Power Delay Product (PDP) is 85–99% in the proposed mux-based CNFET ternary circuits as compared to the other benchmarked designs.

CNTFET Based Ternary 1-Trit &amp; 2-Trit Comparators for Low Power High-Performance Applications

1-Trit and 2-Trit Ternary comparator circuits using Complementary Metal–Oxide–Semiconductor (CMOS) as well as Carbon Nanotube Field-Effect Transistor (CNTFET) is proposed and investigated for Low Power High-performance applications. The design and simulation are investigated and authenticated using Hailey Simulation Program with Integrated Circuit (HSPICE) with Predictive technology model (PTM) low power 32 nm metal gate/High-K/Strained-Si Model for CMOS and 32 nm Stanford Model for CNTFET. The CNTFET based design is compared with the CMOS design in terms of significant design aspects, specifically delay, Average Power consumption and Power delay product (PDP). A comparison is performed among CMOS and CNTFET based ternary comparator circuits which reveals that CNTFETs can lead to more efficient ternary circuits. In terms of delay and power consumption, the CNTFET based 1-Trit Ternary Comparator performs better than the CMOS based 1-Trit Ternary Comparator as the delay and Average power consumption are reduced by 89.7% and 57.3% in CNTFET type as compared to the CMOS based 1-Trit Ternary Comparator design. Similarly, in the case of the 2-Trit comparator, the CNTFET based design performs better than the CMOS-based design as the delay and Average power consumption are reduced by 88.7% and 42% in the CNTFET type.

Breaking the Limits in Ternary Logic: An Ultra-Efficient Auto-Backup/Restore Nonvolatile Ternary Flip-Flop Using Negative Capacitance CNTFET Technology

Despite the advantages of ternary logic, it has suffered from excessive transistor count and limited noise margin. This work proposes an ultra-efficient nonvolatile ternary flip-flop (FF) based on negative capacitance carbon nanotube field-effect transistors (NC-CNTFETs). By harnessing the negative differential resistance effect in NC-CNTFETs, the proposed design is similar to a conventional volatile binary FF regarding the number of transistors and control signals. During a scheduled power gating or a sudden power outage, the proposed ternary FF benefits from an auto-backup/auto-restore capability without employing any additional transistors, nonvolatile devices, or control signals. This leads to zero device overhead, which is a breakthrough in designing nonvolatile memory circuits. On the other hand, the back-to-back slave latch’s hysteretic behavior provides an extraordinary static noise margin that transcends the noise margin of both conventional ternary and binary latches. The simulation results indicate that eliminating additional backup and restore circuitries provides 43% improvements in transistor count, 59% improvements in power saving and 98% improvements in energy-saving than state-of-the-art binary and ternary FFs. Moreover, the proposed design presents a 1.5 times higher static noise margin than the conventional binary and ternary FFs. Our proposed approach opens new doors in realizing ultra-efficient nonvolatile ternary circuits and systems in neuromorphic applications using ferroelectric-based transistors.