Ternary Content Addressable Memory Research Articles

A look-up table-based processing-in-SRAM architecture for energy-efficient search applications

This paper presents an efficient in-memory computing architecture for search and logic function applications. The proposed design benefits from an SRAM cell, using two single-ended read bit-lines to enable binary and ternary content addressable memories (BCAM and TCAM) and logic functions. As our proposed cell benefits from Schmitt trigger inverters based on independent gate FinFETs. No data distraction occurs due to the half-selection issue. The results indicate no failure in the proposed method in the half-selected cells in the BCAM and TCAM functions. Moreover, the proposed cell shows 58% and 89% lower power in the write and read operations than the conventional SRAM-based IMC design. Also, by providing basic logic operations in the proposed design, applications with high-accuracy requirements can be implemented. Moreover, a neural network is also implemented to assess the proposed design in a practical application. The results show that our design consumes 41% and 50% lower energy than its counterparts.

A novel machine learning‐based classification approach to prevent flow table overflow attack in Software‐Defined Networking

SummarySoftware‐defined networking (SDN) is an emerging networking architecture where the network control is physically separated from the forwarding plane. It is dynamic, manageable, cost‐effective, and flexible, which is ideal for today's high‐bandwidth applications. The flow table is the fundamental data structure residing in ternary content addressable memory (TCAM) that provides flow rules for incoming flows. The TCAM is the costliest part of an SDN switch that can store limited flow rules. Hence, it is susceptible to distributed denial of service (DDoS) and more specifically to Transformed DDoS (TDDoS). It targets the flow tables, exhausting its limited resource, and resulting in flow table overflow. During overflow, the controller is incapable of installing new rules to the switch, and the switch function is disabled from the network. In this paper, a novel framework named machine learning‐based overflow prevention (MLOP) was proposed which includes a victim switch was identified using association rule mining algorithm concepts. Then, the fuzzy C‐means (FCM) was applied to classify the attack in the victim switch. In addition, FCM ensemble with an optimizing method called dynamic time warping (DTW) which detects similar patterns in the time window during classification. Finally, an elbow method is used that determines the cluster count for optimizing clusters which increases the attack detection and also increases the holding time with reduced packet loss. The real‐time network traffic datasets were used for simulations, and the results were compared with other state‐of‐the‐art approaches. The experimental results show that MLOP increases the holding time by 15% on average and reduces the packet loss due to flow table Overflow by 22.81% than the other existing approaches. In addition, the throughput is increased in the proposed MLOP from 10% to 40%, and end‐to‐end delay is reduced between the variations of 10% to 70%.

Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices

This study proposes a self-rectifying ferroelectric tunnel junction (SR-FTJ) crosspoint array to satisfy the stringent size requirements of the Internet-of-Things devices. Each cell in the SR-FTJ crosspoint array consists of two SR-FTJs stacked vertically, resulting in ultrahigh density. The SR-FTJ crosspoint array can operate as: 1) ternary content-addressable memory (TCAM) or 2) binary content addressable memory (BCAM) or physically unclonable function (PUF) in the dual-mode operation. In the dual-mode operation, the amount of the current flowing through the SR-FTJs remains the same, resulting in a stable PUF response regardless of the BCAM data. The dual-mode operation of the SR-FTJ crosspoint array is experimentally verified by 4-in wafer-level demonstrations. HSPICE simulation results using the industrial-compatible 180-nm technology with the SR-FTJ model reflecting measured characteristics show that the SR-FTJ crosspoint array achieves the lowest search energy (2.05 fJ/search/bit) and the highest randomness (Hamming weight of 0.5000) among the previous content addressable memories (CAMs) and PUFs. In addition, the SR-FTJ crosspoint array reduces area by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&gt;$</tex-math> </inline-formula> 84.2% compared to the previous structures that implement individual CAM and PUF.

DT2CAM: A Decision Tree to Content Addressable Memory Framework

Decision trees are powerful tools for data classification. Accelerating the decision tree search is crucial for on-the-edge applications with limited power and latency budget. In this paper, we propose a content-addressable memory compiler for decision tree inference acceleration. We propose a novel ”adaptive-precision” scheme that results in a compact implementation and enables an efficient bijective mapping to ternary content addressable memories while maintaining high inference accuracies. We also develop a resistive-based functional synthesizer to map the decision tree to resistive content addressable memory arrays and perform functional simulations for energy, latency, and accuracy evaluations. We study the decision tree accuracy under hardware non-idealities including device defects, manufacturing variability, and input encoding noise. We test our framework on various decision tree datasets including <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Give Me Some Credit</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Titanic</i> , and <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">COVID-19</i> . Our results reveal up to 42.4% energy savings and up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$17.8\times$</tex-math></inline-formula> better energy-delay-area product compared to the state-of-art hardware accelerators, and up to 333 million decisions per sec for the pipelined implementation.

Design consideration of ferroelectric field-effect-transistors with metal–ferroelectric–metal capacitor for ternary content addressable memory

The performance of ferroelectric field-effect transistor (FeFET)-based ternary content addressable memory (TCAM) is examined to optimize the metal-ferroelectric-metal (MFM) capacitor of FeFET through a compact model based on the multi-domain Preisach theory. To reduce the search delay of the FeFET-based TCAM, the area of the MFM capacitor should be reduced, therefore enhancing polarization. Further, the effect of the polarization properties of ferroelectric material on the performance of the FeFET-based TCAM is explored. The increase in the polarization of ferroelectric material leads to better performance; however, the coercive voltage should also be optimized. As a result, to improve the performance of a circuit using FeFETs, simulations using reliable compact models are required. The results of this study can provide directions for developing ferroelectric materials.

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AbstractThis work (DOI: 10.1002/inf2.12416) demonstrates an in‐memory search system based on the self‐selective memristors. First, by utilizing the intrinsic randomness of the memristor conductance, a hardware locality sensitive hashing (LSH) encoder is constructed to map the feature vectors into compact binary code. Subsequently, an ultra‐low‐power 2R ternary content addressable memory is demonstrated, serving as the high parallel distance computing engine. Based on the in‐memory search system, the typical data mining algorithms are demonstrated as the benchmark and the system shows 168 times energy saving comparing with the CPU with the software‐comparable accuracy. image

BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory

This work presents BP-SCIM: a reconfigurable 8T static random access memory (SRAM) macro for bit-parallel searching and computing in-memory (CIM). The decoupled read/write ports of the employed 8T SRAM bit-cell eliminate read disturbance during search and CIM operations. BP-SCIM can support both in-memory Boolean logic and arithmetic operations. Novel CIM-friendly algorithms and peripheral circuits are proposed to reduce the latency of complex arithmetic operations such as multiplication and division. In addition, BP-SCIM can be configured as either a binary content-addressable memory (CAM) or a ternary CAM for fast searching. A 256 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 64 BP-SCIM test chip was implemented in 65-nm CMOS technology. The 8-bit addition and 8-bit multiplication operations can achieve the maximum energy efficiency of 3.11 TOPS/W and 0.17 TOPS/W, respectively at 0.7 V supply. For the binary CAM search operation, BP-SCIM can achieve the minimum energy consumption of 0.91 fJ/bit/search at 87 MHz and 0.8 V supply.

Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine

Reconfigurable hardware is a promising technology for implementing firewalls, routing mechanisms, and new protocols for evolving high-performance network systems. This work presents a novel deterministic approach for a Range-enhanced Reconfigurable Packet Classification Engine based on the number of rules on FPGAs. The proposed framework uses a RAM-established Ternary Match to represent the prefix and the range prefix and efficient rule-reordering for priority selection to get both best-match and multi-match in the same architecture. The recommended framework exhibits 3.2 Mbits of LUT-RAM-based ternary content addressable memory (TCAM) to hold a maximum of 31.3 K of 104- bit rules with 520 MPPS . LUT-RAM, along with BRAM, shows 4 Mbits of TCAM space to implement 38.5 K of 104- bit rules to sustain a throughput of 400 MPPS on Virtex-7 FPGA. The complete architecture offers scalability, better resource utilization (minimum of 50% ), representation of inverse prefix with single entry, range expansion with a single rule, getting best- and multi-match, and determination of the required number of FPGA resources for a particular dataset.

Ferroelectric Ternary Content Addressable Memories for Energy-Efficient Associative Search

A fast and efficient search function across the database has been a core component for a number of data-intensive tasks in machine learning, IoT applications, and inference. However, the conventional digital machines implementing the search functionality with repetitive arithmetic operations suffer from the energy efficiency and performance degradation due to the significant data transfer between the storage and processing units in the Von Neumann architecture. Ternary content addressable memories (TCAMs) are an essential hardware form of computing-in-memory (CiM) designs that aim to overcome the data transfer bottlenecks by implementing the parallel associative search function within the memory blocks. While most state-of-the-art TCAM designs focus on improving the information density by harnessing compact nonvolatile memories (NVMs), little efforts have been spent on optimizing the energy efficiency of the NVM-based TCAM. In this article, by exploiting the ferroelectric FET (FeFET) as a representative NVM, we propose an NOR-type 2FeFET-1T and an NAND-type 2FeFET-2T TCAM designs that enable highly energy-efficient associative search by reducing the associated precharge overheads. We then propose a hybrid ferroelectric NAND-NOR (HFNN) TCAM design to further improve the energy efficiency. An HFNN-based segmented architecture is proposed to reduce the search delay and energy by search operation pipeline. Evaluation results suggest that the proposed 2FeFET-1T, 2FeFET-2T and HFNN TCAM design consume <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.03\times $ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.08\times $ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$226.92\times $ </tex-math></inline-formula> less search energy than the conventional 16T complementary metal oxide semiconductor (CMOS) TCAM, respectively. Application benchmarking shows that our proposed 2FeFET-1T/2FeFET-2T/HFNN TCAM can save, on average, 45.2%/50.6%/57.5% the GPU energy consumption as compared to the conventional GPU.

Non-volatile logic-in-memory ternary content addressable memory circuit with floating gate field effect transistor

Due to the limitations of the currently widely used von Neumann architecture-based computing system, research on various devices and circuit systems suitable for logic-in-memory computing applications has been conducted. In this work, the silicon-based floating gate memory cell transistor structure, which has been attracting attention as a memory to replace the dynamic random access memory or NAND Flash technology, was newly recalled, and its applicability to logic-in-memory application was confirmed. This floating gate field effect transistor (FGFET) has the advantage that the compatibility of the existing silicon-based complementary metal–oxide–semiconductor (CMOS) process is far superior to that of logic-in-memory application devices to which materials with new memory characteristics are applied. At the 32 nm technology node, which is the front node to which the planar MOSFET structure is applied, an analysis environment that can simultaneously analyze the device and circuit of the FGFET was established. For a seamless connection between FGFET-based devices and circuit analysis, the compact model of the FGFET was developed, which is applied to logic-in-memory ternary content addressable memory (TCAM) circuit design. It was verified that the two types of logic-in-memory TCAM circuits to which FGFETs are applied are superior to a conventional CMOS FET-based TCAM circuit in the number of devices used (=circuit area) and power/energy efficiency.

Ferroelectric-gate tunnel field-effect transistor one-transistor ternary contents addressable memory

In the era of ‘big data’, the von Neumann architecture has significant energy consumption and latency penalties for data transfer between memory and processor. However, ternary content addressable memories (TCAMs) enable fast and energy-efficient operation by performing a parallel search for given data and returning information about whether it matches. In this study, a single transistor (1T) ferroelectric-gate tunnel FET (FeTFET) was introduced for TCAM operations, and its functionality was verified through technology computer-aided design (TCAD) simulations. The FeTFET has intrinsic directional currents due to its unique p–i–n structure. Also, the transfer curve of the FeTFET can be shifted in both directions depending on the polarization state of the ferroelectric material. By combining these properties of the FeTFET, it was confirmed that stable search operations can be performed for stored logic states. Thus, compared to conventional TCAM cell that use two or more transistors, it is expected that the proposed 1T-TCAM cell can store and search more bits in the same area.

Self‐selective memristor‐enabled in‐memory search for highly efficient data mining

AbstractSimilarity search, that is, finding similar items in massive data, is a fundamental computing problem in many fields such as data mining and information retrieval. However, for large‐scale and high‐dimension data, it suffers from high computational complexity, requiring tremendous computation resources. Here, based on the low‐power self‐selective memristors, for the first time, we propose an in‐memory search (IMS) system with two innovative designs. First, by exploiting the natural distribution law of the devices resistance, a hardware locality sensitive hashing encoder has been designed to transform the real‐valued vectors into more efficient binary codes. Second, a compact memristive ternary content addressable memory is developed to calculate the Hamming distances between the binary codes in parallel. Our IMS system demonstrated a 168× energy efficiency improvement over all‐transistors counterparts in clustering and classification tasks, while achieving a software‐comparable accuracy, thus providing a low‐complexity and low‐power solution for in‐memory data mining applications.image

AM4: MRAM Crossbar Based CAM/TCAM/ACAM/AP for In-Memory Computing

In-memory computing seeks to minimize data movement and alleviate the memory wall by computing in-situ, in the same place that the data is located. One of the key emerging technologies that promises to enable such computing-in-memory is spin-transfer torque magnetic tunnel junction (STT-MTJ). This paper proposes AM4, a combined STT-MTJ-based Content Addressable Memory (CAM), Ternary CAM (TCAM), approximate matching (similarity search) CAM (ACAM), and in-memory Associative Processor (AP) design, inspired by the recently announced Samsung MRAM crossbar. We demonstrate and evaluate the performance and energy-efficiency of the AM4-based AP using a variety of data intensive workloads. We show that an AM4-based AP outperforms state-of-the-art solutions both in performance (with the average speedup of about 10 ×) and energy-efficiency (by about 60 × on average).

An integrated load balancing scheme based on SDN ASR algorithm

At present, the flow table of the SDN switch is stored in the costly Ternary Content Addressable Memory (TCAM) cache. Due to the cost problem, the number of flow tables that the SDN switch can store is extremely limited, which is far less than the number of traffic, so it is prone to overflow problem, and leads to network paralysis. That has become a bottleneck in restricting the processing capacity of the data center, and will become a weak point focused by attackers. In this paper, we propose an algorithm for the Alarm Switch Remove (ASR) that fully loads the flow table space in SDN, and further put forward an integrated load balancing scheme in SDN. Finally, we use Mininet to verify that the scheme can ease the SDN switch flow table overflow problem and increase network throughput.

Integration of Interdomain Flow-Rule in Software-Defined Networks for Embedded Internet of Things Devices

Software-defined networking (SDN) is an evolving technology providing proper segregation between the control part and data-forwarding domain of network devices. The expansion of the Internet of Things (IoTs) and embedded mobile devices increases the volume of traffic at the network backbone and causes processing costs in the control plane. This directly affects the Ternary Content Addressable Memory (TCAM) of the switches because insufficient space makes it more challenging to manage the flow-entries. In this situation, providing services to specific users who newly authenticate after the successful handoff from the previous SDN domain is challenging. This paper proposes a method for implanting the users’ primary domain’s flow-rules in the serving SDN domain. As the TCAM is already suffering from a short space, it is hard to handle the flow-tables of multiple SDN domains in limited TCAM storage. The SDN-based Integration of the Interdomain Flow-rule in the SDN (IIF-SDN) scheme maximizes the proficiency of the switches by effectively storing flow-table and flow-entries. The effectiveness of the proposed scheme is benchmarked with proactive and reactive SDN approaches.

In-memory computing with emerging memory devices: Status and outlook

In-memory computing (IMC) has emerged as a new computing paradigm able to alleviate or suppress the memory bottleneck, which is the major concern for energy efficiency and latency in modern digital computing. While the IMC concept is simple and promising, the details of its implementation cover a broad range of problems and solutions, including various memory technologies, circuit topologies, and programming/processing algorithms. This Perspective aims at providing an orientation map across the wide topic of IMC. First, the memory technologies will be presented, including both conventional complementary metal-oxide-semiconductor-based and emerging resistive/memristive devices. Then, circuit architectures will be considered, describing their aim and application. Circuits include both popular crosspoint arrays and other more advanced structures, such as closed-loop memory arrays and ternary content-addressable memory. The same circuit might serve completely different applications, e.g., a crosspoint array can be used for accelerating matrix-vector multiplication for forward propagation in a neural network and outer product for backpropagation training. The different algorithms and memory properties to enable such diversification of circuit functions will be discussed. Finally, the main challenges and opportunities for IMC will be presented.

Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme

Fast communication between networking devices increases the importance of the ternary content addressable memory (TCAM). The demands for low energy in networking devices have accelerated the research on nonvolatile TCAMs that store data without the power supply. Recently, ferroelectric field-effect transistors (FeFETs), nonvolatile three-terminal devices with a high on/off ratio, have been adopted for TCAMs. Although the previous FeFET TCAMs consume low write energy with a significantly compact TCAM cell area, they suffer from write problems: 1) the write scheme cannot afford the saturated polarization switching in FeFETs and 2) the states stored in the unselected TCAM cells are changed during the write operation. In addition, search yield is deteriorated by wide process variations of FeFETs. This paper proposes a novel FeFET TCAM that is free from the write problems of the previous FeFET TCAMs and tolerant to process variations. This paper also proposes a novel match line scheme to improve search energy and time by reducing match line capacitance and the amount of discharged voltage in the match evaluation phase. Industrial-compatible 28 nm technology-based simulation results with the Preisach FeFET model show that the proposed FeFET TCAM achieves the highest search yield.

Design of a Compact Spin-Orbit-Torque-Based Ternary Content Addressable Memory

This article presents the design of a novel and compact spin-orbit torque (SOT)-based ternary content addressable memory (TCAM). Experimentally validated/calibrated micromagnetic and macrospin simulations have been used to quantify various tradeoffs regarding the write operation, such as write energy, error rate, and retention time. SPICE simulations incorporating various sources of variability are used to evaluate search operations, optimize the proposed novel TCAM cell based on SOT magnetic random access memory (SOT-MRAM), and benchmark it against static random access memory (SRAM)- and FeFET-based TCAMs. We show low search error rates (SERs) (< 10−4) while considering various sources of variability for four transistors- and two magnetic tunnel junctions (MTJs)-based TCAM array.

Structural plasticity‐based hydrogel optical Willshaw model for one‐shot on‐the‐fly edge learning

AbstractAutonomous one‐shot on‐the‐fly learning copes with the high privacy, small dataset, and in‐stream data at the edge. Implementing such learning on digital hardware suffers from the well‐known von‐Neumann and scaling bottlenecks. The optical neural networks featuring large parallelism, low latency, and high efficiency offer a promising solution. However, ex‐situ training of conventional optical networks, where optical path configuration and deep learning model optimization are separated, incurs hardware, energy and time overheads, and defeats the advantages in edge learning. Here, we introduced a bio‐inspired material‐algorithm co‐design to construct a hydrogel‐based optical Willshaw model (HOWM), manifesting Hebbian‐rule‐based structural plasticity for simultaneous optical path configuration and deep learning model optimization thanks to the underlying opto‐chemical reactions. We first employed the HOWM as an all optical in‐sensor AI processor for one‐shot pattern classification, association and denoising. We then leveraged HOWM to function as a ternary content addressable memory (TCAM) of an optical memory augmented neural network (MANN) for one‐shot learning the Omniglot dataset. The HOWM empowered one‐shot on‐the‐fly edge learning leads to 1000× boost of energy efficiency and 10× boost of speed, which paves the way for the next‐generation autonomous, efficient, and affordable smart edge systems.image

Memristor Crossbar Circuit for Ternary Content‐Addressable Memory with Fine‐Tuning Operation

Memristor‐based ternary content‐addressable memory (TCAM) has emerged as an alternative to conventional static random‐access memory (SRAM)‐based TCAM because of its high‐density integration and zero‐static energy consumption. Herein, 0T2R TCAM operation on a 32 × 32 passive memristor crossbar circuit is experimentally verified. The effective margin, which is the difference between the match case and 1‐bit mismatch case, is improved through precise tuning operations. Moreover, the number of mismatch bits and match cases can be accurately detected thanks to the linear relationship between the number of mismatch bits and match‐line current. In addition, the nonideal effects in the passive crossbar array including dynamic voltage drop and sneak current are analyzed through SPICE studies. These results indicate that the proposed TCAM operating conditions can ensure stable TCAM operation in larger arrays.