Ternary Adder Research Articles

Energy-efficient design and CNFET implementation of GDI-based ternary prefix adders

Abstract Ternary adders have produced more benefits compared to binary adders i.e., the ternary adder occupies less amount of area as well as produces less interconnect complexity. However, the CMOS implementation of the ternary adders failed to perform the process when the channel length was taken as 32 nm. At 32 nm technology, the CMOS transistors exhibit undesired effects such as Short Channel Effects (SCEs), mobility degradation, high leakage current, etc. Multi-gate devices are preferred to overcome these issues. Carbon Nano-tube Field Effect Transistors (CNFETs) are one of the technologies to work efficiently when the channel length is 32 nm. In this paper, CNFET-based ternary prefix adders are designed. Power consumption is the most critical requirement for the VLSI system, as it enhances energy efficiency and reduces heat dissipation. One way to achieve this power reduction is by minimizing the number of transistors employed in the adder circuits. This study employed a reduction technique known as Gate Diffusion Input (GDI) logic included in the proposed prefix adder design. The overall experimental investigation is done with the help of the HSPICE supporting platform. The proposed adder improved by reducing the power by up to 83%, energy by up to 83%, current by up to 78%, and delay by up to 96%. Finally, the Power Delay product (PDP) was also reduced by 84% compared to existing ternary adders. The proposed design proves to be highly effective in implementing the neuron structure, with the corresponding parameters thoroughly analysed and well-documented in this study.

Comparing Unbalanced and Balanced CNTFET Ternary Adders and Multipliers with the Corresponding Binary Ones

This paper compares the performance of the ternary adders and multipliers using balanced and unbalanced set of values. We use the 1-trit adders to evaluate the two versions of a 4-trit propagate adder, which are comparedwith a 6-bit corresponding propagate adder. Similarly, we compare the two types of 2*2 trit multipliers with a3*3 bit multiplier. The simulations with a 32-nm Carbon Nanotuble Field-Effect Transistor (CNTFET) technology show that the binary adders and multipliers are more efficient than the ternary ones that compute the same amount of information

Efficient realization of quantum balanced ternary reversible multiplier building blocks: A great step towards sustainable computing

Nowadays, quantum computing plays a significant role in reducing the execution time in complicated computations. There are different reversible algorithms for quantum computation and many quantum circuits theoretically designed until now. These designs are only built from reversible gates because reversibility is a necessary logic in quantum circuits. Additionally, ternary representation can allow designing a circuit with fewer inputs and outputs, leading to a considerable decline in size or number of qutrits. Although other papers in quantum ternary reversible logic are in unbalanced representation, this paper, for the first time, considers balanced ternary advantages to achieve a more efficient design for quantum multipliers as the main component in arithmetic blocks. Six criteria are introduced to show how balanced representation increases the overall performance. In this work, two general balanced ternary adder blocks (full-adder and half-adder) and two balanced ternary partial product generators (BTPPGs) are proposed, and also a 2 × 2 and a 3 × 3 balanced ternary multipliers built from these components. The quantum costs of proposed balanced ternary multipliers enhanced 17% for a 2 × 2 multiplier and 34% for a 3 × 3 multiplier.

Ternary Full Adder Designs Employing Unary Operators and Ternary Multiplexers.

The design of the Ternary Full Adders (TFA) employing Carbon Nanotube Field-Effect Transistors (CNFET) has been widely presented in the literature. To obtain the optimal design of these ternary adders, we propose two new different designs, TFA1 with 59 CNFETs and TFA2 with 55 CNFETs, that use unary operator gates with two voltage supplies (Vdd and Vdd/2) to reduce the transistor count and energy consumption. In addition, this paper proposes two 4-trit Ripple Carry Adders (RCA) based on the two proposed TFA1 and TFA2; we use the HSPICE simulator and 32 nm CNFET to simulate the proposed circuits under different voltages, temperatures, and output loads. The simulation results show the improvements of the designs in a reduction of over 41% in energy consumption (PDP), and over 64% in Energy Delay Product (EDP) compared to the best recent works in the literature.

Post algebras and ternary adders

Except for qubits for which the different possible values are unordered, the different values of m-valued circuits either with voltage levels, current levels or charge levels are totally ordered. Either at the Math level (Post algebras) or at the circuit level, it means that each multiple valued level must be decomposed into binary levels, processed with binary computation and finally converted into a multiple valued level. Using ternary adders as example, we show that the ternary-to-binary decoding and binary encoding should be applied to the whole adder or to restricted parts of the adder. The second approach using multiplexers leads to the most efficient ternary adders. However, a comparison with binary adders shows that the ternary-to-binary and binary-to-ternary conversions is the reason for which the binary adders are more efficient.

A Low-Power Ternary Adder Using Ferroelectric Tunnel Junctions

Computing systems are becoming more and more power-constrained due to unconventional computing requirements like computing on the edge, in-sensor, or simply an insufficient battery. Emerging Non-Volatile Memories are explored to build low-power computing circuits, and adders are one among them. In this work, we propose a low-power adder using a Ferroelectric Tunnel Junction (FTJ). FTJs are two-terminal devices where the data is stored in the polarization state of the device. An FTJ-based majority gate is proposed, which uses a current-mode sensing technique to evaluate the majority of the inputs. By conditionally selecting between the majority and its complement, an XOR operation is implemented, thereby achieving full-adder functionality. Since FTJ-based majority operation is slow, a ternary adder architecture is used to compensate for the speed loss. The ternary adder proposed by us has two stages of full adder and requires O(1) time for n-bit addition. The proposed adder is verified using a simulation in CMOS 130 nm technology. A 32-bit addition can be achieved in 100 μs and consumes 0.78 pJ, which is very power efficient (7.8 nW). The proposed adder can be used in applications where power consumption is crucial, and speed is not a strict requirement.

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

AbstractThe history of ternary adders goes back to more than 6 decades ago. Since then, a multitude of ternary full adders (TFAs) have been presented in the literature. This article conducts a review of TFAs so that one can be familiar with the utilised design methodologies and their prevalence. Moreover, despite numerous TFAs, almost none of them are in their simplest form. A large number of transistors could have been eliminated by considering a partial TFA instead of a complete one. According to our investigation, only 28.6% of the previous designs are partial TFAs. Also, they could have been simplified even further by assuming a partial TFA with an output carry voltage of 0 V or VDD. This way, in a single‐VDD design, voltage division inside the Carry generator part would have been eliminated and less power dissipated. As far as we have searched, there are only three partial TFAs with this favourable condition in the literature. Additionally, most of the simulation setups in the previous articles are not realistic enough. Therefore, the simulation results reported in these papers are neither comparable nor entirely valid. Therefore, the authors got motivated to conduct a survey, elaborate on this issue, and enhance some of the previous designs. Among 84 papers, 10 different TFAs (from 11 papers) are selected, simplified, and simulated in this article. Simulation results by HSPICE and 32 nm carbon nanotube FET technology reveal that the simplified partial TFAs outperform their original versions in terms of delay, power, and transistor count.

Optimizing Ternary Multiplier Design With Fast Ternary Adder

Existing ternary multiplier designs are difficult to use in ternary systems. Thus, ternary Wallace tree multipliers that reduce the number of transistors by using 4-input ternary adders are proposed to improve the performance of existing ternary multipliers. A ternary carry-select adder is also proposed to reduce the carry propagation delay, used as a carry-chain adder of the Wallace tree. The proposed multipliers are designed with a custom ternary standard cell library synthesized by multi-threshold complementary metal-oxide-semiconductor (CMOS) with a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$28~nm$ </tex-math></inline-formula> process. Power and delay are verified via HSPICE simulation. The proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$36\times36$ </tex-math></inline-formula> ternary multiplier shows 79.3% power-delay product improvement over the previous ternary multiplier. The proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$40\times40$ </tex-math></inline-formula> ternary multiplier shows a power-delay product comparable with that of the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$64\times64$ </tex-math></inline-formula> binary multiplier synthesized using Synopsys Design Compiler.

Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits

Multiple valued logic (MVL) can represent an exponentially higher number of data/information compared to the binary logic for the same number of logic bits. Compared to the conventional devices, the emerging device technologies such as Graphene Nano Ribbon Field Effect Transistor (GNRFET) and carbon nanotube field effect transistor (CNTFET) appears to be very promising for designing MVL logic gates and arithmetic circuits due to some exceptional electrical properties such as the ability to control the threshold voltage. This variation of the threshold voltage is one of the prescribed techniques to achieve multiple voltage levels to implement the MVL circuit.This work presents a 4-input ternary adder using carbon nanotube field effect transistor (CNTFET). Many researchers have been done work on implementation of ternary adders and multipliers. But no one has done the comparison of this proposed ternary adder with different types of nano transistors. Hence this work has been proposed a design of low power and high speed 4-input adder which will be useful for designing of fast ternary multipliers. All the proposed designs have been simulated using emerging device such as CNTFET at 32nm technology node. From the simulations, we have calculated the power consumptions of the proposed designs, carry propagation delay and power delay product for the CNTFET circuits. It has been observed that CNTFET based proposed logic circuits given a better performance than the conventional logical circuits.

Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders

This work presents comparison of ternary combinational digital circuits that reduce energy consumption in low-power VLSI (Very Large Scale Integration) design. CNTFET and GNRFET-based ternary half adder (THA) and multiplier (TMUL) circuits has been designed using ternary unary operator circuits at 32nm technology node and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. The effect of CNTFET and GNRFET parametric variation with threshold voltage on performance metrics namely delay and power has been analyzed. Dependence of threshold voltage on the geometry of carbon nanotube and graphene nanoribbon makes it feasible to be used for ternary logic design. It is analyzed that CNTFET based circuits are energy efficient than the GNRFET- based circuits. It is also concluded that the CNTFET-based circuitshas less power-delay product (PDP) when compared to GNRFET- based circuits. CNTFET-based THA is 23.5% more efficient than GNRFET-based THA and CNTFET-based Tmul is97.8% more efficient than GNRFET-based Tmul.All the digital circuits have been simulated using HSPICE tool.

Fast Complete Ternary Addition with Novel 3:1 T-Multiplexer

Background: Complete Ternary Adder is the prime building block for Ternary Carry Save Adder (TCSA) and acts as a critical deciding factor to optimize the overall speed-power performance for many complex ternary computing like ternary multiplications. Objective: This work proposes a new idea for high-speed complete Ternary Adder design with reduced Power-Delay-Product (PDP) using PTL (Pass Transistor Logic) based novel 3:1 Ternary Multiplexer (T-MUX) for efficient ternary computing. Materials: No external materials have been used in the present work. Methods: In the proposed approach, a novel 3:1 T-MUX with conventional E-MOS (Enhancementtype Metal Oxide Semiconductor) transistor is designed first. The Novel Select Unit (SU) and Control Unit (CU) are the prime building blocks of the proposed T-MUX circuit, which are discussed in detail. The 3:1 T-MUX is exploited next to achieve the proposed high-speed, low-PDP Ternary Half and Full Adder operation. The complete adder circuit is designed and optimized based on BSIM4 device parameters using 32nm standard CMOS technology with 1.0V supply rail at 27°C temperature. Trit values “0”, “1” and “2” are represented with 0V, 0.5V and 1.0V respectively. Extensive T-Spice simulation with all possible test patterns using PWL (Piece Wise Linear) input source validates the proposed circuit. The evaluated speed-power result of the proposed TFA is then compared with the most recent competitive study to set a benchmark. Results: The proposed complete TFA offers 68.9% and 82.5% reduction in propagation delay along with 27.7% and 31.6% Power-Delay-Product (PDP) reduction compared to the most recent competitive complete TFA Design-1 and Design-2, respectively. Discussion: As per the study, the proposed idea can be a good selection to produce fast ternary addition along with reduced Power-Delay-Product (PDP). Conclusion: The proposed complete TFA can be utilized effectively as Ternary Carry Save Adder (TCSA) for fast, low-PDP ternary multiplication as well as for other computation-intensive applications.

Novel ternary adders and subtractors in quantum cellular automata

Novel ternary adders and subtractors in quantum cellular automata

A high-efficiency Wallace tree based multi-trit multiplier in CNTFET technology

ABSTRACT In this paper, a multi-digit ternary (multi-trit) Wallace tree-based multiplier in CNTFET technology is presented. In this work, a modified 1-trit multiplier is applied to reduce the number of the CNTFETs where it uses unary operators to estimate the product and the carry. An optimised architecture of a multi-digit ternary adder is also presented. It is applied at the last stage of the multiplier to reduce the overall propagation delay. Hence, higher speed is achieved spending a few more number of CNTFETs. The proposed design is simulated in HSPICE using Stanford University’s 32 nm CNFET technology model. Simulation results show significant improvements in power delay products and hardware utilisation. The proposed 3-trit multiplier applies 750 number of CNTFETs where the PDP is 75 fJ. This represents an approximately 20% improvement in the PDP while more than 100 CNTFETs are saved. For further evaluation, the proposed structure is also extended to 6, 9 and 12-trit multipliers.

Algorithmic basis for the functioning of private autonomous combat neural networks: algebraization of language forms

It is shown that the modern development of weapons and military equipment will trigger the issue of improving artificial intelligence systems, in particular, their gradual convergence with human intelligence. It is shown that this requires the discovery of the algorithmic basis of artificial intelligence systems, including on the basis of the transition to multivalued logics. A close relationship has been established between the algebraization of natural language and the creation of the language of combat neural networks distributed systems in which processing is carried out based on the same operations that are involved in the human brain. The basis for this is the natural definition of language as a transpersonal structure, which largely determines the nature of human intelligence. A universal means of aggregating police multi-valued logics is provided, many elements can be placed at the disposal of General Galois. Thus, an analogue of the Zhegalkin polynomial is used, which is valid for achieving multi-valued logic with the use of properties (the Zhegalkin polynomial itself applies only to the case of binary logic). A selective case study that proves the constructiveness of the proposed application, a discoverable solution that tests the operation of a ternary adder using a Galois field containing three elements.

Design and implementation of ternary adder for High-Performance arithmetic applications by using CNTFET material

This work presents 1-bit hybrid full adder cell using proposed ternary logic along with carbon nanotube. The novelty of this design is the remarkable optimization of power consumption by reducing the hardware part which makes it area efficient and low power. Wide bandwidth and High speed are other salient features of the presented design. To begin with Proposed ternary logic, it works in three logic level in addition to that it improvises dynamic performance of full adder along with CNT technology to maintain the law of scalability for enhancing the silicon technology. The work has been simulated on HSPICE software using 32 nm process CNTFET technology. The operation voltage was.9V at 100 MHz frequency. The relative improved percentage in the area and PDP to be found 13.01–56.18% and 14.27–58.54% respectively. In order to provide fair comparison relative data of similar studies and simulated results has been carried out and put in the tabular form in the later part of the paper.

TReMo+: Modeling Ternary and Binary ReRAM-Based Memories With Flexible Write-Verification Mechanisms

Non-volatile memory (NVM) technologies offer a number of advantages over conventional memory technologies such as SRAM and DRAM. These include a smaller area requirement, a lower energy requirement for reading and partly for writing, too, and, of course, the non-volatility and especially the qualitative advantage of multi-bit capability. It is expected that memristors based on resistive random access memories (ReRAMs), phase-change memories, or spin-transfer torque random access memories will replace conventional memory technologies in certain areas or complement them in hybrid solutions. To support the design of systems that use NVMs, there is still research to be done on the modeling side of NVMs. In this paper, we focus on multi-bit ternary memories in particular. Ternary NVMs allow the implementation of extremely memory-efficient ternary weights in neural networks, which have sufficiently high accuracy in interference, or they are part of carry-free fast ternary adders. Furthermore, we lay a focus on the technology side of memristive ReRAMs. In this paper, a novel memory model in the circuit level is presented to support the design of systems that profit from ternary data representations. This model considers two read methods of ternary ReRAMs, namely, serial read and parallel read. They are extensively studied and compared in this work, as well as the write-verification method that is often used in NVMs to reduce the device stress and to increase the endurance. In addition, a comprehensive tool for the ternary model was developed, which is capable of performing energy, performance, and area estimation for a given setup. In this work, three case studies were conducted, namely, area cost per trit, excessive parameter selection for the write-verification method, and the assessment of pulse width variation and their energy latency trade-off for the write-verification method in ReRAM.

Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM).

Due to the difficulties associated with scaling of silicon transistors, various technologies beyond binary logic processing are actively being investigated. Ternary logic circuit implementation with carbon nanotube field effect transistors (CNTFETs) and resistive random access memory (RRAM) integration is considered as a possible technology option. CNTFETs are currently being preferred for implementing ternary circuits due to their desirable multiple threshold voltage and geometry-dependent properties, whereas the RRAM is used due to its multilevel cell capability which enables storage of multiple resistance states within a single cell. This article presents the 2-trit arithmetic logic unit (ALU) design using CNTFETs and RRAM as the design elements. The proposed ALU incorporates a transmission gate block, a function select block, and various ternary function processing modules. The ALU design optimization is achieved by introducing a controlled ternary adder–subtractor module instead of separate adder and subtractor circuits. The simulations are analyzed and validated using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions (supply voltages) to test the robustness of the designs. The simulation results indicate that the proposed CNTFET-RRAM integration enables the compact circuit realization with good robustness. Moreover, due to the addition of RRAM as circuit element, the proposed ALU has the advantage of non-volatility.

Mux Based Ultra-Low-Power Ternary Adders and Multiplier implemented with CNFET and 45 nm MOSFETs

ABSTRACT This paper presents improved multiplexer-based ultra-low-power ternary Half Adder (HA), ternary Full Adder (FA), and ternary 1-bit multiplier designs. The proposed circuits consume 61–91% lesser power and can be implemented with 10–40% lesser number of transistors, as compared to the other corresponding circuits available in the literature. The reduction in power and transistor count has been achieved through improved multiplexer designs and judicious use of pass transistor logic. CNFETs have low gate capacitance and hence are ideal devices for ultra-low-power VLSI applications; however, CMOS technology is presently the most preferred technology, because of the easy and low-cost fabrication option made available by the well-established CMOS fabrication labs. Keeping this in view, the proposed mux-based ternary half adder has been designed with both 45 nm MOSFETs and CNFETs. The performance of the proposed HA design has been benchmarked with other CNFET HA reported in the literature. The proposed mux-based CNFET ternary HA, FA and 1-bit multiplier have 10–30% lesser propagation delays than the other designs available in the literature. The reduction in the Power Delay Product (PDP) is 85–99% in the proposed mux-based CNFET ternary circuits as compared to the other benchmarked designs.

CNFET-Based Ultra-Low-Power Dual-$$V_{DD}$$ Ternary Half Adder

CNFET-Based Ultra-Low-Power Dual-$$V_{DD}$$ Ternary Half Adder

A low-power dynamic ternary full adder using carbon nanotube field-effect transistors

Ternary logic uses fewer interconnects than binary logic, and smaller voltage swings are required for the same information transfer. Carbon Nanotube transistors (CNFETs) have many advantages over Metal Oxide Semiconductor transistors (MOSFETs), such as equal mobility of electrons and holes, the ability to adjust the threshold voltage by changing the nanotube's diameter, and lower leakage power. In this paper, a dynamic ternary full adder is presented using CNFETs. Subsequently, a 5-trit ripple carry adder is designed based on the proposed dynamic ternary full adder and buffer circuits. The proposed hybrid circuits are designed using clocked dynamic logic. Synopsys HSPICE simulator and Stanford's 32-nanometer CNFET model are used to simulate the circuits. The performance of the approach is evaluated under different supply voltages, loads, and temperatures. It is shown that the proposed full adder has lower power consumption, transistor count, PDP, and EDP compared with previously presented ternary adders. Furthermore, the proposed circuit is more robust to process variations.