Abstract
ABSTRACT In this paper, a multi-digit ternary (multi-trit) Wallace tree-based multiplier in CNTFET technology is presented. In this work, a modified 1-trit multiplier is applied to reduce the number of the CNTFETs where it uses unary operators to estimate the product and the carry. An optimised architecture of a multi-digit ternary adder is also presented. It is applied at the last stage of the multiplier to reduce the overall propagation delay. Hence, higher speed is achieved spending a few more number of CNTFETs. The proposed design is simulated in HSPICE using Stanford University’s 32 nm CNFET technology model. Simulation results show significant improvements in power delay products and hardware utilisation. The proposed 3-trit multiplier applies 750 number of CNTFETs where the PDP is 75 fJ. This represents an approximately 20% improvement in the PDP while more than 100 CNTFETs are saved. For further evaluation, the proposed structure is also extended to 6, 9 and 12-trit multipliers.
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