High-performance 3–2 Compressor Using Efficient XOR-XNOR in Nanotechnology

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AbstractIn this paper, two new 3–2 compressor architecture topologies are proposed which have low power and high speed using both CMOS and CNTFET technology. A 3–2 compressor topology involves XOR-XNOR module and 2:1 multiplexer module. The performance of recent XOR-XNOR circuits is analyzed in terms of transistor count, power dissipation, delay, power-delay product (PDP), and energy delay product (EDP). The superiority of pass transistor logic-based multiplexer is established over transmission gate-based multiplexer is validated by simulation results. Thus, high-performance 3–2 compressor is implemented using 10 T XOR-XNOR gate and PTL-based 2:1 multiplexer. In order to prove effectiveness, the performance of the proposed 3–2 compressor design 1 is compared with the 3–2 compressor design 2 in terms of transistor count, power dissipation, delay, power-delay product (PDP), and energy delay product (EDP). Performances of all circuits are justified using Cadence Virtuoso Analog Environment in 45 nm gpdk technology and 10 nm Stanford CNTFET model at 0.6–1.4 V supply.Keywords3–2 compressorCNTFETXOR-XNOR circuitFull adder