Terman Method Research Articles

Passivation of Ge/high-κ interface using RF Plasma nitridation

In this paper, plasma nitridation of a germanium surface using NH3 and N2 gases is performed with a standard RF-PECVD method at a substrate temperature of 250 °C. The structural and optical properties of the Ge surface have been investigated using Atomic Force Microscopy (AFM), Fourier Transform Infrared Spectroscopy (FT-IR), and Variable Angle Spectroscopic Ellipsometery (VASE). Study of the Ge (100) surface revealed that it is nitrated after plasma treatment while the GeO2 regrowth on the surface has been suppressed. Also, stability of the treated surface under air exposure is observed, where all the measurements were performed at room ambient. The electrical characteristics of fabricated Al/Ti/HfO2/GeON/p-Ge capacitors using the proposed surface treatment technique have been investigated. The C-V curves indicated a negligible hysteresis compared to ∼500 mV observed in untreated samples. Additionally, the C-V characteristic is used to extract the high-κ/Ge interface trap density using the most commonly used methods in determining the interface traps. The discussion includes the Dit calculation from the high-low frequency (Castagné–Vapaille) method and Terman (high-frequency) method. The high-low frequency method indicated a low interface trap density of ∼2.5 × 1011 eV−1.cm−2 compared to the Terman method. The J-V measurements revealed more than two orders of magnitude reduction of the gate leakage. This improved Ge interface quality is a promising low-temperature technique for fabricating high-performance Ge MOSFETs.

Modification of the Terman method for determination of interface states in metal–insulator–semiconductor structures

In this work a modification of Terman method for determination of interfacial energy states located in the forbidden energy gap of the semiconductor (interface states) convenient for application in metal—high-κ—Si structures is proposed and explained in details. It has been found that usually observed presence of tails in the distribution of interface states towards the band edges is an artifact due to the method of determination of interface state densities. While excluding the contribution of quantum charge in semiconductor close to the interface with dielectric, these tails in the distribution disappear. Simple efficient method for determination of total density of interface states over the silicon bandgap is proposed.

Germanium MOS capacitors grown on Silicon using low temperature RF-PECVD

In this paper, Ge metal-oxide-semiconductor capacitors (MOSCAPs) are fabricated on Si using a low temperature two-step deposition technique by radio frequency plasma enhanced chemical vapor deposition. The MOSCAP gate stack consists of atomic layer deposition of Al2O3 as the gate oxide and a Ti/Al metal gate electrode. The electrical characteristics of 9 nm Al2O3/i-Ge/Si MOSCAPs exhibit an n-type (p-channel) behavior and normal high frequency C–V responses. In addition to CV measurements, the gate leakage versus the applied voltage is measured and discussed. Moreover, the electrical behavior is discussed in terms of the material and interface quality. The Ge/high-k interface trap density versus the surface potential is extracted using the most commonly used methods in detemining the interface traps based on the capacitance–voltage (C–V) curves. The discussion included the Dit calculation from the conductance method, the high-low frequency (Castagné–Vapaille) method, and the Terman (high-frequency) method. Furthermore, the origins of the discrepancies in the interface trap densities determined from the different methods are discussed. The study of the post annealed Ge layers at different temperatures in H2 and N2 gas ambient revealed an improved electrical and transport properties of the films treated at T < 600 °C. Also, samples annealed at <550 °C show the lowest threading dislocation density of ~1 × 106 cm−2. The low temperature processing of Ge/Si demonstrates a great potential for p-channel transistor applications in a monolithically integrated CMOS platform.

Improved Schottky behavior of GaN nanorods using hydrogen plasma treatment

In order to find the effect of hydrogen (H) treatment on leakage current and current conduction mechanism in GaN nanorods (NRs) Schottky diode, GaN NRs surface was subjected to H plasma treatment. Experimental results showed that Schottky barrier height (Φb) increased, while the ideality factor (n) decreases by the H treatment. The Φb, n of as-grown GaN NRs were found to be 0.54 eV, 2.16, on the other hand in H treated GaN NRs Schottky diodes, Φb was found to be increase to 0.72 eV, and n decreased to 1.30. Barrier inhomogeneity was confirmed by temperature dependence I-V parameters. The surface state density (NSS) calculated from Terman's method were found to be 1.21 × 1013 eV−1cm−2 and 2.15 × 1012 eV−1cm−2 for as-grown and H treated GaN NRs respectively. These results suggested H treatment effectively passivate the surface states and decreased NSS could be leads to enhancement in the Schottky behavior of GaN NRs.

Interface State Density in Atomic Layer Deposited SiO2/&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\beta $ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Ga2O3(&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\bar {2}01$ &lt;/tex-math&gt; &lt;/inline-formula&gt;) MOSCAPs

The interface state density ( $D_{\mathrm{ it}})$ at the interface between $\beta $ -Ga2O3 ( $\bar {2}01$ ) and atomic layer deposited (ALD) SiO2 dielectric is extracted using Terman method and conductance method. The effect of the different surface treatments on the extracted $D_{\mathrm{ it}}$ was also studied. It is observed that the extracted $D_{\mathrm{ it}}$ of $6\times 10^{11}$ cm $^{-2}$ eV $^{-1}$ for the sample with no surface treatment is lower than hydrofluoric and hydrochloric acid treated samples. Low $D_{\mathrm{ it}}$ sample shows narrow peak in the conductance method, suggesting a smooth interface. The extracted low $D_{\mathrm{ it}}$ makes ALD SiO2 an attractive candidate for future Ga2O3 power devices.

Defect termination on crystalline silicon surfaces by hydrogen for improvement in the passivation quality of catalytic chemical vapor-deposited SiNx and SiNx/P catalytic-doped layers

We investigate the role of hydrogen (H) in the improvement in the passivation quality of silicon nitride (SiNx) prepared by catalytic chemical vapor deposition (Cat-CVD) and Cat-CVD SiNx/phosphorus (P) Cat-doped layers on crystalline silicon (c-Si) by annealing. Both structures show promising passivation capabilities for c-Si with extremely low surface recombination velocity (SRV) on n-type c-Si. Defect termination by H is evaluated on the basis of defect density (Nd) determined by electron spin resonance (ESR) spectroscopy and interface state density (Dit) calculated by the Terman method. The two parameters are found to be drastically decreased by annealing after SiNx deposition. The calculated average Dit at midgap (Dit-average) is 2.2 × 1011 eV−1 cm−2 for the SiNx/P Cat-doped c-Si sample with a SRV of 2 cm/s, which is equivalent to 3.1 × 1011 eV−1 cm−2 for the SiNx/c-Si sample with a SRV of 5 cm/s after annealing. The results indicate that H atoms play a critical role in the reduction in Dit for SiNx/c-Si and SiNx/P Cat-doped c-Si, resulting in a drastic reduction in SRV by annealing.

Interface and electrical properties of ultra-thin HfO2 film grown by radio frequency sputtering

Interfacial composition and electrical properties of ultra-thin hafnium oxide (HfO2) films on p-type <100> Si substrate are reported. Hafnium oxide (HfO2) thin films are prepared using radio-frequency sputtering method and subsequently annealed at different temperature. The effect of post-deposition annealing on the interfacial and chemical state of HfO2/Si gate stack has been characterised by means of X-ray reflectivity and X-ray photoelectron spectroscopy studies. Peaks of X-ray photoelectron spectroscopy spectra at 530.50 and 532.25eV originate from Hf–O–Si bond illustrated the creation of Hf-silicate based interfacial layer at the high-k/Si interface. X-ray reflectivity fitting result also corroborated the formation of Hf silicate interfacial layer. Capacitance-voltage measurements revealed insignificant hysteresis in case of film annealed at 600°C. Interface trap density has been extracted using Terman method and is found to be 3.18×10−11cm−2eV−1 at −1.0V. Minimum equivalent oxide thickness (EOT) of 1.3nm was obtained for the film annealed at 600°C. The gate leakage current density of the HfO2 film annealed at 600°C is 1.5×10−5A/cm2 at a bias voltage of −2V.

The influence of electron energy quantization in a space-charge region on the accumulation capacitance of InAs metal-oxide-semiconductor capacitors

The influence of electron energy quantization in a space-charge region on the accumulation capacitance of the InAs-based metal-oxide-semiconductor capacitors (MOSCAPs) has been investigated by modeling and comparison with the experimental data from Au/anodic layer(4-20 nm)/n-InAs(111)A MOSCAPs. The accumulation capacitance for MOSCAPs has been calculated by the solution of Poisson equation with different assumptions and the self-consistent solution of Schrödinger and Poisson equations with quantization taken into account. It was shown that the quantization during the MOSCAPs accumulation capacitance calculations should be taken into consideration for the correct interface states density determination by Terman method and the evaluation of gate dielectric thickness from capacitance-voltage measurements.

Effect of alloying temperature on the capacitance–voltage and current–voltage characteristics of low‐pressure chemical vapor deposition SiNx/n‐GaN MIS structures

The low‐pressure chemical vapor deposition (LPCVD)‐SiNx layer is deposited prior to the ohmic alloying as the passivation layer and gate dielectric layer in GaN device fabrication. The effect of alloying temperature on the LPCVD‐SiNx/GaN interface and LPCVD‐SiNx dielectric film is evaluated by the capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The C–V analysis by frequency‐dependent method and Terman method shows that the higher density of interface states occurs at the higher alloying temperature, while I–V analysis indicates that the higher alloying temperature can lead to smaller current density with slightly deeper traps for Poole–Frenkel conduction. The hydrogen‐related bonds may be the cause and affects the interfacial properties of LPCVD‐SiNx/GaN as well as the electrical properties of LPCVD‐SiNx film.

Improving Interface Quality of 4H-SiC MOS Devices with High Temperature Oxidation Process in Mass Produce Furnace

A high-temperature process is used to enhance the COx desorption rate to reduce trap density in SiC/SiO2 interface for SiC MOSFETs. Interface state density as measured by Terman method and C-ψs method for the oxidation processes at a high temperature of 1350°C show significant improvement compared to traditional Si thermal oxidation temperature of 1200°C. The higher oxidation temperature led to a much faster growth rate and some observable hysteresis in the CV curves, which could be due to electron trap and can be resolved by NOx post oxidation anneal (POA).

Barrier lowering and leakage current reduction in Ni-AlGaN/GaN Schottky diodes with an oxygen-treated GaN cap layer

We report on the effect of oxygen annealing for GaN surface on the Schottky barrier configuration and leakage current in Ni-AlGaN/GaN Schottky barrier diodes. After oxygen annealing, their turn-on voltage and reverse-bias leakage current characteristics are significantly improved due to a reduction in the Schottky barrier height (SBH) and suppression in the surface states respectively. Interface state density extracted from the Terman method was reduced by 2 orders of magnitude. X-ray photoelectron spectroscopy measurements show that the oxygen annealing induces Ga2O3 on the GaN surface. The formation of Ga2O3 reduces the interface state density as well as lowers the SBH through the modification of hybridized metal induced gap states.

Extraction of interface state density in oxide/III–V gate stacks

Extracted interface trap densities (Dit) in the oxide/III–V gate stacks vary strongly with the utilized measurement procedures and values of device parameters used in the extraction analysis. Such Dit dependency on both selected procedures and parameters compromises unambiguous extraction of energy distributions of defects affecting device characteristics. To overcome this uncertainty, we propose an extraction approach, which combines the essential features of the high–low method and Terman method, allowing us to self-consistently determine Dit distribution along with values of the critical device parameters, effective oxide thickness (EOT) and substrate doping density (Nd).

Effects of recess process and surface treatment on the threshold voltage of GaN MOSFETs fabricated on a AlGaN/GaN heterostructure

GaN MOSFETs on a AlGaN/GaN heterostructure with a recess gate were fabricated. The charges near the SiO2/GaN interface of the GaN MOSFETs with different etching conditions were evaluated. It was found that stronger bombardment damage in the dry process will bring more charges near the interface and finally make the threshold voltage of the device negative. Nitrogen plasma treatment and ammonia water (NH4OH) treatment were investigated to recover or remove the damaged layer in order to achieve an enhancement-mode (E-mode) device with positive threshold voltage on the dry-recessed semi-insulating (SI) GaN surface. The influence of these treatments on the interface state density was also characterized using the Terman method by using the GaN MOS capacitor. An E-mode GaN MOSFET with a maximum field-effect mobility of 148.1 cm2 V−1 s−1 and a MOS capacitor with an interface state density of 3 × 1011 cm−2 eV−1 were realized by the NH4OH treatment.

4H-silicon carbide-dielectric interface recombination analysis using free carrier absorption

In this paper, an alternative method to characterize the interface between 4H polytype of Silicon Carbide (4H-SiC) and passivating dielectric layers is established. The studies are made on dielectric-semiconductor test structures using Al2O3 as dielectric on 4H-SiC n-type epitaxial layers. Samples with different pre- and post-dielectric deposition preparations have been fabricated on epilayers of varying thicknesses. Effective lifetimes (τeff) of all the samples were measured by an optical pump-probe method utilizing free carrier absorption (FCA) to analyse the influence of the 4H-SiC/dielectric interface on charge carrier recombination. The relative contribution to τeff from the surfaces increases with decreasing epilayer thickness, and by analysing the data in combination with numerical modelling, it is possible to extract values of the surface recombination velocities (SRVs) for interfaces prepared in different ways. For instance, it is found that SRV for a standard cleaning procedure is 2 × 106 cm/s compared to a more elaborate RCA process, yielding a more than 50 times lower value of 3.5 × 104 cm/s. Furthermore, the density of interface traps (Dit) is extracted from capacitance-voltage (CV) measurements using the Terman method and a comparison is made between the SRV extracted from FCA measurements and Dits extracted from CV measurements on the same structures fabricated with metal contacts. It is observed that the SRV increase scales linearly with the increase in Dit. The strong qualitative correlation between FCA and CV data shows that FCA is a useful characterization technique, which can also yield more quantitative information about the charge carrier dynamics at the interface.

(Invited) Reducing EOT and Interface Trap Densities of High-k/III-V Gate Stacks

In0.53Ga0.47Asis currently being investigated as a channel material for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) for post-Si complementary CMOS applications. A major obstacle facing the development of MOSFETs with In0.53Ga0.47As channels is the high density of traps (Dit ) at the gate dielectric/III-V semiconductor interface. Interface trap densities are relatively straightforward to detect for In0.53Ga0.47As channels, because of its narrow band gap (0.75 eV); at room temperature they cause, for example, a frequency-dependent hump in the depletion region of capacitance-voltage (CV) characteristics, and peaks in normalized conductance maps. To reduce the large trap densities at interfaces between In0.53Ga0.47As and the gate dielectric (typically Al2O3 or HfO2) various surface preparation and passivation methods are currently being investigated in the literature. In this presentation, we will discuss the development of novel, in-situ surface preparation methods prior to atomic layer deposition (ALD) of gate dielectrics on In0.53Ga0.47As, and their influence on EOT scaling and Dit . The surface treatments employed here consist of in-situ cleaning involving alternating cycles of nitrogen plasma and trimethylaluminum (TMA) pulses prior to ALD of different dielectrics. We demonstrate metal-oxide-semiconductor capacitors (MOSCAPs) with HfO2 and HfO2/Al2O3 dielectrics with very low Dit (in the low 1012 cm-2 eV-1 range) that can be scaled to sub-nm EOT (accumulation capacitances exceeding 3 µF/cm2 at 1 MHz for n-In0.53Ga0.47As). To elucidate the mechanisms by which these novel surface preparation methods allow for reducing both Dit and EOT, we present complementary studies of the MOSCAP electrical properties (GV and CV), interface chemistry and surface morphology using XPS, TEM, SIMS and atom probe tomography, as a function of surface cleaning parameters. Because the surface preparation methods employed here allow for both low Dit and low EOT, well behaved gate stacks can also be obtained on p-In0.53Ga0.47As channels. Comparisons of the CV results for p- and n-channels with calculated CV allow for analysis of the limitations of currently employed methods of Dit analysis, such as the Terman method.

Influence of Series Resistance and Interface State Density on Electrical Characteristics of Ru/Ni/n-GaN Schottky structure

We have investigated the electrical properties of Ru/Ni/n-GaN Schottky structure using current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height (Fbo) and ideality factor (n) of Ru/Ni/n-GaN Schottky structure are found to be 0.66 eV and 1.44, respectively. The Fbo and the series resistance (RS) obtained from Cheung's method are compared with modified Norde's method, and it is seen that there is a good agreement with each other. The energy distribution of interface state density (NSS) is determined from the I-V measurements by taking into account the bias dependence of the effective barrier height. Further, the interface state density NSS as determined by Terman's method is found to be 2.14´10 12 cm -2 eV -1 for the Ru/Ni/n-GaN diode. Results show that the interface state density and series resistance has a significant effect on the electrical characteristics of studied diode.

Extraction of interface state density at SiO2/SiC interfaces based on impedance measurements with different temperatures

We quantitatively compare density of interface states (Dit) at 4H-SiC/SiO2 interfaces evaluated by the high–low method, the Terman method and the conductance method. The results show that Dit evaluated from the Terman method exhibits the strong measurement temperature dependence and is lower than that evaluated from the other methods, indicating that it is difficult to accurately evaluate Dit in a wide range of surface potential by the Terman method. On the other hand, it is found that Dit by the conductance method is basically in agreement with Dit by the high–low method and is slightly higher near the conduction band edge. This result indicates that the conductance measurement allows us to detect interface states with shorter time constant and with surface potential closer to the band edge. Also, Dit by the conductance method has no measurement temperature dependence, confirming us the accuracy. These results suggest that the conductance method can detect more interface states than the Terman method and high–low method.

Interfacial characteristics of Al/Al2O3/ZnO/n-GaAs MOS capacitor

The interfacial characteristics of Al/Al2O3/ZnO/n-GaAs metal—oxide—semiconductor (MOS) capacitor are investigated. The results measured by X-ray photoelectron spectroscopy (XPS) and high-resolution transmission electron microscopy (HRTEM) show that the presence of ZnO can effectively suppress the formations of oxides at the interface between the GaAs and gate dielectric and gain smooth interface. The ZnO-passivated GaAs MOS capacitor exhibits a very small hysteresis and frequency dispersion. Using the Terman method, the interface trap density is extracted from C–V curves. It is found that the ZnO layer can effectively improve the interface quality

Effect of annealing on the electronic parameters of Au/poly(ethylmethacrylate)/n-InP Schottky diode with organic interlayer

A thin poly(ethylmethacrylate) (PEMA) layer is deposited on n-InP as an interlayer for electronic modification of Au/n-InP Schottky structure. The electrical properties of Au/PEMA/n-InP Schottky diode have been investigated by current–voltage (I–V) and capacitance–voltage (C–V) measurements at different annealing temperatures. Experimental results show that Au/PEMA/n-InP structure exhibit a good rectifying behavior. An effective barrier height as high as 0.83 eV (I–V) and 1.09 eV (C–V) is achieved for the Au/PEMA/n-InP Schottky structure after annealing at 150 °C compared to the as-deposited and annealed at 100 and 200 °C. Modified Norde's functions and Cheung method are also employed to calculate the barrier height, series resistance and ideality factors. Results show that the barrier height increases upon annealing at 150 °C and then slightly decreases after annealing at 200 °C. The PEMA layer increases the effective barrier height of the structure as this layer creates a physical barrier between the Au metal and the n-InP. Terman's method is used to determine the interface state density and it is found to be 5.141 × 1012 and 4.660 × 1012 cm−2 eV−1 for the as-deposited and 200 °C annealed Au/PEMA/n-InP Schottky diodes. Finally, it is observed that the Schottky diode parameters change with increasing annealing temperature.

Re-examination of the extraction of MOS interface-state density by C–V stretchout and conductance methods

The extraction of interface-state density by the stretchout of MOS C–V (Terman method) is re-examined. It is shown that the typical 1 MHz frequency is not nearly high enough to get rid of the interface-state contribution to the MOS capacitance. When coupled with a bias-dependent trap time constant (τ), this could result in a severe underestimate of the interface-state density. The ‘conductance method’, on the other hand, can extract the interface-state density accurately if the MOS is biased in depletion and if ω ∼ 1/τ is within the measured frequency range. Also, the robustness of the conductance method subject to errors in the estimated oxide capacitance, as well as its extendibility into regions of weak and strong inversion is investigated. Furthermore, two cases of false peaks under the conductance method are mentioned: the first due to a small tunneling leakage in thin oxides and the second due to a high density of bulk-oxide traps.