(Invited) Reducing EOT and Interface Trap Densities of High-k/III-V Gate Stacks

Abstract

In0.53Ga0.47Asis currently being investigated as a channel material for III-V metal-oxide-semiconductor field effect transistors (MOSFETs) for post-Si complementary CMOS applications. A major obstacle facing the development of MOSFETs with In0.53Ga0.47As channels is the high density of traps (Dit ) at the gate dielectric/III-V semiconductor interface. Interface trap densities are relatively straightforward to detect for In0.53Ga0.47As channels, because of its narrow band gap (0.75 eV); at room temperature they cause, for example, a frequency-dependent hump in the depletion region of capacitance-voltage (CV) characteristics, and peaks in normalized conductance maps. To reduce the large trap densities at interfaces between In0.53Ga0.47As and the gate dielectric (typically Al2O3 or HfO2) various surface preparation and passivation methods are currently being investigated in the literature. In this presentation, we will discuss the development of novel, in-situ surface preparation methods prior to atomic layer deposition (ALD) of gate dielectrics on In0.53Ga0.47As, and their influence on EOT scaling and Dit . The surface treatments employed here consist of in-situ cleaning involving alternating cycles of nitrogen plasma and trimethylaluminum (TMA) pulses prior to ALD of different dielectrics. We demonstrate metal-oxide-semiconductor capacitors (MOSCAPs) with HfO2 and HfO2/Al2O3 dielectrics with very low Dit (in the low 1012 cm-2 eV-1 range) that can be scaled to sub-nm EOT (accumulation capacitances exceeding 3 µF/cm2 at 1 MHz for n-In0.53Ga0.47As). To elucidate the mechanisms by which these novel surface preparation methods allow for reducing both Dit and EOT, we present complementary studies of the MOSCAP electrical properties (GV and CV), interface chemistry and surface morphology using XPS, TEM, SIMS and atom probe tomography, as a function of surface cleaning parameters. Because the surface preparation methods employed here allow for both low Dit and low EOT, well behaved gate stacks can also be obtained on p-In0.53Ga0.47As channels. Comparisons of the CV results for p- and n-channels with calculated CV allow for analysis of the limitations of currently employed methods of Dit analysis, such as the Terman method.