Tensile Contact Etch Stop Layer Research Articles

The Impacts of Cesl and STI Mechanical Stress Effect on Device Performance for UTBB FD-SOI MOSFET

The effects of a stressor nitride oxide layer on device performance and reliability are investigated. Impact of tensile and compressive stress contact etch stop layer (CESL) and shallow trench isolation(STI) mechanical stress on performance and mobility enhancement of <110>/(100) Fully Depleted Sillicon On Insulator(FD-SOI) MOSFETs (ultrathin film, short length, metal-gate/high-K stack, thin BOX) were studied in detail. By thoroughly evaluating their impact on current, mobility, and threshold voltage, the performance gain of CESL is quantified at CMOS with mobility enhancement identified as the major source. It is also experimentally demonstrated that advantageous Length of Diffusion. In the Compress CESL(cCESL) strain , PMOS show 34% performance enhancement with LOD increase 0.1nm to 1um. On the ather hand, NMOS show 3.41%. In the Tensile CESL(tCESL) strain , NMOS show 11.72% performance enhancement with same LOD condition. On the ather hand , PMOS has changed 3.72%.

Strain Modification of PECVD Nitride By Plasma Immersion Ion Implantation Processes

Strain engineering was introduced in the microelectronics industry almost two decades ago to improve the carrier mobility due to the modification of the band structures in the Metal Oxide Field Effect Transistor (MOSFET) channel [1, 2]. One method to induce local strain in the transistor channel consists in using Contact Etch Stop Layer (CESL) as stress liner. In order to improve both n-MOS and p-MOS performance, the use of a dual stressed liner (DSL) integration is a solution that combines tensile and compressive films on the same wafer [3]. However, the poor mechanical stability of the compressive PECVD nitride layer when exposed to a high thermal budget, combined with the increased integration complexity, limits the interest of the DSL approach. An alternative solution to tackle these limitations consists in locally transforming the tensile CESL nitride into compressive by Plasma Immersion Ion Implantation (PIII).For this study, PIII processes were performed on 300mm silicon bare wafers capped with a 35nm tensile PECVD nitride. Various species (Hydrogen (H), Helium (He) and Nitrogen (N)) implanted at various acceleration voltages (increasing from 1 to 6 in arbitrary units) and doses (A<B<C) were studied using a Pulsion® tool manufactured by IBS. After these processes, the samples were characterized by various techniques such as ellipsometry, bow measurement, Scanning Electron Microscopy observations, Secondary Ion Mass Spectrometry or FTIR analysis.The stress of the various nitride layers was determined by the Stoney formula, using the curvature measurements and the layer thickness determined by ellipsometry, assuming the shift of the bow results only from the change in nitride stress. Results show that, for all the species studied, the PIII process provides the capability to change the nitride stress from initially tensile to neutral or even compressive when increasing the dose and the acceleration voltage (Fig.1). The largest stress modifications were achieved with nitrogen and hydrogen. For the latter however, the blistering of the nitride layer is observed for the highest doses due to an excessive hydrogen concentration, which is prohibitive for further process integration. By using helium PIII process, the stress change is less for identical process parameters (Fig.1), leading to a neutrally stressed nitride layer. Increasing the helium dose to modify the nitride stress further leads to a consumption of the layer, which limits the use of helium only to the reversal of the mechanical stress.To verify that the stress change will remain during the subsequent process steps, curvature measurements were performed after a consequent thermal budget, equivalent to PMD deposition, applied after the PIII processes. The results show no significant change of the stress level.We demonstrated the capability of PIII processes to turn a tensile CESL nitride layer into a compressive one in a reasonable processing time thanks to the high beam current achievable with PIII process, without any consumption of the layer and without the need of a post implantation thermal treatment. Complementary analysis are on-going to fully characterize the impact of each species on the CESL physicochemical properties and thereby understand its stress evolution. Thanks to these encouraging results, the most promising conditions of all the species mentioned above will be experimented on electrical structures to quantify the related static performance gain.This project (OCEAN12) has received funding from the ECSEL Joint Undertaking (JU) under grant agreement No 783127. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and France, Germany, Austria, Portugal, Greece, Spain, Poland.[1] S. Ito, et al, “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, 2000 IEDM Tech. Dig., p. 247[2] T.K. Kang, IEEE ELECTRON DEVICE LETTERS, VOL. 33, NO. 6, JUNE 2012.[3] H. S. Yang, “Dual Stress Liner for High Performance sub-45nm Gate Length SO1 CMOS Manufacturing”, IEDM 2004 Figure 1

Comprehensive Stress Effect of Thin Coatings and Silicon-Carbon Lattice Mismatch on Nano-Scaled Transistors with Protruding Poly Gate.

Enhancing the mobility in metal-oxide-semiconductor field-effect transistors (MOSFETs) with narrow channel widths is highly sensitive to the stress effects of Si channel when related advanced strain engineering is introduced and is compatible with semiconductor processes. In practice, layouts have significant effect on the device performance, especially for the protruding gate width on shallow trench isolation structures. The geometric parameter is investigated by systematically analysing an n-channel MOSFET composed of silicon-carbon (SiC) stressors embedded in the source and drain (S/D) regions and a tensile contact etch stop layer (CESL) using three-dimensional finite element simulation. Tensile CESL (1.1 GPa) and a SiC S/D stressor with a carbon mole fraction of 1.65% are loaded on the structure. The difference in the interactive percentages between the mechanical bending effect of the CESL from the top of the poly gate and the downward force of the CESL adjacent to the spacer sidewall of the gate occurs when the protruding gate width is increased. Results indicate that mobility was highly enhanced by approximately 72.5% at a width of approximately 0.2 μm. The mechanical bending effect becomes dominant when the gate width is more than 0.2 μm. Consequently, the mobility gain decays and consequently converges toward a constant.

Magnifying the effective intrinsic stress of surface coating on the performance of nano-scaled Ge-based high-k/metal gate device through superficial layout designs

Scaling of dimensions for traditional Si-based metal oxide semiconductor field-effect transistors (MOSFETs) is limited. Thus, a promising transistor material and a corresponding fabricated process should be selected to improve the electrical performance of advanced nanodevices. According to the viewpoint of material survey, germanium-based MOSFET, which exhibits intrinsic high mobility, is considered a promising candidate for next-generation transistors. With the suitable introduction of stress-induced thin coating, such as silicon nitride contact etch stop layer (CESL), the electron mobility of devices can be further enhanced to compensate for the significant degeneration of lattice-mismatched stress resulting from rigorous dimensional shrinkage. The tensile CESL is commonly adopted to induce a biaxial tensile stress on the wide scope of n-type MOSFETs. However, the induced tensile stress that occurs along the transverse direction of a concerned device channel decreases the carrier mobility. Hence, this study proposes special layout designs with dummy gates placed on the transverse direction of the device channel. The effect of stress magnification from CESL coating on Ge-based n-type MOSFET is presented via a finite element analysis and a high-order piezoresistance model. Result shows that an enhanced carrier mobility gain of approximately 16.47% is obtained when a 50 nm-thick CESL with a tensile of 2.0 GPa is considered.

Effect of contact-etch-stop-layer and Si1-xGex channel mechanical properties on nano-scaled short channel NMOSFETs with dummy gate arrays

The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤20nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a+3.0GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100nm gate width.

Interaction influence of S/D GeSi lattice mismatch and stress gradient of CESL on nano-scaled strained nMOSFETs

The intrinsic stress of thin films has become an important resource as advanced strain engineering is introduced into nanoscaled semiconductor devices. The performance of preferred device infrastructure can be studied by estimating stress-induced mobility gain. However, traditional simulation approaches for device stress typically do not consider the eventual consequence of the stress gradient of strained thin films on nanoscaled transistor stress prediction. Thus, the actual operating characteristic of concerned devices can be easily misunderstood. To resolve this issue, this research presents a fabrication-oriented simulation methodology for device stress and combines it with a multi-layered deposition model for thin film. This study aims to explore stress-induced effects on the performance of a Ge-based testing vehicle for 20nmn-type metal-oxide-semiconductor field-effect transistors (nMOSFETs) with Ge1−xSix alloys embedded into the source/drain regions of the device. Intrinsic stress is introduced via a 1.0GPa tensile contact etch stop layer (CESL). Analysis results indicate that stress contours adjacent to the top of the device gate are different from those obtained using the conventional simulation method. Moreover, greater CESL stress passes through the spacer and reaches the device channel. Furthermore, a relationship between the stress components and piezoresistivity coefficients of the Ge material is adopted to estimate the width dependence of the Ge-based nMOSFET on its mobility gain. A maximum mobility gain of up to 60.87% is acquired from the estimated results, and a channel width of 200nm is preserved.

The effect of CESL and dummy poly gate for n-type MOSFETs with short Si0.75Ge0.25 channel

In this investigation, the n-channel metal–oxide–semiconductor file–effect transistor (MOSFET) with contact–etch–stop–layer (CESL) stressor, SiGe channel, and dummy poly gate is proposed. The simulated technique is utilized to explore the stress distribution of nMOSFET with the channel region induced by foregoing mechanical. We use ANSYS software, which is based on finite element analysis (FEA), to simulate the stress distribution in the channel region. The simulation results indicated the CESL and SiGe channel significantly affected the stress distribution within the channel region. The sources of loading are 1.1, 2, and 3 GPa tensile CESL (t-CESL) and a SiGe channel structure with 25% germanium (Ge) mole fraction. The effect of dummy poly gate is discussed, including the dummy poly gate number and various pitches of the dummy poly gate. The simulation results indicate that the pitch of the dummy poly gate substantially influences the number of dummy poly gates. The electron mobility enhancement in the inversion layer of n-channel MOSFET was discussed. Electron mobility enhancement was evaluated by piezoresistance coefficients. Hence, the percentages of improvement of electron mobility with different structural conditions were compared. The relationships between stress distribution in the channel and dummy poly gate layout could be understood clearly through systematic analysis.

Ge1 − xSix on Ge-based n-type metal–oxide semiconductor field-effect transistors by device simulation combined with high-order stress–piezoresistive relationships

The considerably high carrier mobility of Ge makes Ge-based channels a promising candidate for enhancing the performance of next-generation devices. The n-type metal–oxide semiconductor field-effect transistor (nMOSFET) is fabricated by introducing the epitaxial growth of high-quality Ge-rich Ge1−xSix alloys in source/drain (S/D) regions. However, the short channel effect is rarely considered in the performance analysis of Ge-based devices. In this study, the gate-width dependence of a 20nm Ge-based nMOSFET on electron mobility is investigated. This investigation uses simulated fabrication procedures combined with the relationship of the interaction between stress components and piezoresistive coefficients at high-order terms. Ge1−xSix alloys, namely, Ge0.96Si0.04, Ge0.93Si0.07, and Ge0.86Si0.14, are individually tested and embedded into the S/D region of the proposed device layout and are used in the model of stress estimation. Moreover, a 1.0GPa tensile contact etching stop layer (CESL) is induced to explore the effect of bi-axial stress on device geometry and subsequent mobility variation. Gate widths ranging from 30nm to 4μm are examined. Results show a significant change in stress when the width is <300nm. This phenomenon becomes notable when the Si in the Ge1−xSix alloy is increased. The stress contours of the Ge channel confirm the high stress components induced by the Ge0.86Si0.14 stressor within the device channel. Furthermore, the stresses (Syy) of the channel in the transverse direction become tensile when CESL is introduced. Furthermore, when pure S/D Ge1−xSix alloys are used, a maximum mobility gain of 28.6% occurs with an ~70nm gate width. A 58.4% increase in mobility gain is obtained when a 1.0GPa CESL is loaded. However, results indicate that gate width is extended to 200nm at this point.

A Resultant Stress Effect of Contact Etching Stop Layer and Geometrical Designs of Poly Gate on Nanoscaled nMOSFETs with a Si1-xGe(x) Channel.

In this research, an n-type metal-oxide-semiconductor field effect transistor (nMOSFET) device with a SiGe channel exerted by the combination of a contact etching stop layer (CESL) and silicon germanium (Si1-xGe(x)) channel stressors is proposed. To explore the foregoing mechanical effect on the stress distribution of nMOSFETs within the channel region, a process-oriented simulated technique is adopted for the concerned nMOSFET device. The loading sources are a 1.1 GPa tensile CESL (t-CESL) and a SiGe channel structure constructed with 0%, 22.5%, and 25%, germanium (Ge) mole fractions. The results of the simulation show that the stress components of the Si1-xGe(x) channel evidently increase when the Ge mole fraction within a Si1-xGe(x) layer is increased. A pulling force exerted on the protruding gate structure by the CESL layer that causes dominant bending deformation and channel stress variation behaviors is a major reason for this phenomenon. Therefore, the degree of bending effect caused by the protruding gate structure is concluded as being the key to determining the trends and stress magnitudes of the Si1-xGe(x) device channel.

Simulation-based sensitivity estimation of the geometric effect of poly gates on nanoscale n-type metal-oxide-semiconductor field-effect transistors with silicon–carbon alloy

The mobility enhancement of metal-oxide-semiconductor field-effect transistors (MOSFETs) using narrow gate lengths and channel widths is sensitive to the stress effects of silicon channels related to advanced strain engineering. The layout pattern of MOSFETs significantly influences the device performance, particularly the protruding gate width on shallow trench isolation structures. This paper investigates the geometric construction of an n-channel MOSFET composed of silicon–carbon stressors embedded in source/drain regions. The stressors have a 1.65% carbon mole fraction and a 1.1GPa tensile contact etch stop layer. Finite element analysis and analysis of variance were used to determine the bending effect of protruding gate widths on the MOSFETs. Results show that the main variation parameters are channel lengths and protruding gate widths, which determine the improvement in device performance. These results can serve as guidelines of stress impacts for predicting the next-generation node technologies of layout patterns.

A Stress Concentration MOSFET Structure

A MOSFET using a stress concentration (SC) structure to enhance the channel stress in strained MOSFETs is proposed. The nMOSFETs with gate length varying from 15 to 350 nm are simulated to investigate the effects of SC. For devices strained by tensile contact etching stop layer, over 12% driving current improvement better than that of conventional strained devices has been achieved. The method for introducing SC is effective for both short-and long-channel device.

Impact of stress induced by stressors on hot carrier reliability of strained nMOSFETs

In this study, the nMOSFETs with contact-etch-stop-layer (CESL) stressor and SiGe channel have been fabricated with a modified 90 nm technology. The performance of nMOSFETs has been measured. And the hot carrier reliability of the SiGe-channeled nMOSFETs with various CESL nitride layers has also been extensively studied. In addition, the impact of stress induced by CESL stressor and SiGe-channel on hot-carrier reliability of the strained nMOSFETs has been analysed through experimental investigation. The shift in threshold voltage (Δ V th ) vs. stress time ( t ) under different stress temperatures was measured. Furthermore, according to the reliability results, both the interface states ( N it ) and oxide trapped charges ( N ot ) increased after hot-carrier stress. With regard to the hot-carrier reliability, for all stress conditions the degradation of strained nMOSFETs with compressive CESL stressor is more serious than the degradation of those with tensile CESL stressors. The nMOSFET devices with tensile CESL have better performance and hot-carrier reliability than those with compressive CESL. Moreover, it is suggested that the CESL-induced damages ( N it ) located at the interface between gate dielectric and underlying channel be responsible for the hot-carrier reliability.

Investigation of consequent process-induced stress for N-type metal oxide semiconductor field effect transistor with a sunken shallow trench isolation pattern

The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22nm and lower. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10% to 20% enhancement in carrier mobility.

Stress Impact of a Tensile Contact Etch Stop Layer on Nanoscale Strained NMOSFETs Embedded with a Silicon–Carbon Alloy Stressor

For the purpose of enhancing performance in NMOSFETs, inducing an ever increasing tensile stress along Si channel direction is beneficial through the use of advanced strained engineering. By means of the lattice mismatched SiC with different carbon mole fraction, integrated with tensile contact etch stop layer (CESL), the obtainment of significant mobility gain is expected. In the present research, the stress distribution in NMOSFETs with the combinations of Silicon-Carbon (SiC) stressor and tensile CESL is systematically studied by using three-dimensional (3D) finite element analysis (FEA). Width dependency in conjunction with different nanoscale gate length is also analyzed. The analysis results indicate that the stress impact of SiC stressor resulting from the stress component along channel direction on Si region dominates and tensile CESL could enhance this effect. Further important is that the vertical stress within NMOSFETs, is raised greatly due to tensile CESL through the examined range of gate widths, especially for narrower width. Therefore, the predicted results reveal excellent mobility gain through such strain engineering.

Effect of gate capping configurations and silicon-on-insulator thickness with external stresses on partially depleted metal-oxide-semiconductor field-effect transistors

Silicon nitride gate capping by contact etch-stop layer (CESL) was used in this study to induce high and low tensile and compressive stresses on 50-, 70-, and 90-nm-thick silicon-on-insulator (SOI) n-/p-metal-oxide-semiconductor field-effect transistors. The devices with thicker SOI show a higher interface state, particularly the highly strained devices, although they exhibit higher transconductance. The transconductances of different CESL configurations are sensitive to the tSOI effect, but the transconductances of different tSOI are less sensitive to external compressive stress compared with those of CESL configurations. The CESL-induced compressive devices show higher piezoresistive coefficients than the tensile CESL devices, yielding an external stress of up to about 45.7 MPa for both longitudinal and transverse configurations. This probably results from nonlinear stress-strain relations on the CESL-induced strained channel.

External Stresses on Tensile and Compressive Contact Etching Stop Layer SOI MOSFETs

A n-/p-SOI MOSFET capped with a standard 380 Å tensile contact etching stop layer (CESL) and a 700 Å compressive CESL and with SOI thicknesses of 500/700/900 Å were measured in this paper. Additionally, external uniaxial compressive stresses with both longitudinal and transverse directions up to 45.7 MPa were applied on the devices sitting on cut silicon bars. Temperature-induced threshold voltage shifts and input-referred voltage noise showed bigger depletion zones and higher noise in the device with compressive CESL. The measurement suggests that both SOI thickness and CESL type are critical for mobility enhancement or degradation of devices. The capped compressive CESL for n-/p-SOI MOSFETs demonstrated higher piezoresistive coefficient compared with tensile CESL under external uniaxial compressive stresses for both longitudinal and transverse configurations.

An Investigation of the Effect of Elastic Constants of Spacer in n-FETs CESL Stressor

The strained-Si approach from the contact etching stop layer (CESL) stressor with two kinds of Young's modulus spacer has been investigated. From the TSUPREM4 simulation of the CESL tensile stressor, the tensile channel stress induced by the SiN spacer material is found to be 60% more than that by the oxide spacer material. With the use of a tensile CESL stressor for the 90-nm n-FETs, an extra 10% enhancement in drive current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dsat</sub> was obtained in the device with a high Young's modulus (270-290 GPa) SiN spacer as compared with that with a low Young's modulus (66 GPa) SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> spacer. The electrical data are in good agreement with the prediction of the stress simulation.

Tensile CESL-induced strain dependence on impact ionization efficiency in nMOSFETs

Process-induced strain dependence of impact ionization efficiency (IIE) in nMOSFETs with a tensile contact etch stop layer (CESL) is presented for the first time. From the universal relationship between the IIE and the electric field in the pinch-off region, a difference in the IIE of nMOSFETs between without and with the tensile CESL is found. This result can be mainly attributed to the narrowing effect of the bandgap energy caused by the tensile CESL-induced strain into the channel, i.e., the reduced threshold energy for impact ionization. In addition, the wafer-bending experiments can further provide strong evidence for the bandgap energy narrowing. It means that the IIE measurement could serve as a reliable monitor of the process-induced strain into the channel.