Ge1 − xSix on Ge-based n-type metal–oxide semiconductor field-effect transistors by device simulation combined with high-order stress–piezoresistive relationships

Abstract

The considerably high carrier mobility of Ge makes Ge-based channels a promising candidate for enhancing the performance of next-generation devices. The n-type metal–oxide semiconductor field-effect transistor (nMOSFET) is fabricated by introducing the epitaxial growth of high-quality Ge-rich Ge1−xSix alloys in source/drain (S/D) regions. However, the short channel effect is rarely considered in the performance analysis of Ge-based devices. In this study, the gate-width dependence of a 20nm Ge-based nMOSFET on electron mobility is investigated. This investigation uses simulated fabrication procedures combined with the relationship of the interaction between stress components and piezoresistive coefficients at high-order terms. Ge1−xSix alloys, namely, Ge0.96Si0.04, Ge0.93Si0.07, and Ge0.86Si0.14, are individually tested and embedded into the S/D region of the proposed device layout and are used in the model of stress estimation. Moreover, a 1.0GPa tensile contact etching stop layer (CESL) is induced to explore the effect of bi-axial stress on device geometry and subsequent mobility variation. Gate widths ranging from 30nm to 4μm are examined. Results show a significant change in stress when the width is <300nm. This phenomenon becomes notable when the Si in the Ge1−xSix alloy is increased. The stress contours of the Ge channel confirm the high stress components induced by the Ge0.86Si0.14 stressor within the device channel. Furthermore, the stresses (Syy) of the channel in the transverse direction become tensile when CESL is introduced. Furthermore, when pure S/D Ge1−xSix alloys are used, a maximum mobility gain of 28.6% occurs with an ~70nm gate width. A 58.4% increase in mobility gain is obtained when a 1.0GPa CESL is loaded. However, results indicate that gate width is extended to 200nm at this point.