Temperature Polysilicon Thin Film Research Articles

P‐15.4: A newly Integrated Ambient Light sensor with full in‐cell structure

In this paper, we present a novel integrated light‐dependent sensor which can be used to detect the illuminance of the ambient light. Based on the low temperature polysilicon (LTPS) thin film transistor (TFT) process and photosensitivity of a‐Si, the sensor can realize 0‐10K lux of the monitor range and 0.5 lux/step. It saves more space for terminal devices which will also facilitates the full screen display.

A Self-Refreshing Memory-in-Pixel Comprising Low Temperature Poly-Silicon and Oxide TFTs for 3-Bit Liquid Crystal Displays

In this letter, a self-refreshing multi-level memory-in-pixel (MIP) circuit for liquid crystal display (LCD) comprising low temperature poly-silicon and oxide (LTPO) thin film transistors (TFTs) is proposed. Since the proposed MIP circuit features self-refreshing without embedding frame memory, power consumption can be minimized when displaying a still image. Measurement results verify that the proposed circuit successfully enables a 3-bit grayscale. The LCD employing the proposed MIP circuit consumes only 1.22 % of power compared with a conventional LCD when displaying a still image. Thus, the proposed multi-level MIP circuit is expected to enable a low-power LCD featuring higher color depth with a simple structure.

Effect of NBTI on the Electrical Characteristics and Trap States of Low Temperature Poly-silicon Thin Film Transistor

Polysilicon thin film transistors have broad application prospects in high-performance flat panel displays and flexible wearable devices due to their high carrier mobility and good stability. However, due to process conditions and other reasons, there are traps inside, and under some electrical stress conditions, its electrical properties will degrade. Here we report the changes in electrical characteristics of p-type polysilicon thin film transistors with stress time at a negative gate voltage of -20V and a temperature of 60°C. It is obtained that the transfer characteristics of the p-type polysilicon thin film transistor move in the negative direction with the increase of Negative Bias Temperature Instability time, and with the increase of SS degradation, and the total trap state inside it is calculated by SS, which provides a theoretical basis for improving the reliability of the device.

Degradation modeling with spatial mapping method in low temperature poly silicon thin film transistor aged off-state bias

We conducted experimental and quantitative studies on the effects of off-state bias stress of the p-type polycrystalline silicon thin film transistors, and present a degradation model using spatial mapping simulations. In the off-state bias stress condition, the gate induced drain leakage current (GIDL) is determined by the gate and drain voltage (Vgd), and the gate bias stress above a certain bias is accompanied by a change in Vth. The spatial distributions of the electric field and the electron concentration are considered as degradation factors, and are used in the equations for defect creation (DC) and the charge trapping (CT) model. We had to implement different forms of the aging model in the two regions: 1) CT in the poly-Si/SiOX interface, and 2) DC in the channel bulk. Finally, our degradation model allows us to analyze how the GIDL current decreases with various aging conditions, and provides a quantitative relationship between the amount of charge trapping and the amount of defect creation.

A Memory-in-Pixel Circuit for Low-Power Liquid Crystal Displays With Low Temperature Poly-Silicon and Oxide Thin Film Transistors

We propose a new memory-in-pixel (MIP) circuit using low temperature poly-silicon and oxide (LTPO) thin film transistors (TFTs) to achieve the high reliability as well as low power consumption. The proposed pixel circuit can greatly reduce the frame frequency due to extremely low leakage current of oxide TFTs. Moreover, the driving TFTs of the circuit can be stable under continuous stress for a long period of time because low temperature poly-silicon TFTs show high reliability. The pixel is driven directly by applying black or white voltage so that a flicker can be minimized. Fabricated circuit successfully verifies the circuit performance under the frame frequency of 1/60 Hz and the polarity inversion frequency of 0.5 Hz. Therefore, we expect that our proposed MIP circuit can provide flicker-free liquid crystal displays featuring low power consumption as well as high reliability.

Thermal conductive hybrid polyimide with ultrahigh heat resistance, excellent mechanical properties and low coefficient of thermal expansion

It is a great challenge to fabricate flexible substrate materials with an ultrahigh heat resistance, low coefficient of thermal expansion (CTE) and high thermal conductivity, which is required to process low temperature poly-silicon thin film transistors in active matrix organic light-emitting-diode devices. Despite the development of new monomers is also possible to simultaneously improve the heat resistance and dimensional stability of polyimides, the space for improvement is limited and the cost is greatly increased. Traditional polymer nanocomposites can increase the glass transition temperature (Tg) and reduce the CTE, but they cause a significant drop in mechanical properties. Herein, an amino-functionalized boron nitride nanosheets (BNNS_APS) hybrid polyimide (PI) was prepared by in situ polymerization. The hybrid PI exhibited ultrahigh heat resistance, excellent thermal conductivity, low CTE and good mechanical properties with 1 wt% BNNS_APS doping. The Tg of the hybrid PI was improved up to 473 °C and the thermal conductivity was increased by 100% compared with pure PI. The CTE was less than 7 ppm/K, and the tensile strength and elongation at break increased to 336 MPa and 16.6%, respectively. These results are attributed to the good dispersion of BNNS_APS in the PI matrix and the strong interactions between the BNNS_APS and PI chains. The mechanism was proposed and discussed in detail.

P‐1.6: Highly Stable LTPS TFT on Si Wafer under High Current Stress

In this work, we report low temperature polysilicon (LTPS) thin film transistor (TFT) on the glass substrate and silicon wafer substrate by using blue laser annealing (BLA). The TFTs evaluated the high current stress (HCS) at the gate voltage (VGS) ‐20 V and the drain voltage (VDS) ‐6 V for 1 h. As a result, the performance of TFT on the silicon wafer shows excellent stability of HCS compared to that of TFT on the glass substrate. Also, viewed in its entirety, the break down current (IBK) of glass sample smaller than silicon wafer sample at breakdown voltage.

Solution Based Al2O3 Gate Insulator for Low Temperature Poly Silicon TFT

Solution based insulator was applied for low temperature poly silicon thin film transistor (TFT). Solution process has several advantages of low cost, short process time and no plasma damage. Several kinds of solution-based materials were tested for TFTs, including organic insulators. In this paper, we present the aluminum oxide gate insulator based on solution process. For poly-silicon process, amorphous silicon is deposited by sputtering and crystallized by blue laser diode annealing. After pattering of the poly-silicon, gate insulator of Al2O3 was formed by solution process. After gate insulator etching, source/drain metal was deposited and patterned. Low temperature process below 400℃ for all TFT fabrication with low cost has been developed and reported. The insulator was characterized with the metal-insulator-semiconductor (MIS) structure. 0.8 M Al(NO3)39H2O solution with DMAC (Di-methyl-acetamide) was coated on the Si-wafer. The surface of silicon wafer was treated with oxygen plasma before coating to improve the adhesion. After spin-coating, it was baked at 150℃ for 5 min. It was annealed finally at 300℃ for 1 h. To improve the insulator performance, the multi coating was tested. After coating and baking, it was coated again. Figure 1 shows the I-V characteristics for the sample coated for three times. As the number of coating increased, leakage current was reduced and the break down voltage increased. Figure 1

The Oxide TFT with Solution Based Gate Insulator

Low temperature poly-Silicon (LTPS) thin film transistor (TFT) and Oxide TFT are developed for the better performance of the active matrix display. Recently, oxide TFT has been investigated intensively due to simple process and higher mobility than amorphous silicon TFT. Typical parameters of TFT are mobility, threshold voltage and On/Off ratio which are influenced by gate insulator. The widely used material for gate insulator is SiO2 which is rich in the earth and inexpensive. But vacuum equipments like the plasma enhanced chemical vapor deposition (PECVD) and the RF Magnetron sputter need large investment and maintenance cost than non-vacuum process. Oxide TFT of top gate structure reduces the parasitic capacitance between source-drain and gate metal. The plasma damage during deposition of gate insulator on an oxide active layer cause the defects which deteriorate TFT characteristics. However, the gate insulator by solution process reduces the defects by plasma process. SU-8 which is a negative photoresist (PR) has been being used widely in micro electro mechanical system (MEMS). It is constituted with octuple epoxy groups and includes photosensitize to react with UV light. The polymer network generated by cross-linking has mechanical and chemical stabilities and high electrical resistance. In this experiments, SU-8 was used for the gate insulator of the oxide TFT and investigated the effect of the SU-8 gate insulator on the oxide TFT. In this paper, we investigated the characteristics of gate insulator of SU-8 as changing UV exposure time to SU-8. SU-8 was coated by spin coating with 2000 rpm on a p-type Si wafer. After soft-bake for 1.5 min at 95˚C, UV of 365 nm was exposed at an energy of 320mJ/s. Exposure times were varied as 30s, 60s, 120s, and 240s. After UV exposure, hard bake was done for 20 min at 115˚C. An Al layer was deposited on SU-8, and electrical properties of the SU-8 were measured after post-annealing. Figure 1 shows the current densities of the SU-8 insulators for various exposure time from 30s to 240s. As shown in Fig. 1, the leakage currents decreased as the exposure time increased from 30s to 240s. For the gate insulator of the oxide TFT, the proper UV exposure is important. Figure 1

Flexible PVDF-TrFE pyroelectric sensor driven by polysilicon thin film transistor fabricated on ultra-thin polyimide substrate

In this work we present a flexible pyroelectric sensor composed by a PVDF-TrFE capacitor realized on ultra-thin polyimide film (5μm thick), integrated with a n-channel low temperature polysilicon thin film transistor also fabricated on ultra-thin polyimide (8μm thick). Exploiting a multi-foil approach, the pyroelectric capacitors and the transistors were attached one over the other reaching a final thickness of about 15μm. The bottom contact of the sensor capacitance was connected to the gate of the transistor by a silver ink, while, for bias and load resistances, we used external elements. The active sensor area was defined by a circular capacitor with a diameter of about 2mm. In order to enhance PVDF-TrFE pyroelectric properties, an external stepwise voltage was applied to the structure up to values of 160V at a temperature of about 80°C. The devices were then tested, at different working frequencies (up to 800Hz) under a specific infrared radiation provided by a He–Ne laser, with a wavelength of 632nm and maximum power of 5mW. An output signal of tens of millivolt was observed at 10Hz, exploiting the pre-amplification of polysilicon thin film transistor.

The low temperature polysilicon (LTPS) thin film MOS Schottky diode on glass substrate for low cost and high performance CO sensing applications

The Au/SnO 2/n-LTPS MOS Schottky diode prepared on a glass substrate for carbon monoxide (CO) sensing applications is studied. The n-LTPS (n-type low temperature polysilicon) is prepared by excimer laser annealing and PH 3 plasma treatment of an amorphous Si thin film on glass substrate. The developed Schottky diode exhibits a high relative response ratio of ∼546% to 100 ppm CO ambient under condition of 200 °C and −3 V bias. The response ratio is better than the reported SnO 2 based resistive type CO sensors of 100% and 37%, respectively on poly-alumina and glass substrates or comparable to 390% of Pt-AlGaN/GaN Schottky diode CO sensor. Thus, the Au/SnO 2/n-LTPS Schottky diode has the potential to develop a low cost high performance CO sensor.

Partially light-controlled imaging system based on High Temperature Poly-Silicon Thin Film Transistor-Liquid Crystal Display

A partially light-controlled imaging system is proposed as a novel device. It is used to improve the imaging quality at the illumination of 1.979 x 10(5)lx by means of mitigating image contrast. It consists of a High Temperature Poly-Silicon Thin Film Transistor-Liquid Crystal Display (HTPS TFT-LCD), which is set between the lens and CCD and is coupled with CCD by the optical fiber taper. The transmittance of pixelated LCD can be controlled by Field-Programmable Gate Array to realize the partially light-controlled and thus dynamic range of the imaging system can be extended. Samples of indoor objects and outdoor license plate are photographed by the prototype imaging system under strong light. The imaging results of this novel system are satisfactory with better restored details, compared with the photos taken by normal CCD camera (WAT-231S2) which uses aperture and shutter to control the overall light intensity.

An integrated driving circuit implemented with p-type LTPS TFTs for AMOLED

Based on the technology of low temperature poly silicon thin film transistors (poly-Si-TFTs), a novel p-type TFT AMOLED panel with self-scanned driving circuit is introduced in this paper. A shift register formed with novel p-type TFTs is proposed to realize the gate driver. A flip-latch cooperated with the shift register is designed to conduct the data writing. In order to verify the validity of the proposed design, the circuits are simulated with SILVACO TCAD tools, using the MODEL in which the parameters of LTPS TFTs were extracted from the LTPS TFTs made in our lab. The simulation results indicate that the circuit can fulfill the driving function.

Thermal dependence of low-frequency noise in polysilicon thin film transistors

Thermal dependence of low frequency noise in low temperature (≤ 600 °C) polysilicon thin film transistors is studied in devices biased from weak to moderate inversion and operating in the linear mode. Drain current noise spectral density, measured in the temperature range from 260 K to 310 K, is thermally activated following the Meyer Neldel rule. Analysis of the thermal activation of noise, supported by the theory of trapping/detrapping processes of carriers into oxide traps located close to the interface, leads to the calculation of the deep state interface distribution in function of the Meyer Neldel characteristic energy.

Electrical properties of ultra-thin oxynitrided layer using N 2O plasma in inductively coupled plasma chemical vapor deposition for non-volatile memory on glass

In this work, the silicon oxynitride layer was studied as a tunneling layer for non-volatile memory application by fabricating low temperature polysilicon thin film transistors on glass. Silicon wafers were oxynitrided by only nitrous oxide plasma under different radio frequency powers and plasma treatment times. Plasma oxynitridation was performed in RF plasma using inductively coupled plasma chemical vapor deposition. The X-ray energy dispersive spectroscopy was employed to analyze the atomic concentration ratio of nitrogen/oxygen in oxynitride layer. The oxynitrided layer formed under radio frequency power of 150 W and substrate temperature of 623 K was found to contain the atomic concentration ratio of nitrogen/oxygen as high as 1.57. The advantage of high nitrogen concentration in silicon oxide layer formed by using nitrous oxide plasma was investigated by capacitance–voltage measurement. The analysis of capacitance–voltage characteristics demonstrated that the ultra-thin oxynitride layers of 2 nm thickness formed by only nitrous oxide plasma have good properties as tunneling layer for non-volatile memory device.

High Efficiency Stacked Organic Light-Emitting Diodes Employing Li2O as a Connecting Layer

We demonstrate the high-efficiency stacked organic light-emitting diodes (OLEDs) introducing new connecting layers. In the green stacked OLEDs, the external efficiencies increase proportionally to the number of the stacked units without suffering the decrease in power efficiency. The current, power and external efficiencies at 0.5 mA/cm2 of the stacked OLED with six stacked units (6-stacked OLED) have reached 235 cd/A, 46.6 lm/W, and 65.8%, respectively. Furthermore, we have applied the connecting layers to a white stacked OLED and fabricated an active-matrix full-color display with a low temperature polysilicon thin film transistor backplane. In the device, the current efficiency of the white 2-stacked OLED is enhanced by a factor of 2.2. The initial luminance drop is significantly suppressed for the white 2-stacked OLED compared to 1-stacked OLED. The proposed white stacked OLED technology can be applied to a full-color display for a practical use.

High-Performance Low Temperature Poly-Silicon Thin Film Transistors Fabricated by Excimer Laser Irradiation with Bottom-Gate Scheme

In this work, high-performance low-temperature poly-Silicon bottom-gate TFTs with single grain boundary perpendicular to the current flow in the channel regions have been demonstrated. A lateral grain growth of 0.75 μm in length could be artificially grown via the super lateral growth phenomenon using excimer laser irradiation with the plateau structure. Consequently, bottom-gate TFTs made by this method exhibit higher field-effect-mobility, lower leakage current, steeper subthreshold slope, larger on/off current ratios and improved device uniformity owing to this location-manipulated lateral grains. In addition, it shows better reliability because of the smooth interface between gate dielectric and poly-Si channel films.

High-Performance Low Temperature Poly-Silicon Thin Film Transistors Fabricated by Excimer Laser Irradiation with Bottom-Gate Structure

not Available.

P-135: Fast Bend Transition of the Pi-Cell at Low Temperature

We have developed fast bend transition method of pi-cell in low temperature. This cell requires a transition of the liquid crystals (LC) from an initial splay state to bend transition before normal driving operation. This study analyzed the conditions under which this transition is generated in low temperature. Consequently, a method of fast bend transition by applying waveform that make the most of LC's dynamic response, using structure of top-gate electrode and surface alignment in Low Temperature Poly-Silicon (LTPS) Thin Film Transistor (TFT) cell was established.

Low frequency noise model in N-MOS transistors operating from sub-threshold to above-threshold regions

The drain current activation energy dependence on the gate voltage is first evaluated from temperature measurements in both low temperature (⩽600 °C) polysilicon thin film transistors and in crystalline silicon N-MOSFETs, operating from sub-threshold to above-threshold regions. The noise behaviour of these transistors is then described with a low frequency noise model based on the Meyer–Neldel drain current expression. This model is built on carrier fluctuations at the gate oxide/active layer interface and the corresponding defect density is then deduced. It suggests that these defects close to the interface, causing detrapping/trapping processes of carriers and fluctuations of the flat-band voltage, are mainly responsible for the low frequency noise in the two operating modes. Noise measurements on different N-MOS transistors are confronted to result from the presented model.