Temperature Humidity Bias Research Articles

Electrochemical Metallic Ion Migration Property of Multi-Layer Ceramic Capacitor for Car Electronics

As the use of electrical components in automobiles increases, the occurrence of electorchemical metallic ion migration (ECM), which is one of the causes of various failures in electrical components, is also increasing. Therefore, in this study, 1608 MLCC chip components were used for temperature-humidity-bias (THB) tests at 65℃/85%R.H., 65℃/95%R.H., and 85℃/85%R.H. Three types of THB tests were conducted for 2,934 h. For the THB test, voltages of 3.3, 12 and 24 V were applied, and real-time resistance of MLCCs were measured at every 40 mms intervals. During the ECM test, the ECM occurrence time was measured by monitoring the insulation resistance of between the electrode of MLCC under each THB test conditions. The failure criteria for ECM occurrence were 106 Ω or less, and the time when it occurred more than twice was judged as the ECM failure criteria. Based on the ECM occurrence time, the mean life time of ECM occurrence according to temperature, humidity and applied voltage conditions was derived through Weibull statistical analysis. Finally, we compared and analyzed the sensitivity of MLCC components to ECM generation under use environment of automotive electronics.

Reliability Investigations in Printed Electronic Assemblies

Aerosol-Jet Printing (AJP) technology is a popular additive manufacturing method for achieving complex net geometry with micron-level accuracy. This opens up new possibilities in fabrication of electronic assemblies in 3D curvilinear form factors. Therefore, it is vital to understand not only the performance of AJP printed electronics, but also their reliability under different kinds of life-cycle operational and environmental stresses. Electrochemical migration (ECM) under temperature-humidity-bias (THB) conditions can lead to dendritic growth, which can cause dielectric breakdown, leakage current, and unexpected short circuit. ECM propensity and life prediction models for THB conditions were studied for AJP printed coupons based on silver-nanoparticle (AgNP) inks. Cyclic thermo-mechanical fatigue was studied under accelerated temperature cycling testing and modeling. Failures were found to occur mostly at interconnect transition regions due to stress concentrations caused by sudden transitions in local architecture. Drop/Shock failures for extreme accelerations were studied using a high-G drop tower. Deformations were characterized using high-speed photography and transient finite element modeling was used to study high strain-rate failures. Acknowledgments: Jason Fleischer from the Laboratory for Physical Sciences, Harvey Tseng and Jian Yu from the Army Research Lab

Temperature-Humidity-Bias Testing and Life Prediction Modeling for Electrochemical Migration in Aerosol-Jet Printed Circuits

Abstract Aerosol-Jet Printing (AJP) technology, applied to the manufacturing of printed hybrid electronics (PHE) devices, has the capability to fabricate highly complex structures with resolution in the tens-of-microns scale, creating new possibilities for the fabrication of electronic devices and assemblies. The widespread use of AJP in fabricating PHE and package-level electronics necessitates a thorough assessment of not only the performance of AJP printed electronics but also their reliability under different kinds of life-cycle operational and environmental stresses. One important hindrance to the reliability and long-term performance of such AJP electronics is electrochemical migration (ECM). ECM is an important failure mechanism in electronics under temperature and humidity conditions because it can lead to conductive dendritic growth, which can cause dielectric breakdown, leakage current, and unexpected short circuits. In this paper, the ECM propensity in conductive traces printed with AJP process, using silver-nanoparticle (AgNP) based inks, was experimentally studied using temperature-humidity-bias (THB) testing of printed test coupons. Conductive dendritic growth with complex morphologies was observed under different levels of temperature, humidity, and electric bias in the THB experiments. Weibull statistics are used to quantify the failure data, along with the corresponding confidence bounds to capture the uncertainty of the Weibull distribution. A nonmonotonic relationship between time-to-failure and electric field strength was noticed. An empirical acceleration model for ECM is proposed, by combining the classical Peck's model with a quadratic polynomial dependence on electric field strength. This model provides good estimate of acceleration factors for use conditions where the temperature, humidity, and electrical field are within the tested range, but should be extrapolated with care beyond the tested range.

Development of high performance flip chip ball grid array (FCBGA) packages for automotive application processors

Automobiles have witnessed rapid proliferation of infotainment, driver assistance and autonomous driving features which have led to significant increase in semiconductor content per car. However, this has also required increased integration of device functionality to meet the new automotive requirements for in-vehicle networking, autonomous driving, infotainment, and sensor integration. Advance technology/packages are needed to provide ideal solutions for automotive grade reliability, high electrical performance, and multi-function integration for automotive application processors. To address these requirements, innovative packages including Flip Chip Ball Grid Array (FCBGA) are the potential solutions. In this study FCBGA packages are developed for automotive processor application and qualified for AEC2 qualification tier. To achieve higher performance and reliability, different package substrate materials such as core dielectric and build-up dielectric were evaluated. Mechanical modelling and simulation of package reliability and influence of key material properties such as coefficient of thermal expansion (CTE), modulus of elasticity (E) and glass transition temperature (Tg) was used to provide guidance for the selection of substrate and assembly materials. Developed packages met all the product performance requirements and passed package qual conditions of high temperature storage life (150°C, 500 hours), temperature cycling (-55 °C to 125 °C, 1000 cycles), temperature humidity bias (85 °C, 85% RH, 1000 hours) and board level temperature cycling (-40 °C to 125 °C, 1000 cycles).

High Temperature Reverse Bias (HTRB) & Temperature Humidity Bias (THB) Reliability Failure Mechanisms and Improvements in Trench Power MOSFET and IGBT

High Temperature Reverse Bias (HTRB) reliability failure is found to be caused by huge amount of undesirable hydrogen proton (H+) ions from packaging resin or external environment, while Temperature Humidity Bias (THB) reliability failure is known to be caused by moisture accumulation. A commonly known method of improving HTRB is by increasing phosphorus concentration in the PMD layer to enhance device gettering capability against H+. However, this is usually achieved at the expense of THB reliability as excessive phosphorus on the PMD surface gives rise to moisture accumulation and caused THB failure. In this paper, we performed a series of experiments to uncover two elements in PMD that are responsible to getter H+, which are Phosphorus-Oxygen-Hole-Center (POHC) and dangling bonds. We also discussed 2 possible ways to boost these H+ gettering elements to improve HTRB reliability without the adverse impact on THB reliability: Utilization of Plasma Enhanced Chemical Vapor Deposition (PECVD) Phospho-Tetraethyl-Orthosilicate (PTEOS) in PMD layer to replace the commonly used Atmospheric Pressure Chemical Vapor Deposition (APCVD) or Sub Atmospheric Chemical Vapor Deposition (SACVD) Boro-Phospho-Tetraethyl-Orthosilicate (BPTEOS) and the introduction of Tetraethyl-Orthosilicate (TEOS) capping layer on PMD layer. Both methods have proven to greatly alleviate HTRB and THB reliability marginality problems.

High-Voltage Temperature Humidity Bias Test (HV-THB): Overview of Current Test Methodologies and Reliability Performances

The high voltage temperature humidity bias test (HV-THB) has become increasingly popular for evaluating the performances of power semiconductor devices. Given the new challenges of the power semiconductor industry, several applications and devices need to be designed to withstand harsh environments during working operations, with a remarkable focus on high-humidity conditions. The HV-THB test allows one to activate and study different failure mechanisms which were not highlighted by the standard low voltage THB test, enabling new designs in several energy conversion fields, such as energy harvesting, industry and automotive applications. After a brief introduction of current test standards, this work goes through the current methodologies and state-of-the-art of the HV-THB test. The following sections are then dedicated to the knowledge about the failure mechanisms and the models for accelerated testing. Eventually, there is a section devoted to the main passivation materials in order to understand their effects on the HV-THB capabilities of the devices.

Surface modification of thermoplastics by low-pressure microwave O2 plasma treatment for enhancement of the adhesion of the interface box/encapsulating resin and the influence on film capacitors operating under extreme humidity conditions

A low-pressure microwave O2 plasma is applied on the plastic boxes of the metallized film capacitors to strengthen the interfacial adhesion of thermoplastic box/encapsulating resin. The effectiveness of the plasma is reported by analyzing Scanning Electron Microscopy (SEM) micrographs, X-Ray Photoelectron Spectroscopy (XPS) spectra, and contact angle and roughness measurements. An enhancement of the polar character and total free surface energy in both thermoplastics (polybutylene terephthalate (PBT) and polycarbonate (PC)) are determined. Hence, a better wettability of the plastic boxes with the encapsulating epoxy resin is achieved after the plasma application. During the Temperature-Humidity Bias Test (THB), the metallized film capacitors with PC box improves the performance after being plasma treated. Additional capacitor interfaces seem to play a key role in the performance of the device according to the loss of capacitance determined during the THB Test.

Multilayer film passivation for enhanced reliability of power semiconductor devices

Automotive requirements are becoming ever more severe in terms of device operation under high stress and in harsh working conditions. In this context, passivation layers play a fundamental role in determining electrical performance and reliability. This study focuses on the primary and secondary passivation layers applied to the state-of-the-art power devices and their influence on reliability. Power diodes assembled in standard module packages are used as test vehicles, and high-voltage temperature humidity bias tests are performed to stress the structures. A complete failure mode analysis highlights the phenomena behind the degradation of the passivation layers. Different passivation schemes are evaluated through the application of specific inorganic and organic combinations of layers. Finally, a summary of the typical degradation mechanisms and interactions is presented.

Effect of SDBS on the oxidation reliability of screen-printed Cu circuits

Cu nanopaste is a candidate to replace Ag nanopaste, but the oxidation problems associated with Cu nanopaste must be overcome. In this study, we fabricated Cu nanopaste with various contents of sodium dodecylbenzene sulfonate (SDBS), and the oxidation behaviors of Cu nanopaste with various contents of SDBS were investigated. Then, Cu nanopastes were printed using a screen-printing machine and sintered with infrared energy. The fabricated circuits were evaluated using high-temperature storage tests and steady-state temperature humidity bias life testing. The printed Cu pattern with SDBS showed better oxidation-resistant properties than that without SDBS. After the reliability test, 2 wt% of SDBS shows less oxide based on X-ray diffraction, microstructure, and electrical resistivity measurements, and the optimized content of SDBS was 2 wt% in the Cu nanopaste.

Data-Driven Life Modeling of Electrochemical Migration on Printed Circuit Boards Under Soluble Salt Contamination

Under the air pollution environment, the dust enters the electronic products and deposits on the printed circuit boards (PCB) during the service life. Soluble salts in the airborne dust can reduce the critical humidity and increase the ion concentrations on condensed water film on PCB, which has been proven to aggravate the insulation failure of the high-density PCB caused by electrochemical migration (ECM). It is practical application significance for how to establish a life model to evaluate the ECM of PCB under the interaction of soluble salt with temperature, relative humidity, and electric field strength. In this article, through the temperature humidity bias acceleration experiment, the ECM failure of PCB under the contamination of the different concentrations of NaCl solution is simulated, and the ECM characteristics and failure mechanism are studied through the change of surface insulation resistance (SIR) and the morphology and element compositions of migration products. The time to the insulation failure of PCB under different conditions are obtained by the analysis of SIR curves. Based on the data-driven method, the life modeling of ECM failure of PCB under soluble salt contamination is studied by multivariate non-linear regression and machine learning methods, such as support vector regression, gradient boost regression tree, and random forest regression. It is proved that it is valid to use machine learning to establish the ECM failure life model of PCB in complex environments with limited life data.

Chip-Package-Board Reliability of System-in-Package Using Laminate Chip Embedding Technology Based on Cu Leadframe

We investigate the reliability of a system-in-package (SiP) technology, which uses laminate chip embedding based on a copper leadframe. For this SiP technology, we apply different Si-based transistor technologies. We test the reliability of three types of chip-embedded packages: a single-chip embedded package (SCP) with an embedded MOSFET test chip for basic understanding, and two SiPs—a multichip embedded package (MCP) with a dc/dc converter for industrial applications and a SiP for lighting applications. In order to better represent specific field stresses for the target applications, we develop and investigate new test methods for laminate-based packages. In this article, we report the design, the implementation, and the results of those new methods and discuss their benefits and validity. We conducted conventional test methods like temperature humidity bias (THB) for comparison. The results of all these tests demonstrate a very good reliability of the chip-embedded packages. We also investigate early damages inside the packages using failure analysis techniques such as cross sectioning. The cooperation of partners along the value chain resulted in a coherent understanding of chip-package-board material aspects and design for reliability.

High Voltage Temperature Humidity Bias Test (THB) customized system and methodologies for reliability assessment of power semiconductor devices

High Voltage Temperature Humidity Bias Test (THB-HV) is currently the state of the art test method for reliability evaluation of power devices in high humidity environments at high voltage. These conditions have become especially significant in the case of power modules for the automotive industry and other applications in harsh environments. In this research work, a custom system for active monitoring of THB-HV testing is developed and customized, in order to evaluate different testing methodologies, intercept device degradation in real time, and allow for a controlled and more accurate failure analysis of the DUTs.

Lock-in Thermography Failure Detection on Multilayer Ceramic Capacitors After Flex Cracking and Temperature–Humidity–Bias Stress

A nondestructive method using lock-in thermography (LIT) to detect failures in multilayer ceramic capacitors (MLCCs) is presented. The thermal response of new 25-V MLCCs is compared to the thermal response of the same capacitors after the insertion of flex cracks as well as after 24 and 96 h of total exposure time to a temperature of 75 °C, 75% relative humidity, and 25-V bias. The thermal response was measured before the introduction of any flex cracks, as well as directly after flex cracks were inserted by bending the printed circuit board to $6000~\mu $ Str. No significant change was detected in the thermal profile upon the introduction of flex cracks of which the presence was verified by X-ray imaging. After the MLCCs were subjected to a total of 96 h of temperature–humidity–bias stress, a significant increase in leakage current could be detected as a hotspot in one of the initially 24 samples by LIT. The influence of the different parameters, such as lock-in frequency, bias voltage, and measurement time, on the detectability of the hotspot is presented. Finally, the hotspot location is correlated with the cross-sectional analysis of the capacitor, where melting and solidifying into nickel spheres are found.

A comparison of the Cu electrochemical migration behavior between Cu lines with 5 um L/S realized by conventional Semi Additive Process (SAP) and an innovative Excimer Laser Damascene Process

Abstract The technological evolution regarding multi-chip integrated Fan-Out packages and chip scale packages (CSPs) with high amounts of I/O demands for even higher routing densities. Conventional used technologies and materials like mask aligner and photosensitive polymers used for semi additive process (SAP) in the BEOL have reached its limits to push the resolution down to two um. New materials and technologies are necessary to overcome these limits. As the routing density increases, so does the reliability requirements. The electrochemical migration between Cu lines cannot be neglected and need to be analyzed as the distance between the Cu lines is decreasing. A new approach for fine-line multi redistribution layers (RDL) realized by an excimer laser dual damascene process was presented in the past, using laser ablation and Cu chemical mechanical planarization (CMP) to realize embedded Cu lines. This approach has several advantages regarding the processing but one of the most important characteristics of the damascene approach is the improved electrochemical migration behavior. The Cu lines are partially cladded by the Ti part of the seed layer due to the way of processing. The Ti acts as a barrier layer and inhibits the Cu migration into the surrounding polymer. RDL structures realized by conventional SAP have Ti only under and not between the Cu lines. In this study different test samples with interdigital structures (resp. interdigital capacitor IDC) with five um line and space width (L/S) were realized to analyze the electrochemical migration behavior between the fingers of the IDC. The samples were realized by SAP and by the excimer laser damascene process and were subsequently tested by the temperature humidity bias (THB) test resp. biased High Accelerated Stress Test (bHAST). With the help of this work, we were able to compare the reliability of both process variants and to demonstrate and prove the reliability of embedded copper lines realized by the excimer laser damascene process.

12‐4: Late-News Paper: Reliability Improvement of IGZO and LTPS Hybrid TFTs Array Technology

We report fabrication processes of indium gallium zinc oxide (IGZO) and low temperature poly silicon (LTPS) hybrid TFTs array technology. And the SiOx/IGZO interface quality modification and the performance of different thickness of active layer of IGZO device has been investigated by positive gate bias temperature stress method. The optimum processes conditions have been used on the 1.4” inch circular LCD to improve and pass operation tests of high temperature operation (HTO) 274hrs and temperature‐humidity‐bias (THB) 462 hrs to reach mass production phase.

Latest advancement of fully additive process for 8 µm ultra-fine pitch chip-on-film (COF) by nano-size Ni–P metallization

This paper presents the first demonstration of a precision formation of conductor patterns as fine as 8 µm pitch for flex-based electronics assemblies. We have developed a novel fully additive process (FAP) by combining an ultra-thin chemical surface modification on polyimide (PI) to achieve a uniform Ni–P metallization and subsequent high-speed electrolytic pattern copper plating. On top of the modified interface, an ultra-thin anchoring layer (< 5 nm) constituting amide and carboxyl bonding is able to compensate the hydrophilic nature of the modification layer to obtain reliable adhesion even after being subjected to 300 °C heat treatment, as verified by XPS and TEM analysis at 1000kX. This exceptional property eliminates the trade-off concern by achieving both high-speed signal transmission and enhanced interfacial bond strength on a smooth surface (Ra < 60 nm). Experimental results revealed that the bending endurance and trace deformation characteristic of the fine pitch circuit by this FAP is comparable to conventional COF substrates and is also able to produce high-quality diffusion bonds with the formation of nano-twin structure on the Au–Au bonding interface. Insulation resistance measurements showed no metal residues and no current leakage between 16, 20, and 25 µm pitch COF after temperature humidity bias. On the basis of these results, FAP by direct Ni–P metallization proposed in this work provides unique opportunities for ultra-fine pitch and high electrical performance interconnects.

Power Semiconductor SMD Package Embedded in Multilayered Ceramic for Low Switching Loss

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At 175 °C, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 μA up to a reverse voltage of 980 V. The measured maximum reverse current (IRM), reverse recovery time (Trr), and reverse recovery charge (Qrr) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to 300 A/μs.

Miniature environmental chambers for temperature humidity bias testing of microelectronics.

Environmental chambers are commonly used for reliability testing of microelectronics and other products and materials. These chambers are large, expensive, and limit electrical connectivity to devices under test. In this paper, we present a collection of ten small, low-cost environmental chambers, with humidity control based on mixtures of water and glycerol placed inside the chambers. We demonstrate relative humidities from 44% to 90%, at temperatures from 30 to 85 °C, enabling industry-standard testing at 85% humidity and 85 °C. The division of samples between ten separate chambers allows different conditions to be applied to each sample, in order to quickly characterize the effects of the environment on device reliability, enabling extrapolation to estimate lifetimes in working conditions.

Failure analysis of plastic encapsulated circuits after autoclaving

Abstract Considering that moisture is a crucial factor affecting Plastic Encapsulate Microcircuits (PEMs), several test methods, including Temperature Humidity Bias (THB), autoclaving, and Highly Accelerated Stress Test (HAST), were proposed to assess the moisture resistance capacity of PEMs. To investigate the impact of moisture on PEMs, one certain type of Metal-Oxide -Semiconductor Field Effect Transistor (MOSFET) was selected as a representative of PEMs and underwent an autoclaving in this paper. The results demonstrate that the influences of moisture are diverse. Then a series of analyses, including electrical testing, Scanning Acoustic Microscope (SAM), bond pull testing, metallurgical microscopy, surface and cross-sectional analysis by Scanning Electron Microscope (SEM) and Energy Dispersive Spectrometer (EDS), were conducted to determine the failure cause. With the analyses, the increase of static drain-to-source on resistance is ascribed to surface oxidation. Besides, the moisture invading from the crack along the die side is deemed to contribute to the leakage current failure and the function failure. Finally, some suggestions are proposed to protect PEMs against moisture.

Preparation and Evaluation of a Zirconia/Oligosiloxane Nanocomposite for LED Encapsulation.

A zirconia/oligosiloxane nanocomposite encapsulant has been developed and tested in a high-power LED package against commercial silicone resins. The composite was a marriage of zirconia nanocrystals modified with butyric acid (BA) and 3-methacryloxy propyl trimethoxysilane (MPTMS) and a high-index methacryloxy-oligosiloxanes resin made from MPTMS plus dimethyl, diphenyl, and triphenyl silanes. The modified zirconia had an index of 1.762 (@589 nm) and was dispersible in many solvents. The oligosiloxane resin, however, had an index of 1.5413 with good encapsulation properties and low viscosity allowing the incorporation of more zirconia. The final nanocomposite showed a refractive index of 1.625 with high transparency and a wavelength-independent scattering, both desirable for the light extraction from LED. When tested in a high-power LED package, the composite encapsulant resulted in 13% more light output compared to the commercial encapsulant (OE-6630, Dow Corning Corp.) and showed longer than 1000 h of lifetime (L70) under the steady-state Temperature Humidity Bias (THB) test.