Digital Circuit Technology Research Articles

Investigation of basic elements and devices in multilayer technology for HTS digital RSFQ circuits

Abstract Complex high temperature superconductor digital RSFQ circuits require a multilayer technology that is compatible with freely positionable Josephson junctions. For RSFQ circuits, especially small inductances are required. This can be achieved by using superconducting striplines on a YBCO groundplane. We have produced and examined all basic elements like, e.g., superconducting cross-overs, vias, pinhole free insulation layers and on-chip resistors that are necessary to design and fabricate HTS RSFQ circuits. All structures have been successfully tested and integrated with ramp type junctions with PBCO barriers. For the superconducting lines over the groundplane an inductance of 0.8 pH/square was measured which shows the advantage of a superconducting groundplane. Based on this technology we fabricated a simple multilayer circuit consisting of two magnetically coupled d.c.-SQUIDs. Here we used bicrystal junction stacks due to the smaller spread of junction parameters. The circuit allowed essential operations like generating, erasing and detecting a single flux quantum. One d.c.-SQUID served as storage loop while the other was kept permanently in the voltage state and was used to determine the internal flux state of the storage loop.

Inverter made of complementary p and n channel transistors using a single directly deposited microcrystalline silicon film

We report a p channel thin-film transistor (TFT) made of directly deposited microcrystalline silicon (μc-Si). By integrating this p TFT with its n channel counterpart on a single μc-Si film, we fabricated a complementary metal-silicon oxide-silicon (CMOS) inverter of deposited μc-Si. The μc-Si channel material was grown at 320 °C by plasma-enhanced chemical vapor deposition in a process similar to the deposition of hydrogenated amorphous silicon. The highest postdeposition TFT process temperature was 280 °C. The low-temperature p channel μc-Si TFT and the integrated CMOS inverter represent building blocks of a digital circuit technology based on ultralow-temperature silicon.

Self-timing and vector processing in RSFQ digital circuit technology

As the operating speed of rapid single flux quantum (RSFQ) integrated circuits and systems increases, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, the authors present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. They also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High-speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists of two self-timed shift registers and an on-chip 8-28-GHz clock generator.

Overview of complementary GaAs technology for high-speed VLSI circuits

A self-aligned complementary GaAs (CGaAs) technology (developed at Motorola) for low-power, portable, digital and mixed-mode circuits is being extended to address high-speed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature, it is years ahead of CMOS in terms of fast gate delays at low power supply voltages. Complementary circuits operating at 0.9 V have demonstrated power-delay products of 0.01 /spl mu/W/MHz/gate. Propagation delays of unipolar circuits are as low as 25 ps. Logic families can be mixed on a chip to trade power for delay. CGaAs is being evaluated for VLSI applications through the design of a PowerPC-architecture microprocessor.

A 5-μm-wide 18-cm-long low-loss YBa/sub 2/Cu/sub 3/O/sub 7-δ/ coplanar line for future multichip module technology

Narrow and low-loss YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// (YBCO) coplanar lines, which can be used in multichip module technology for future high-density and high-speed digital circuits, have been developed. Etch-back planarization and a patterning process combining Ar-ion milling and wet-etching enabled us to form an 18-cm-long 5-/spl mu/m-wide YBCO coplanar line without electrical shorts, even for the narrow spacing of 2.5 /spl mu/m. The surface resistance of this line was kept at a level comparable to that of 10- or 25-/spl mu/m-wide YBCO coplanar lines and also comparable to that of unpatterned films. This indicates successful fabrication of the 5-/spl mu/m-wide YBCO coplanar line without notable loss increase resulting from process damage. The 5-/spl mu/m-wide line showed a low-transmission loss of 0.49 dB at 10 GHz and 55 K. This level of loss is similar to that in Cu coaxial cables. No significant increase in transmission loss was observed up to an input power level of 16 mW at 10 GHz and 55 K. This input power is comparable to the power-handling capability required for transmitting high-speed digital signals through the lines with characteristic impedance of 50 /spl Omega/. These results show that the narrow 5-/spl mu/m-wide YBCO coplanar line has great potential for high-density and high-speed digital circuits.

A project scheduling methodology derivedas an analogue of digital circuit technology

The purpose of this paper is to propose a new approach for modeling project activitiesand networks of project activities based on a digital circuit metaphor upon which a projectscheduling tool could be built. Each activity is represented by one or more digital circuitelements where the inputs to the elements are the requirements that must be satisfied beforethat activity can begin. We demonstrate that our model has all the capabilities of traditionalmodels such as PERT/CPM. We then extend our model to incorporate additional featuresnot currently supported by most traditional models. We illustrate the use of AND, OR,NAND, NOR, and XOR gates in the creation of a project network and show how combina-tionsof these elements can be used to represent arbitrarily complex activity requirements.Finally, we discuss how our model could be used to create an open, flexible, extendible anddistributable project planning tool that supports continuous process improvement. The paperpresents the model and how it was developed as an analogue of digital circuit design. Thus,it serves two audiences: those interested in the modeling process and those interested in anovel approach to project scheduling.

Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits

Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology based on superconductors that has emerged as a possible alternative to advanced semiconductor technologies for large scale ultra-high speed, very low power digital applications. Timing of RSFQ circuits at frequencies of tens to hundreds of gigahertz is a challenging and still unresolved problem. Despite the many fundamental differences between RSFQ and semi- conductor logic at the device and at the circuit level, timing of large scale digital circuits in both technologies is principally governed by the same rules and constraints. Therefore, RSFQ offers a new perspective on the timing of ultra-high speed digital circuits. This paper is intended as a comprehensive review of RSFQ timing, from the viewpoint of the principles, concepts, and language developed for semiconductor VLSI. It includes RSFQ clocking schemes, both synchronous and asynchronous, which have been adapted from semiconductor design methodologies as well as those developed specifically for RSFQ logic. The primary features of these synchronization schemes, including timing equations, are presented and compared. In many circuit topologies of current medium to large scale RSFQ circuits, single-phase synchronous clocking outperforms asynchronous schemes in speed, device/area overhead, and simplicity of the design procedure. Synchronous clocking of RSFQ circuits at multigigahertz frequencies requires the application of non-standard design techniques such as pipelined clocking and intentional non-zero clock skew. Even with these techniques, there exist difficulties which arise from the deleterious effects of process variations on circuit yield and performance. As a result, alternative synchronization techniques, including but not limited to asynchronous timing, should be considered for certain circuit topologies. A synchronous two-phase clocking scheme for RSFQ circuits of arbitrary complexity is introduced, which for critical circuit topologies offers advantages over previous synchronous and asynchronous schemes.

Co-integration of high speed InP-based HBTs and RTDs using chemical beam epitaxy

CBE is used to co-integrate InP-based heterojunction bipolar transistors (HBTs) and resonant tunneling diodes (RTDs) for the first time to reduce the complexity of conventional digital circuit technology. The integrated transistors have maximum dc and differential current gain of ∼ 53.6 and 122, respectively, with breakdown voltages V ceo ≈ 6 V and V cbo ≈ 9 V. For microwave performance, the maximum f T and f max are ∼ 77 (63) and ∼ 60 (53) GHz after (before) the onset of negative differential resistance. For digital circuit application, the HBT + RTD structure was used to build bistable mode low power monolithic integrated circuits, including a NAND gate, an inverted majority gate and a NOR gate.

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS

1-V power supply high-speed low-power digital circuit technology with 0.5-/spl mu/m multithreshold-voltage CMOS (MTCMOS) is proposed. This technology features both low-threshold voltage and high-threshold voltage MOSFET's in a single LSI. The low-threshold voltage MOSFET's enhance speed performance at a low supply voltage of 1 V or less, while the high-threshold voltage MOSFET's suppress the stand-by leakage current during the sleep period. This technology has brought about logic gate characteristics of a 1.7-ns propagation delay time and 0.3-/spl mu/W/MHz/gate power dissipation with a standard load. In addition, an MTCMOS standard cell library has been developed so that conventional CAD tools can be used to lay out low-voltage LSI's. To demonstrate MTCMOS's effectiveness, a PLL LSI based on standard cells was designed as a carrying vehicle. 18-MHz operation at 1 V was achieved using a 0.5-/spl mu/m CMOS process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The application of gallium arsenide integrated circuit technology to the design and fabrication of future generation digital signal processors: promises and problems

The development of gallium arsenide digital integrated circuit technology has progressed rapidly during the past decade. It is argued that in order to derive the maximum benefit from this technology as it is inserted into next-generation signal and data processors, all aspects of the design, assembly, testing, and maintenance of the systems will have to be considered synergistically. Salient issues which must be considered in the implementation of these advanced digital processors are reviewed, including the effects of system, logic board, chip layout, and packing constraints on memory layout, logic design, and arithmetic implementation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The Need for a Wholistic Design Approach when using Gallium Arsenide Technology

The emerging Gallium Arsenide digital integrated circuit technology is rapidly becoming well enough established that designers of signal and data processors are planning its incorporation into advanced computational engines of all types. An examination of the characteristics of present and future generation GaAs integrated circuits indicates that they will emphasize moderate on-chip gate counts and high gate speeds. Complete advantage can be taken of GaAs digital technology only if traditional signal processor architectures are completely recast at the memory layout, logic design, arithmetic implementation, and system architecture levels, and if these issues are considered in combination with system, logic board, and chip layout and packaging constraints in a single integrated approach.

GaAs/AlGaAs and InGaAs/AlGaAs MODFET inverter simulations

Although MODFET's have exhibited the fastest switching speed for any digital circuit technology, there is as yet no clear consensus on optimal inverter design rules. We therefore have developed a comprehensive MODFET device model that accurately accounts for such high gate bias effects as transconductance degradation and increased gate capacitance. The device model, which agrees with experimental devices fabricated in this laboratory, is used in the simulation of direct-coupled FET logic (DCFL) inverters with saturated resistor loads. Based on simulation results, the importance of large driver threshold voltage not only for small propagation delay times but for wide logic swings and noise margins is demonstrated. Furthermore, minimum delay times are found to occur at small supply voltages as seen experimentally. Both of these results are attributed to the reduction of detrimental high gate bias effects. The major effect of reducing the gate length on delay time is to decrease the load capacitance of the gate. Using 0.25-µm gates, delay times of 5 and 3.6 ps at 300 and 77 K, respectively, are predicted. Finally, the recently introduced In-GaAs/AlGaAs MODFET's are shown to have switching speeds superior to those of conventional GaAs/AlGaAs MODFET's.

GaAs High-Speed Digital IC Technology: An Overview

Gallium arsenide integrated circuit technology has advanced to the stage where small-scale integration (SSI) and medium-scale integration (MSI) circuits are available for implementation in high-speed digital systems. The recent availability of GaAs wafer foundries for fabrication of custom designs, along with commercially available GaAs components, allows system designers for the first time to take advantage of the inherent high speed and low power capabilities of the technology. Large-scale integration (LSI) complexity circuits are already being fabricated in the United States and abroad, and higher levels of integration are expected. This will result in improved levels of performance for large digital systems. The advantages of higher levels of integration are clearly evident, although there appears to be an optimum level of integration for each GaAs logic family beyond which system speed actually degrades. In conjunction with the development of GaAs technology, an industry-standard GaAs production process is also evolving. This generic process is available (with minor variations) from most of the GaAs wafer foundries and IC manufacturers. Here the authors review digital GaAs IC device and circuit technology and analyze the performance of GaAs circuits fabricated by this production process. They also analyze the effect of the GaAs IC integration levelmore » on computer system speed.« less

Ultra-high-speed ring oscillators based on self-aligned-gate modulation-doped n + -(Al, Ga)As/GaAs FETs

Ultra-high-speed ring oscillator test circuits based on modulation-doped n+-(Al, Ga)As/GaAs field-effect transistors have been fabricated using a completely planar, self-aligned gate by an ion-implantation process. A gate propagation delay of 11.6 ps/gate at a power dissipation of 1.56 mW/gate was measured at room temperature. On cooling to 77 K the gate delay decreased to 8.5 ps/gate at a power dissipation of 2.59 mW/gate. These ring oscillator gate delay times are the fastest ever reported for any semiconductor digital circuit technology.

Design and performance of "1.25-µm" CMOS for digital applications

This paper presents a detailed approach for the design and performance analysis of 1.25-µm CMOS digital circuit technology based on relatively simple sets of fundamental device parametric and circuit equations. As a start, a topological and "in-depth" baseline is assumed for this 1.25-µm CMOS technology, based, in part, on a set of achievable lithographic feature sizes and alignment tolerances together with a set of reasonable process geometric parameters. The process baseline is TWIN-WELL CMOS using n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> epi on an n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> substrate as the host starting material. Two of the key geometric parameters defined are effective channel length, L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</inf> = 1 µm, and gate oxide thickness, t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</inf> = 250 Å. Other dimensions have been selected using quasi-scaling rules consistent with a 2λ of 1.25 µm. The design process starts with the selection of the average "well" doping levels from a consideration of some key short-channel effects: simple charge sharing and drain-induced barrier lowering (DIBL). The selection of a suitable operating voltage, V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> , is considered during this process as it effects junction breakdown voltage, gate oxide fields, and more importantly, potential hot-electron injection. Additional process design analyses are presented with respect to the establishment of gate threshold voltages and field inversion voltages. A simple transient analysis procedure is developed for a basic inverter structure which yields results close to those obtained through more detailed SPICE simulations. A unit delay (single fan-out) analysis is performed yielding delays of 214 ps for a V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> of 5 V and 270 ps for a V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</inf> of 3.3 V.

TheSLC 96Subscriber Loop Carrier System: Overview

Like all digital transmission systems, digital subscriber loop carrier seems destined to play an ever-increasing role in modern communication networks. This trend derives its strength from basic and pervasive factors: (1) the great ease with which digital transmission can support new services, particularly those related to any form of data transmission; (2) the seemingly inexhaustible potential of digital integrated circuit technology to realize ever-decreasing cost, size, and power-per-circuit function; (3) the great promise digital transmission holds for synergy with digital switching. This paper provides an overview to a series of papers that describe in detail AT&T Technologies eminently successful entry in this market, the SLC® 96 Subscriber Loop Carrier System. Emphasis is placed on the background leading to the development and the forces that shaped the system's architecture.

New Biomedical Disciplines and Advances in Computer Performance through Speed Enhancements - Convergence of Problems and Solutions

A class of signal processing problems has been identified which is characterized by input data bandwidths greater than 100 × 106 bytes/second and/or by throughput requirements beyond 5 × 108 arithmetic operations/second, thereby requiring specialized hardware processor implementations for their solution. Examples of such problems from biomedical environment will be presented and discussed. These large computational problems may be suitable candidates for solution by means of an emerging digital integrated circuit technology based upon Gallium Arsenide substrate material, in which the switching speed of the basic gates is enhanced. The technology of GaAs devices, the digital systems which will employ them in an optimal manner, and the tools necessary to design these systems to operate in very high frequency regimes, are described and reviewed.

Recent Advances in GaAs Digital IC Technology

Interest in the GaAs digital integrated circuit technology is growing at a rapid pace. In this paper a comparative analysis of the GaAs FET technology and Si technologies is made. Recent developments at our laboratory are discussed. These include: (1) The implementation of the processing of 3 inch diameter wafers, which brings GaAs fabrication in line with standard semiconductor precessing; (2) Data on the performance of frequency divider circuits showing operation at clock rates as high as 2.6 GHz for a simple D-flip-flop architecture (equivalent to 77 ps average NOR gate propagation delay), and showing excellent performance over a wide temperature range; (3) the design of a GaAs RAM cell capable of very low static power dissipation (>1 µW/bit).

Performance of digital integrated circuit technologies at very high temperatures: John L. Prince, Bruce L. Draper, E. A. Rapp, J. N. Kronberg and Lewis T. Fitch IEEE Trans. Components, Hybrids, Manuf. Technol.CHMT-3(4) 571 (December 1980)

Performance of digital integrated circuit technologies at very high temperatures: John L. Prince, Bruce L. Draper, E. A. Rapp, J. N. Kronberg and Lewis T. Fitch IEEE Trans. Components, Hybrids, Manuf. Technol.CHMT-3(4) 571 (December 1980)

Innovative control systems laboratory equipment

Experiments are described that represent a part of a laboratory program at Michigan Technological University that has been considerably augmented by the utilization of various types of custom-designed equipment. Some recent changes in the laboratory reflect changes in program goals that have occurred in response to the availability of improved digital-circuit technology. The laboratory program is designed to supplement the study of system theory and automatic control theory as presented in several undergraduate electrical engineering courses.