GaAs/AlGaAs and InGaAs/AlGaAs MODFET inverter simulations

Abstract

Although MODFET's have exhibited the fastest switching speed for any digital circuit technology, there is as yet no clear consensus on optimal inverter design rules. We therefore have developed a comprehensive MODFET device model that accurately accounts for such high gate bias effects as transconductance degradation and increased gate capacitance. The device model, which agrees with experimental devices fabricated in this laboratory, is used in the simulation of direct-coupled FET logic (DCFL) inverters with saturated resistor loads. Based on simulation results, the importance of large driver threshold voltage not only for small propagation delay times but for wide logic swings and noise margins is demonstrated. Furthermore, minimum delay times are found to occur at small supply voltages as seen experimentally. Both of these results are attributed to the reduction of detrimental high gate bias effects. The major effect of reducing the gate length on delay time is to decrease the load capacitance of the gate. Using 0.25-µm gates, delay times of 5 and 3.6 ps at 300 and 77 K, respectively, are predicted. Finally, the recently introduced In-GaAs/AlGaAs MODFET's are shown to have switching speeds superior to those of conventional GaAs/AlGaAs MODFET's.