Technology Computer-aided Design Research Articles

A comprehensive investigation of total ionizing dose effects on bulk FinFETs through TCAD simulation

This study investigates the total-ionizing-dose (TID) effect on bulk FinFETs under ON-state irradiation bias, aiming to analyze the cause and physical mechanism of irradiation enhancement effects. Utilizing technology computer-aided design (TCAD), for the first time, we find that parasitic transistors located at the apex of the shallow trench isolation (STI) oxide significantly contribute to the subthreshold degradation of the device, leading to a notable increase in off-state leakage current. Furthermore, under identical irradiation bias conditions, narrower-fin and shorter-channel devices exhibit a more pronounced increase in off-state leakage current. This escalation is attributed to an increased amount of trapped charge in the STI oxide and the elevated electrostatic potential of the punch-through stop (PTS) layer, respectively. Additionally, higher drain voltage reduces the threshold voltage of the STI parasitic transistors, resulting in an increased off-state current as drain voltage rises. In summary, investigating the TID effect of bulk FinFETs under ON-bias is crucial, as it can provide theoretical support for reinforcing nanostructured devices against irradiation-induced degradation.

Novel super stack passivation in AlGaN/GaN HEMT for power electronic applications

Abstract A super-stack passivation technique is proposed for an AlGaN/GaN HEMT in order to improve the breakdown voltage and cutoff frequency. The performance of the proposed technique is benchmarked against a conventional GaN HEMT. The analysis and investigation are carried out using Technology Computer-Aided Design (TCAD). The simulation results are validated with experimental data. It is observed that the breakdown voltage of the conventional and proposed devices is 356V and 449V, respectively. In contrast to the conventional device, the breakdown voltage of the proposed device is improved by 21%. This is the manifestation of the suppression of the electric field by the super-stack passivation technique in the proposed device. Furthermore, it is also observed that the Johnson’s figure of merit in the proposed GaN-HEMT is also improved.

Experimental-Modeling Framework for Identifying Defects Responsible for Reliability Issues in 2D FETs.

In this work, a self-consistent method is used to identify and describe defects plaguing 300 mm integrated 2D field-effect transistors. This method requires measurements of the transfer characteristic hysteresis combined with physics-based modeling of charge carrier capture and emission processes using technology computer aided design (TCAD) tools. The interconnection of experiments and simulations allows one to thoroughly characterize charge trapping/detrapping by/from defects, depending on their energy position. Once the trap energy distribution is extracted, it is used as input in transient TCAD simulations to reproduce the experimental hysteretic transfer characteristics. Our method is widely applicable to any 2D channel/gate stack combination. Here, it is demonstrated on FAB-integrated devices with AlOx/HfO2 gate oxide. A Gaussian-approximated defect band in the AlOx interlayer centered at a position of about 0.1 eV below the conduction band minimum of WS2 is obtained. Based on this energy position, it is concluded that aluminum interstitial and oxygen vacancies are the defects giving rise to the observed hysteresis. These defects are detrimental to the stability of the studied devices as they are easily accessible by channel carriers during on-state operation. A prominent hysteresis obtained during measurements is consistent with this conclusion.

Performance Analysis of JL-FinFET with Varied Non-Uniform Doping Concentrations, Fin Height and Fin Width using Device Simulator

With the growth of the MOSFET technology, the size of the transistor becomes smaller which can lead to Short-Channel Effects (SCEs). In order to address the SCEs, multi-gate transistor such as Fin Field-Effect Transistor (FinFET) has been invented. Meanwhile, it is found that the conventional transistor with junctions also has its drawbacks and limitations due to the decrease in the gate length. The SCEs can occur and affect the overall performance of the device with lower switching times and lower current density . In order to address these limitations, new structure of transistor without junction known as a junctionless (JL) transistor has been proposed. In this work, the impact of uniform versus non-uniform doping concentrations, fin height (Hfin) and fin width (Wfin) in JL-FinFET were investigated by using Technology Computer Aided Design (TCAD) Tools. It was found that non-uniform doping concentration of 4 x1018 cm-3 for the source/drain and of 4 x1017 cm-3 for the channel, together with Hfin of 20 nm and Wfin of 4 nm provide the best electrical performance of Ioff = 6.45 x10-17 A, Ion = 6.14 x10-6 A, Ion/Ioff = 9.52 x1010 and DIBL = 11 mV/V. The outcome of this research work can be used as a basis to understand JL-FinFET biosensors for medical applications and more complex JL structures.

Transient Current Analysis of GaN Neutron Detector Based on the SRIM and TCAD Methods

Utilizing Technology Computer Aided Design (TCAD) software, this study determines the optimal thickness and doping concentration for the intrinsic gallium nitride (GaN) layer in a p-i-n GaN diode to improve detection efficiency and reliability. The study examines energy loss and the transient current response induced by alpha and 3H particles within the GaN p-i-n diode. Additionally, TCAD elucidates the transient current behavior arising from electron-hole pair generation, utilizing the Stopping and Range of Ions in Matter SRIM-2013 linear energy transfer distribution as a guide. The simulations disclose that the tailing effect in the transient current response results from radiation-induced hole accumulation. Elevated applied bias results in increased transient current pulse amplitude, attributed to an extended depletion region that boosts carrier collection. These insights are expected to drive advancements in GaN-based neutron detector technology, essential for advancing nuclear and space science applications in the next generation.

AI‐assisted Field Plate Design of GaN HEMT Device

AbstractGaN High Electron Mobility Transistors (HEMTs) plays a vital role in high‐power and high‐frequency electronics. Meeting the demanding performance requirements of these devices without compromising reliability is a challenging endeavor. Field Plates are employed to redistribute the electric field, minimizing the risk of device failure, especially in high‐voltage operations. While machine learning is applied to GaN device design, its application to field plate structures, known for their geometric complexity, is limited. This study introduces a novel approach to streamlining the field plate design process. It transforms complex 2D field plate structures into a concise feature space, reducing data requirements. A machine learning‐assisted design framework is proposed to optimize field plate structures and perform inverse design. This approach is not exclusive to the design of GaN HEMTs and can be extended to various semiconductor devices with field plate structures. The framework combines technology computer‐aided design (TCAD), machine learning, and optimization, streamlining the design process.

Compact design of universal gates with non-aligned gate technology and assessment of its performance in a TCAD Environment

ABSTRACT This paper proposes a technology computer-aided design (TCAD) of a compact single-device NAND and NOR logic gates in 215 nm device length along with speed and power performance results. The universal gates are designed with non-aligned double gate technology, and this helps to reduce the transistor count, giving a compact design structure. The static characteristics and input pattern sensitivity of the NAND and NOR structures are investigated in this work. By using graphical method, the optimal supply voltage of the universal gates was determined. The optimal supply voltage of the NAND gate and NOR gate was 0.9 V and 0.84 V, respectively, at an input frequency of 1 GHz. Further, the device scalability of the proposed structures was analysed. When compared to the past work, the proposed NAND gate and NOR gate improves delay performance by 25.02% and 35.63%, respectively. Additionally, a reduction of 10% and 16% in its supply voltage is achieved. Therefore, the proposed gate has potential to operate at higher frequency with reduced supply voltage, making them suitable in circuit applications.

TCAD‐enabled machine learning framework for DC and RF performance evaluation of InGaAs sub‐channel DG‐HEMTs

AbstractThis research presents a machine learning (ML)‐based model that determines the DC and RF characteristics of InGaAs sub‐channel double gate high electron mobility transistors (DG‐HEMTs) to optimize the device structure. We employ technology computer‐aided design (TCAD) simulations to analyze the DC and RF performance of InGaAs sub‐channel DG‐HEMTs, generating a range of datasets by varying the material composition, layer width, and thickness of different layers in the device structure. We then train and optimize support vector regression (SVR) models using 5‐fold cross‐validation, varying the kernel function and degree parameters, and achieve better performance with the radial basis function (RBF) kernel. The simulated results indicate that the ML model predicts physical parameters more effectively than experimental analysis, offering a compact modeling solution that requires fewer computing resources than traditional methods.

On the coupled effect of a MIS-based anode and AlGaN-polarized super-junction to reduce the local electric field for AlGaN/GaN Schottky barrier diodes

This work employs advanced physical models with the help of technology computer-aided design tools to systematically design and investigate AlGaN/GaN Schottky barrier diodes (SBDs), focusing on enhancing forward conduction and reverse blocking characteristics. A recessed metal/insulator/III-nitride (MIS) anode is demonstrated to manage electric field distribution. The incorporation of a 1 nm thick Al2O3 layer enables a reduced leakage current and a significant increase in breakdown voltage (BV). Subsequently, tailored field plates (FPs) further improve the BV of the MIS SBD to ∼1650 V but strong electric field magnitude will be found at the edge of the FP. Hence, a MIS SBD with a graded AlGaN barrier layer (MIS-GA SBD) is designed, featuring a gradient decrease in Al content along the [0001] direction. The generation of negative polarization charges within the barrier functions as a super-junction, significantly homogenizing the electric field. As a result, the MIS-GA SBD achieves a remarkable BV exceeding 3500 V, highlighting its strong potential for high-voltage power electronic applications.

String-level compact modeling of erase operations in the body-floated vertical channel of 3D charge trapping flash memory

In this study, we examined the use of string-level compact modeling as an effective framework for circuit simulation focusing on erase operation in 3D charge trapping flash (CTF) memory devices. We analyzed the behaviors of the accumulated hole from p-type bulk (p-well) and the corresponding difference of channel electrostatic potential in the CTF cell string, which is attributed to the variation in hole barrier height in the channel of the ground select line (GSL) transistor during erase operation. We derived a formula for the hole current delivering positive potential from the p-well to the channel region and established a modeling procedure. Technology computer-aided design (TCAD) simulation results were used to extract model parameters and analyze channel electrostatic potential during the erase operation. Additionally, experimental data for erase speed were verified using simulation program with integrated circuit emphasis (SPICE) results. Because the erase efficiency is strongly related to hole behaviors based on the conditions of the GSL transistor, the proposed compact modeling is an effective tool for circuit designers and system architects to achieve better performance in erase execution and optimizing the design of 3D CTF memory devices.

TCAD analysis of conditions for DIBL parameter misestimation in cryogenic MOSFETs

The study aimed to theoretically investigate the transfer characteristics of MOSFETs at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our Technology Computer Aided Design (TCAD) simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V t) in the low drain voltage (V d) region, which causes the misestimation of the DIBL parameter. This V t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation in such underlap devices, confirming the dependence of the DIBL parameter on the linear region of V d serves as an effective method to ensure accurate estimation.

Simulation of synaptic properties of ferroelectric memory capacitors and neural network applications

In this work, the electrical properties and synaptic characteristics of hafnium oxide-based ferroelectric memory capacitor with metal - ferroelectric layer - metal (MFM) structure were simulated using TCAD (technology computer aided design) software. Based on the synaptic potentiation/depression characteristics of the simulated memory capacitor, a multilayer perceptron (MLP) network was constructed, and the recognition accuracy and convergence speed of the MLP network in the MNIST recognition task were simulated, and the feasibility of the ferroelectric memory capacitor synaptic device for real neural network operation was analyzed. The results show that the recognition accuracy of the MLP network reaches 93% and stabilizes after 50 iterations of training, and the recognition accuracy of the MLP network is already at a high usable level after a smaller number of training times of 20, which suggests that the synaptic plasticity of the ferroelectric memory capacitor has a good potential for the practical application of the weight updating of the MLP network.

Self-bias Mo–Sb–Ga multilayer photodetector encompassing ultra-broad spectral response from UV–C to IR–B

Achieving an ultra-broad spectral response in a self-bias detector is a formidable challenge that persists in optoelectronics that necessitates innovative solutions. We propose a unique ultra-broadband photodetecting device, utilizing a multilayer structure comprising Molybdenum Di-sulfide (MoS2), Antimony Tri-selenide (Sb2Se3), and Gallium Nitride (GaN), which exhibits the unique capability of detecting photons without applied bias. The fabricated device demonstrates exceptional sensitivity to a wide range of illumination wavelengths, spanning from ultraviolet–C (UV–C) to infrared–B (IR–B). The design detector displays the highest photo-responsivity of 665 mAW−1 in photovoltaic mode and 3.89 × 105 mAW−1 in photoconductive mode. The designed detector also exhibits a minimal dark current of 90 nA and an extremely weak signal detection capability of ∼12 femto watt-hertz−1/2 at 6 V bias. Additionally, the thermal stability of the MoS2-Sb2Se3-GaN (Mo-Sb-Ga) multi-layer-based self-bias detector was explored. Under the self-bias conditions, the photodetector exhibits a stable behavior up to 250°C with a peak responsivity of 635 mAW−1. The thermal durability of the self-bias ultra-broadband photodetector indicates excellent potential for developing futuristic optoelectronic devices. Further, the performance of the developed detector was examined using Technology Computer-Aided Design (TCAD) simulations, providing valuable insights into the device behavior and the transport of photo-generated carriers, enhancing our understanding of the device operation and enabling performance optimization for diverse applications.

TCAD approach for negative capacitance ferroelectric devices for radiation detection applications

Negative capacitance (NC) emerges as a promising technology for low-power, high-performance transistors. The HiEnD project intends to analyze and design high-energy efficient electronic devices based on innovative ferroelectric materials. It explores NC technology for high-resolution tracking detectors in future high-energy physics experiments. It aims to create ultra-thin, radiation-resistant devices for superior signal detection in harsh environments. This paper presents detailed modeling, simulation results, and a comparison with experimental data, highlighting the potential of the developed methodology but also of the technology for the realization of compact, high-performance detectors. Advanced Technology CAD modeling has been employed to investigate the potentiality of NC devices in unconventional application domains, such as high-energy physics experiments. Numerical simulations, capable of verifying experimental results, enhance predictive power, reducing time and cost in detector design and testing.

Measurements and TCAD simulations of guard-ring structures of thin silicon sensors before and after irradiation

The developing of high performing silicon detectors for particle tracking in the next generation of high-energy physics experiments at future colliders (e.g., HL-LHC, FCC) able to operate efficiently up to very high fluence (∼1⋅10171MeVneq/cm2) is of the utmost importance. In order to sustain high voltage values with minimum leakage current injection into the core region of the sensor, the design and optimisation of the Guard-Ring (GR) protection structure is crucial, especially when small substrate thicknesses are used. In a recent R&D batch produced at Fondazione Bruno Kessler (FBK) in the framework of the “eXFlu” project - INFN CSN5 grant for Young Researchers, different optimisation studies of GR structures for thin substrates (45, 30, 20 and 15μm) up to high fluence (2.5⋅10151MeVneq/cm2) have been addressed. These have been enabled thanks to ad-hoc advanced Technology CAD (TCAD) modelling of different GR design strategies, accounting for the comprehensive bulk and surface radiation-induced damage effects, and an extensive test campaign on such GR structures, both before and after irradiation. In this paper the validation of the development framework of the various GR design options before and after irradiation is presented.

Investigation of BPD Faulting under Extreme Carrier Injection in Room vs High Temperature Implanted 3.3kV SiC MOSFETs

Implantation process for high Al dose p+ contact layers in SiC MOSFETs can generate new basal plane dislocations (BPDs). Such BPD faulting under high carrier injection was investigated in SiC MOSFET layers designed for 3.3kV operation with either room temperature (RT) or high temperature (HT) implantations performed for their high dose p+ contact layer. For excess carrier injection levels of ~1x1018 cm-3 implant induced BPDs faulted from the termination regions of the MOSFETs in the case of RT samples, while the HT samples show no BPD faulting because there were no implant-induced BPDs. However, in the active region of the device no BPDs faulted for both the RT as well as HT samples even at a higher carrier injection of ~1x1019 cm-3. Technology computer-aided design (TCAD) simulations show that the lower doped p-well region below the p+ contact in the active area of the device prevents the minority electron density in the p+ contact layer to below 10x the hole density, which limits BPD faulting even when they are present in that layer as in the case of RT implanted samples.

High-density 3D-NAND flash with dual-string select line (D-SSL)

In this study, high-density 3D-NAND flash memory is proposed. Using D-SSL, lateral shrink of cell area can be achieved by distinguishing two strings in a word-line (WL). We verify erase/program and read characteristics using technology computer-aided design (TCAD) simulations with rigorous calibrated condition. The proposed high density NAND flash has normally-on state SSLs through additional process and electrical treatment. In the conventional reference NAND flash, the cell string connected to the bit-line (BL) is distinguished by WL cut (WLC). On the other hand, in the proposed high density NAND flash, the cell string is selected by utilizing the normally-on state SSLs using trapped hole and doped arsenic at the intersection of SSL1 and SSL2. Compared with the conventional scheme, the proposed D-SSL exhibits almost same erase/program and read characteristics. Consequently, the proposed D-SSL scheme can increase memory density with reduced number of WLCs by distinguishing strings using D-SSL.

Aggravated NBTI reliability due to hard-to-detect open defects

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. In the other hand, the behavior of FinFET devices is influenced by self-heating effect (SHE) due to its 3D structure, low thermal coupling and quantum confinement effect, among others. SHE degrades the device’s performance and could worsen reliability mechanisms like NBTI. In addition, some hard-to-detect open defects in FinFET based-circuits using logic gates designed with multi-fin and multi-finger techniques may escape the test and present abnormal static currents, which may increase the impact of self-heating effect and make the NBTI degradation more severe. Hence, it is crucial to accurately determine the temperature profiles of those chips passing the test and presenting abnormal static currents. This paper investigates the reliability of chips passing the test with abnormal static currents using Sentaurus Technology Computer-Aided Design (TCAD). FinFET transistors are calibrated with Intel 14-nm FinFET technology. Our TCAD simulation framework determines accurately the temperature and NBTI degradation. Using the TCAD information, the device degradation over time can be predicted. Moreover, the delay penalization of a critical logic path of an ISCAS benchmark circuit is investigated. The delay penalization of logic paths, attributed to the defect and NBTI, is analyzed with varying logic depths, emphasizing the importance of addressing critical paths with different logic depths. Our study leads to new considerations for improving the prediction of circuit reliability and taking countermeasures.

Multi-objective optimization and inverse design of complementary field-effect transistor using combined approach of machine learning and non-dominated sorting genetic algorithms for next-generation semiconductor devices

Complementary field-effect transistors (CFETs), which are structures in which different types of transistors are vertically stacked with a shared control gate, are being focused on for continuing to satisfy Moore's law by overcoming the limitations in pitch scaling. The structures of semiconductor devices become more complex as technology node shrinks, and interrelated multivariate parameters increase. In addition, predicting problems and proposing solutions by identifying complex patterns within extensive data collected for emerging semiconductor designs pose significant computational challenges and are inherently difficult. As a breakthrough in design technology co-optimization for advanced devices, this study developed a novel optimization framework integrating technology computer-aided design simulations, machine learning, and non-dominated sorting genetic algorithms. The developed framework provides unbiased optimal solutions, even in a high-dimensional objective space, while considering the tradeoff relationships between multiple variables. In addition, it enables inverse design to identify the design parameters of devices that satisfy specific electrical performance criteria using only a forward model, while achieving an error rate of less than 2%. Using this framework, we analyzed the operational mechanism of CFETs by comparing the inverse designs of various devices. This novel approach is particularly important when the design space is complex and extensive and is well suited for developing devices that emerge with technological advancements in the semiconductor industry.

(Invited) A Neural Compact Model Based on Transfer Learning for Organic FETs

Organic field-effect transistors (organic FETs) exhibit highly non-linear electrical characteristics due to their distinctive transport mechanism manifested by thermally-assisted hopping via localized states randomly distributed in both energy and space domains. This feature impedes the establishment of an analytical compact model. In this context, we present an approach to adopt artificial neural networks (ANN) for the development of a compact model, namely a neural compact model, by exploiting the powerful ability of the ANN to describe a non-linear function accurately. In addition, we evaluate the knowledge transfer method to reduce learning time and improve accuracy even when the data is scarce and costly. By technology computer-aided design simulation, we constructed a dataset of electrical characteristics of organic FETs with Gaussian disorder which is calibrated to the experimental measurement. Subsequently, we constructed and compared neural compact models based on conventional deep learning and transfer learning. We showed that the neural compact model with transfer learning provides an equivalent accuracy at a shorter modeling time. A complex dependence on the gate voltage, drain voltage, and temperature is successfully modeled over a wide range of operation regimes and temperatures.