Technology Computer Aided Design Tools Research Articles

On the coupled effect of a MIS-based anode and AlGaN-polarized super-junction to reduce the local electric field for AlGaN/GaN Schottky barrier diodes

This work employs advanced physical models with the help of technology computer-aided design tools to systematically design and investigate AlGaN/GaN Schottky barrier diodes (SBDs), focusing on enhancing forward conduction and reverse blocking characteristics. A recessed metal/insulator/III-nitride (MIS) anode is demonstrated to manage electric field distribution. The incorporation of a 1 nm thick Al2O3 layer enables a reduced leakage current and a significant increase in breakdown voltage (BV). Subsequently, tailored field plates (FPs) further improve the BV of the MIS SBD to ∼1650 V but strong electric field magnitude will be found at the edge of the FP. Hence, a MIS SBD with a graded AlGaN barrier layer (MIS-GA SBD) is designed, featuring a gradient decrease in Al content along the [0001] direction. The generation of negative polarization charges within the barrier functions as a super-junction, significantly homogenizing the electric field. As a result, the MIS-GA SBD achieves a remarkable BV exceeding 3500 V, highlighting its strong potential for high-voltage power electronic applications.

(Invited) Simulations of Ultra-Scaled Electronic Devices with a Novel Flexible Nano-TCAD Nano-Electronic Simulation Software (NESS) Environment

Simulation of conventional and emerging electronic devices using Technology Computer Aided Design (TCAD) tools has been an essential part of the semiconductor industry as well as academic research. Computational efficiency and accuracy of the numerical modeling are the key criteria on which quality and utility of a TCAD tool is ascertained. Further, the ability of the tool to incorporate different modeling paradigms and to be applicable to a wide range of device architectures and operating conditions is essential.In this talk, I will provide an overview of the new device simulator NESS (Nano-Electronic Software Simulator) developed at Device Modelling Group at University of Glasgow. NESS is a fast, modular software with its own structure and mesh generators, and contains different modules for classical, semi-classical, and quantum transport solvers, mobility calculation, kinetic Monte-Carlo etc. NESS can simulate numerous device architectures such as nanowire and bulk transistors, tunnelling field effect transistors (TFET) and resonant tunnelling diodes. Moreover, NESS accounts for various sources of statistical variability in nano-size electronic devices and it can perform statistical simulations for thousands microscopically different devices.

(Invited) Advanced Modeling of Nanoscale Devices

Moore’s scaling law has survived during more than 50 years because the transistor fabrication recipes have been continuously adapted and technology boosters have been gradually introduced, e.g. strain, high- dielectrics, or 3-D FinFETs. The driving force behind these innovations has always been the intuition of clever researchers who benefited from classical technology computer aided design (TCAD) tools. The latter have been used in the semiconductor industry since the end of the 1970’s, when the first 2-D simulations of CMOS devices became feasible on a supercomputer [1]. Over the last 40 years, transistors have undergone tremendous evolutions, their dimensions being reduced by several orders of magnitude, while the physical models at the core of commercially available device simulators have remained the same: electron transport is still described by classical drift-diffusion (DD) equations, which have been modified to capture parts of the quantum mechanical effects affecting nano-transistors, e.g. geometrical confinement tunnelling leakages, or energy quantization [2].A new generation of advanced TCAD tools that go beyond the DD equations and rely on atomistic quantum mechanical concepts is needed to reproduce the characteristics of today’s nanostructures and to predict the performance of not-yet-fabricated components. Such tools should combine different modelling approaches to be able to treat various device types, from state-of-the-art nano-transistors to photo-detectors based on two-dimensional materials or resistive switching random access memories. For example, to shed light on the behaviour of valence change memory (VCM) cells, which consist of metal-insulator-metal stacks, molecular dynamics (MD), kinetic Monte Carlo (KMC), density functional theory (DFT), and quantum transport (QT) should be allied, as illustrated in the accompanying figure. By doing so, the growth of nano-filaments through realistic oxides embedded between two metallic electrodes can be accurately simulated and the electrical current flowing through computed with, e.g., the Non-equilibrium Green’s Function (NEGF) formalism [3]. In this presentation the multi-method simulation environment shown the accompanying Figure will be briefly reviewed. The main focus will be set on the discussion of few applications, among them transistors and memory cells.

Atomistic Simulation of Nanoscale Devices

Device simulation is nowa­days fully integrated into the production tool chain of transistors. The geometry of the latter can be carefully optimized, possible design pitfalls can be identified early on, and the obtained experimental data can be analyzed in detail thanks to state-of-the-art technology computer aided design tools. However, on the one hand, the dimensions of transistors are reaching the atomic scale. On the other hand, novel functionalities (e.g., light emission/detection) and materials, for example III-V semiconductors, are being added to silicon-based chips. To cope with these challenges it is crucial that device simulators go beyond classical theories, pure electronic transport, and continuum models. The inclusion of quantum mechanical phenomena, electro-thermal effects, and light-matter interactions in systems made of thousands of atoms and of various materials has become critical. In this paper, we review one approach that satisfies all these requirements, the Non-equilibrium Green’s Function (NEGF) formalism, focusing on its combination with <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ab initio</i> bandstructure models. The NEGF method allows to treat electrical, thermal, and optical transport at the quantum mechanical level in multi-material, multi-functional devices, without any empirical parameters. Besides advanced logic switches, it can be used to simulate e.g., photo-detectors, thermoelectric generators, or memory cells composed of almost any materials, in the ballistic limit of transport and in the presence of scattering. The key features of NEGF are summarized first, then selected applications are presented, finally challenges and opportunities are discussed.

Performance Analysis of Gate Engineered High-K Gate Oxide Stack SOI Fin-FET for 5 nm Technology

Abstract: This paper analyses the performance of 5 nm gate length gate engineered oxide stack silicon on insulator (SOI) fin field-effect transistor (OS-Fin-FET) for the first time. The high dielectric (High-K) value of the material-based gate oxide stack structure increases both the analog and the radio frequency (RF) performance of the Fin-FET device when compared to standard single gate oxide material structures. The work function of the engineered gate structure further helps in advancing the performance of the device in terms of on current (Ion), off current (Ioff) and the ratio of Ion/Ioff. The proposed OS-FinFET device improves on current (Ion) of the device by 12% in comparison to the high-K dielectric gate oxidebased FinFET device. Simulation of the device is further extended to study different electrical characteristics of the proposed device under other biasing conditions, to estimate enhanced analog and RF performance where the device is highly suitable for low power and high-speed applications. Overall, the proposed device shows improvement in existing architectures of the devices. Technology computer-aided design (TCAD) tool is used to perform entire simulations of the proposed device with 5 nm gate length. Aim: To enhance analog and RF performance of the Fin-FET device at 5 nm gate length. Background: Design of the sub-10 nm Fin-FET device undergoes charge shearing phenomena because of the minimum distance between source and drain. This problem is addressed by using High-K spacer over substrate but it leads to increase in the channel resistance and adverse short channel effects. A combination of different high-K dielectric materials can eliminate this performance. Hence most of the studies concentrated on spacer region and failed to consider channel region. This study tries to improve analog performance of the device using the approach of gate engineering with gate stack approach. Objective: The main objective of this study is to increase on current (Ion) of the device by implementing gate engineering approach, by choosing dual work function-based gate with oxide stack approach. The High-K dielectric material-based gate oxide reduces leakage current, decreases off current which will increase the ratio of Ion/Ioff. Methods: The dual work function gate material is taken with gate oxide stack approach by considering different High-K dielectric materials like HfO2, TiO2 with thin SiO2 layer as the interactive layer. Simulation of the device is carried out using TCAD Tool and results are compared with existing literature, to validate the results. Results: The proposed architecture of the Fin-FET device delivers excellent results in terms of on current and subthreshold characteristics compared to existing literature. The proposed device gives high on current of 0.027 A and current ratio of 1.08X104. Conclusion: A complete comparative analysis is carried out with existing literature on the proposed device, where the proposed device resulted in high performance. The proposed device improves 12% compared to existing literature, which is highly suitable for low power applications.

TCAD Modeling of High-Field Electron Transport in Bulk Wurtzite GaN: The Full-Band SHE-BTE

Gallium Nitride (GaN) High-Electron Mobility Transistors (HEMTs) actually represent one of the best candidates for medium-high power and radio frequency applications. As they operate at large bias and electric fields, a comprehensive analysis of the high-field transport properties is fundamentals, as hot electrons are expected to play a relevant role for the device reliability. In this perspective, Technology Computer-Aided Design (TCAD) simulations can be a very useful tool for the understanding of the phenomena dominating hot-electron degradation mechanisms. The most-accurate modeling approaches are based on the direct solution of the Boltzmann equation, which is not actually available for the GaN material. In this work, the deterministic solution of the Boltzmann transport equation via the spherical-harmonics expansion (SHE-BTE), as incorporated in a commercial TCAD tool, has been extended to the analysis of GaN electrons. To this purpose, the details of the full-band structure has been derived from DFT calculations as in state-of-art literature works, and the electron density of states, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g(E)$ </tex-math></inline-formula> , and group velocity <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$u_{g}(E)$ </tex-math></inline-formula> , have been calculated for the SHE-BTE for the first time. In addition to this, an accurate calibration of the total scattering rate accounting for nonpolar acoustic and optical carrier-phonon interaction, Coulomb scattering and impact ionization has been carried out against available Monte Carlo data and experiments. The proposed model is also shown to correctly predict the temperature dependence of the electron impact-ionization coefficient and current density up to breakdown.

TCAD Calibration at Cryogenic Temperatures for CMOS Image Sensor Simulations

A simple calibration method is presented for the technology computer-aided design (TCAD) simulation at cryogenic temperature, with a special focus on image sensor application. Based on the principle that TCAD tools are not completely mature for cryogenic environment, a calibration is needed to perform reliable simulations. In this work, measurements and simulations of sheet resistances are used for the TCAD calibration, and an experimental verification is performed by means of the extraction of pinning voltages on JFETs and on a pixel including a pinned photodiode (PPD).

Physical modeling of HZO-based ferroelectric field-effect transistors with a WOx channel

The quasistatic and transient transfer characteristics of Hf0.57Zr0.43O2 (HZO)-based ferroelectric field-effect transistors (FeFETs) with a WOx channel are investigated using a 2-D time-dependent Ginzburg-Landau model as implemented in a state-of-the-art technology computer aided design tool. Starting from an existing FeFET configuration, the influence of different design parameters and geometries is analyzed before providing guidelines for next-generation devices with an increased “high (RH) to low (RL)” resistance ratio, i.e., RH/RL. The suitability of FeFETs as solid-state synapses in memristive crossbar arrays depends on this parameter. Simulations predict that a 13 times larger RH/RL ratio can be achieved in a double-gate FeFET, as compared to a back-gated one with the same channel geometry and ferroelectric layer. The observed improvement can be attributed to the enhanced electrostatic control over the semiconducting channel thanks to the addition of a second gate. A similar effect is obtained by thinning either the HZO dielectric or the WOx channel. These findings could pave the way for FeFETs with enhanced synaptic-like properties that play a key role in future neuromorphic computing applications.

Stacked ferroelectric heterojunction tunnel field effect transistor on a buried oxide substrate for enhanced electrical performance *

The device behavior of a stacked ferroelectric heterojunction tunnel field effect transistor (Fe-HTFET) on a buried oxide substrate is investigated in this paper. Si-doped HfO2 was taken as the ferroelectric material over an oxide layer (gate dielectric) in a stacked gate configuration. A higher drive current and reduced subthreshold swing (SS) may be achieved using Si-doped HfO2 that amplifies the gate bias. The effect of various electrical parameters has been investigated by changing the geometric dimensions of the proposed device. The dimensional parameters have been optimized after extensive simulations. The proposed Fe-HTFET simulations and results show that this structure boosts performance significantly and could be considered a good candidate for ultra-low-power applications. To investigate the performance of the proposed Fe-HTFET, two-dimensional simulations have been done using the Sentaurus technology computer-aided design tool.

On the performance of hafnium-oxide-based negative capacitance FinFETs, with and without a spacer

This paper reports a thorough investigation of the impacts of a spacer dielectric on the performance of HfO2-ferroelectric-based negative capacitance (NC)-FinFETs for 10 nm technology (gate length 22 nm) as per International Roadmap for Devices and Systems with in comparison with similarly-sized conventional FinFETs by means of an industry standard technology computer aided design tool. It is found that, although a high-k spacer results in improved subthreshold swing (SS) and I ON, it increases delay due to enhanced gate capacitance for both types of devices. In spite of having higher gate capacitance for a given spacer, the delay is lower for the NC devices than the conventional devices with identical I OFF, which is due to higher I ON in such devices. Comparing with the baseline FinFET; I ON, SS, threshold voltage, delay and power dissipation of NC-FinFET have been found to improve by 69%, 7%, 5%, 14% and 9% respectively, when Si3N4 spacer is used. Implications of spacer on V DD scalability, delay and power dissipation of NC-FinFETs have also been investigated in one-to-one comparison with similarly-sized conventional FinFETs. If identical delay is considered in both the devices, higher active power dissipation due to enhanced gate capacitance is a concern for HfO2-ferroelectric-based NC-FinFETs.

Quantum Efficiency Simulation and Analysis of Irradiated Complementary Metal-Oxide Semiconductor Image Sensors

A quantum efficiency model of complementary metal-oxide semiconductor image sensors based on Shockley–Read–Hall and Auger recombination is developed using the technology computer-aided design tool, and the quantum efficiency degradation after irradiation is analyzed. By simulating the surface recombination velocity and depletion region width of the photodiode, the decrease in the quantum efficiency of complementary metal-oxide semiconductor image sensors under short and long incident light wavelengths is found to be caused by the increase in the surface recombination velocity and capture of optical carriers by radiation-induced defects in the epitaxial layer, respectively. In addition, a method to reduce the quantum efficiency degradation behavior of an irradiated pixel is discussed.

Foreword Special Issue on “New Simulation Methodologies for Next-Generation TCAD Tools”

Technology computer-aided design (TCAD) is an integral part of the development process of semiconductor technologies and devices, a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resulting devices often have an intricate 3-D structure and contain various specifically designed materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (material properties, interfaces, defects, and so on), to nanometric (quantum confinement, non-bulk properties, tunneling, ballistic transport, and so on), to full-chip dimensions (strain, heat transport, and so on), and time scales from femtoseconds (scattering, ferroelectric switching time, and so on) to seconds (trapping times, degradation, and so on). Voltages, currents, and charges have been scaled to such low levels that statistical effects and process variations have a strong impact. Devices based on new materials (e.g., 2-D crystals) and physical principles (ferroelectrics, magnetic materials, qubits, and so on) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools, and are often too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead, a TCAD tool chain is required which can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles, and the ensuing large-scale simulations and that make use of artificial intelligence for well-chosen (sub)routines to decrease the overall simulation time. This Special Issue features six invited and 18 regular papers that address these problems.

Compact Modeling of pH-Sensitive FETs Based on 2-D Semiconductors

We present a physics-based circuit-compatible model for pH-sensitive field-effect transistors based on two-dimensional (2D) materials. The electrostatics along the electrolyte-gated 2D-semiconductor stack is treated by solving the Poisson equation including the Site-Binding model and the Gouy-Chapman-Stern approach, while the carrier transport is described by the drift-diffusion theory. The proposed model is provided in an analytical form and then implemented in Verilog-A, making it compatible with standard technology computer-aided design tools employed for circuit simulation. The model is benchmarked against two experimental transition-metal-dichalcogenide (MoS2 and ReS2) based ion sensors, showing excellent agreement when predicting the drain current, threshold voltage shift, and current/voltage sensitivity measurements for different pH concentrations.

TCAD analysis of tunnel field effect transistor using Ge material for low power application

Low power is important parameter for any semiconductor devices. In transistors the current flow between source to drain through channel region is dependent upon the materials of source, drain and channel. This paper presents a detailed study of the role of Technology Computer-Aided Design (TCAD) simulations of tunnel-field-effect-transistor (TFET) for low power applications with Germanium (Ge) material. Ge has band gap 0.66 V and the most suitable candidate to improve TFET performance. The need and importance of TCAD tool in semiconductor technology development is explained in details in this manuscript. It also elaborates the TCAD techniques for designing a device, parameter extraction and different models that are used to design different TFET structure. TCAD based digital logic design, design for manufacturing, memory designing and reliability study have been also discussed in this paper.

Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs

In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.

The Analysis of SEU in Nanowire FETs and Nanosheet FETs

The effects of the single-event upset (SEU) generated by radiation on nanowire field-effect transistors (NW-FETs) and nanosheet (NS)-FETs were analyzed according to the incident angle and location of radiation, by using three-dimensional technology computer-aided design tools. The greatest SEU occurred when the particle was incident at 90°, whereas the least occurred at 15°. SEU was significantly affected when the particle was incident on the drain, as compared to when it was incident on the source. The NS-FETs were robust to SEU, unlike the NW-FETs. This phenomenon can be attributed to the difference in the area exposed to radiation, even if the channel widths of these devices were identical.

Static and Dynamic Performance Prediction of Ultrahigh-Voltage Silicon Carbide Insulated-Gate Bipolar Transistors

The performance of theoretical ultrahigh-voltage power semiconductor devices has been predicted by means of numerical simulations using the Sentaurus technology computer-aided design tool. A general silicon carbide punch-through insulated-gate bipolar transistor (IGBT) structure has been implemented with suitable physics-based models and parameters to reflect the device characteristics in a wide range of device blocking voltages from 20 to 50 kV. The models for 20 kV class IGBTs have been implicitly validated by means of published experimental results. Mixed-mode simulations were performed that predicted total switching energy loss densities of 335, 629, 906, and 999 mJ/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for 20, 30, 40, and 50 kV class devices, respectively, at 25 °C, JC = 20 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and an ambipolar carrier lifetime of 20 μs. While the IGBT on-state forward voltage drop reduces, the switching losses increase with higher charge-carrier lifetime for a given current density (e.g., 20 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). The large span of simulation results will be used as an input support to the design of future high-power converters.

Design and simulation of a novel concentric silicon drift detector with equal width divider resistor chain and floating cathodes

Enabling the traditional concentric silicon drift detector (CSDD) does not need an external voltage divider in the application; hence, a novel CSDD structure is proposed in this paper, in which resistor chains of equal width are deposited equally between the cathode rings and come in contact with the cathode rings. The new CSDD can achieve voltage division automatically and only needs to bias the voltage on the cathodes of the innermost ring and the outermost ring. In addition, floating cathodes were designed between the cathodes to obtain a nearly straight line drift channel and to reduce the low electric field area near the surface. The electrical properties of three types of floating cathodes (called floating cathodes of a single-ring, floating cathodes of a double-ring, and floating cathodes of a four-ring) were simulated and compared using the technology computer aided design tool. Under the field effect between the floating cathodes and the bulk, the electric field near the surface increased substantially. Moreover, the electric field near the surface of the CSDD with the floating cathodes of a double-ring changes the most uniformly so that the drift path is the straightest.

Effects of tunneling oxide defect density and inter-diffused carrier concentration on carrier selective contact solar cell performance: Illumination and temperature effects

In this study, technology computer-aided design (TCAD) was used to investigate carrier selective contact solar cell performance based on the boundary of tunneling oxide and electron selective contact layer properties. The role of tunneling oxide quality in the passivation and inter-diffusion properties of the plasma-enhanced chemical vapor deposition of phosphorus-doped amorphous silicon as an electron selective contact layer is studied for carrier selective contact solar cells. Tunnel oxide quality varies according to the ratio of Si4+ to Si2+ state. For the Si4+/Si2+ ratio of 4, open-circuit voltage of 730 mV and the lowest interface trap density of 5.3 × 1010 cm−2 eV−1 are achieved. The change in diffusion depth of the doped layer with respect to the annealing temperature is analysed by transmission electron microscopy (TEM)/energy dispersive X-ray spectroscopy (EDS) measurement. Carrier selective contact solar cell parameters are optimized by incorporating the experimental values of interface trap density, inter-diffused impurity concentration, and depth in the Quokka 3 TCAD tool. Solar cell conversion efficiency of 24.31% was obtained. To understand the response of carrier selective solar cell to the environmental changes, the output characteristics of the solar cell were studied by varying the illumination temperature by 10% of the standard test conditions (STC) and temperature from 277 K to 377 K (difference of 100 K).

Study of analog performance of common source amplifier using rectangular core–shell based double gate junctionless transistor

A new state of the art double gate junctionless transistor (DGJLT) namely the rectangular core–shell DGJLT (RCS-DGJLT) based common source amplifier circuit is designed to investigate the performance. An RCS-DGJLT device is designed using a visual technology computer aided design tool and look up table-based Verilog-A model has been designed to carry out spice simulation of the circuit. Device simulation of RCS-DGJLT shows the extraordinary performance when compared to conventional DGJLT. The RCS-DGJLT exhibits an OFF current (Ioff ) ∼10−14 A, ON current (Ion ) ∼10−5 A, ON/OFF current ratio (Ion /Ioff ) ∼109, subthreshold slope ∼68.9 mV decade−1 and drain induced barrier lowering ∼52.6 mV V−1. Also, the AC response of RCS-DGJLT exhibits good performance like lower miller capacitances of order 10–16 F, maximum unity gain frequency of 138.8 GHz, transconductance generation efficiency of 40 V−1, and gain-bandwidth product of 25.4 GHz. The common source amplifier circuit using RCS-DGJLT provides the amplification up to 3.3 times which implies gain (Av ) to be 3.3. The low leakage power of 10.4 pW and average power of 31.2 µW of common source amplifier circuit based on RCS-DGJLT shows the greater potential of using the proposed device in analog applications. Also, the complete flow chart of the process used to design an analog circuit based on proposed RCS-DGJLT is discussed. The result shows the potential of using the RCS-DGJLT device in designing high-frequency applications.