Technology Computer Aided Design Tools Research Articles

Modeling of Single Ionizing Particle Impacts on Logical Elements of a CMOS Triple Majority Gate

The results of the TCAD (Technology Computer Aided Design) simulation of 65-nm bulk CMOS combinational logical elements of a triple majority gate (TMG) for a reliable microprocessor redundant system are presented. The AND and the OR logic elements, each of which consists of NAND and NOR elements and pairs of inverters, topologically located before and after the line of transistors of each of NAND and of NOR elements, are more noise-immune to single transient processes under the impact of single ionizing particles due to the minimization of the duration of the noise pulse by partially compensating them during the simultaneous charge collection from the track of a single nuclear particle. In simulation with TCAD tools, the tracks of the particles along the normal to the chip surface are used. The charge collection by logical elements with compensation when a linear transfer of particle energy to the track of up to 60 MeV cm2/mg leads to a reduction of the duration of the pulse noise at the output of CMOS AND (and OR) elements by factors of 2 to 5.

Temperature sensitivity analysis of SGO metal strip JL TFET

Temperature sensitivity is one of the major concern in conventional stacked gate-oxide junctionless tunnel-field-effect transistor (SGO-JL-TFET). In this regard, the authors have investigated the sensitivity toward the temperature variation of the SGO-JL double-gate TFET with low work-function live strip (LWLS-SGO-JL-TFET) and without LWLS-SGO-JL-TFET (SGO-JL-TFET). Furthermore, they have analysed and compared the impact of operating temperature variation on the DC, analogue/radiofrequency and linearity performances of both the devices with the help of simulation results obtained using technology computer-aided design tool. It can be stated that the proposed device is less sensitive toward the temperature variation in terms of carrier concentration, electric field, on-state current and off-state current, as compared with conventional SGO-JL-TFET. Apart from these parameters, proposed device also demonstrates better temperature sensitivity in terms of analogue performance parameters such as transconductance ( g m ) cut-off frequency ( f T ) , gain bandwidth product and maximum oscillating frequency ( f max ) . Therefore, the proposed device can be a potential candidate for cryogenics and high-temperature applications.

Study of random dopant fluctuation in PNPN feedback FET

The impact of random dopant fluctuation (RDF) on the performance variation of a PNPN feedback field effect transistor (PNPN FBFET) is investigated using a 3D technology computer aided design tool. To investigate RDF-induced device performance variation (e.g. threshold voltage (VTH) variation), the nominal doping profile of each region in a PNPN FBFET is separately randomized. Consequently, in terms of RDF-induced VTH variation, the channel-2 region (i.e. gated channel region) plays a key role as a main contributor to VTH variation, as it is the most decisive region for determining gate-to-channel controllability. As an example, the value of σVTH resulting from the channel-2 region is nine times higher than that from the channel-1 region. Based on the simulation results, guidelines for variation-immune device design are comprehensively discussed.

Investigation of impact of gate underlap/overlap on the analog/RF performance of composite channel double gate MOSFETs

The influence of gate overlap and underlap on the DC/RF behavior of a composite channel based double gate MOSFET (DG MOSFET) that can be used for RF/analog applications is investigated using the 2D Sentaurus TCAD tool in this work. An InAs-inserted In07Ga0.3As composite channel, double silicon delta doping technology, n+-In0.53Ga0.47As source and drain regions, and Si3N4 passivation are some of the key features of the proposed device. 2D-Sentaurus Technology Computer Aided Design (TCAD) simulation has been performed using the hydrodynamic model. Interface trap models have also been incorporated to increase the accuracy of TCAD simulations carried out at room temperature. Key RF/analog figures of merit such as drain current (ID), transconductance (gm), gate leakage current (IGS), subthreshold current, drain induced barrier lowering, electron velocity in the quantum well, cutoff frequency (fT), and maximum oscillation frequency (fmax) have been explored to analyze the RF/analog performance of the proposed device. TCAD simulations reveal the fact that reducing the gate length and employing a gate underlap strategy can improve the analog and RF performance of the proposed DG MOSFET.

Looking for Quality in TCAD-Based Papers

During the past few years, we have seen an increasing number of submissions of “physics-based simulation only” papers to the IEEE TRANSACTIONS ON ELECTRON DEVICES (T-ED). The popularity of such papers may be explained by the fact that the present widespread technology computer-aided design (TCAD) tools are a significant and welcome boost to creativity in the electronic device community. In fact, TCAD tools allow researchers to explore and optimize device structures without being burdened by technology concerns in terms of availability, cost, and time delay.

Predicting Cosmic Ray-Induced Failures in Silicon Carbide Power Devices

A phenomenological expression for predicting atmospheric neutron-induced failure rates in silicon carbide (SiC) power devices is presented. This expression that relates the local electric field to terrestrial neutron-induced failure rate is derived using empirical data that show commonalities between failures of different SiC power devices under this type of radiation. We also present a physics-based approach that provides a similar functional form for predicting these failure rates. The proposed closed-form expression is then used to demonstrate the use of this model in predicting failure rates in a hypothetical silicon carbide power device modeled using a technology computer-aided design tool.

Modeling and simulation of electrolyte pH change in conventional ISFET using commercial Silvaco TCAD

This paper proposes a numerical simulation approach to study the electrolyte pH change of ion-sensitive field effect transistor (ISFET) structures using Silvaco technology computer-aided design (TCAD) tools. This paper examines the ISFET device’s electrical response to electrolyte pH change. The modeling method is exploited by changing the potential surface charge depending on the electrolyte pH change and investigating how will it cause threshold voltage shift of ISFET device and other transfer characteristic parameters. The properties of a user-defined material offered by Silvaco are exploited to simulate the electrolyte behavior. The parameters of silicon semiconductor material (i.e., energy bandgap, permittivity, affinity, and density of states) are set to reconstruct an electrolyte solution. The electrostatic solution of the electrolyte area is investigated by giving a numerical solution for the semiconductor equation inside this area. Results show excellent agreement between theoretical model and self-consistency TCAD model. Additionally, transfer characteristics of a conventional ISFET device are simulated. The ID current as a function of the reference voltage VRef. and drain voltage VD for different pH scale and ID current as a function of VDS for different VRef. values for specific pH value are simulated. The proposed model allows accurate and efficient ISFET modeling by trying different designs and further optimization with commercial Silvaco TCAD tools rather than expensive fabrication.

Single event effects analysis and charge collection mechanisms on AlGaN/GaN HEMTs

This paper focuses on the effect of single event transients on AlGaN/GaN on sapphire high-electron-mobility-transistors (HEMTs). This results in a novel study in high performance transistors using sapphire substrate. Technology computer aided design tools are used in order to perform the radiation simulations, once the DC response of the transistors have been reproduced. Results show the relationship of the drain current density with ion energy and angle of incidence. The current increases as the ion penetrates deeper in the device due to higher energies, while it decreases as the angle increases. To our knowledge, angle strikes have never been studied before in AlGaN/GaN HEMTs. Several charge collection mechanisms are discussed and their relationships with ion energy and angle of incidence are established.

SET analysis and radiation hardening techniques for CMOS LNA topologies

This paper analyses the effects of single-event transients (SETs) on CMOS low noise amplifiers (LNA) designed for a 0.18 technology. Two well-known topologies, the common-source and common-gate cascodes, have been analysed when heavy ions strike the most sensitive nodes of these structures. In order to simulate these strikes both a physics-based technology computer aided design (TCAD) tool and an electrical circuit domain simulator have been used. This way the physics information given by the TCAD tool is combined with the fast transient simulations performed in circuit simulators. To study their SET performance, the maximum voltage peak and the recovery time of the output signal were calculated for both LNAs. Additionally, a safe operating area can be defined, setting the boundaries for acceptable SETs. Radiation hardening by design techniques have been applied at the most vulnerable nodes of both LNAs. The proposed mitigation approaches make both LNAs hardened against radiation, considerably improving their SET performance.

A New Physical Insight for the 3-D-Layout-Induced Cylindrical Breakdown in Lateral Power Devices on SOI Substrate

The layout-induced cylindrical breakdown may occur as a result of the multifinger or circular layout-induced 3-D curvature effect resulting in the breakdown voltage reduction of the power device significantly. In this paper, by using effective doping concentration (EDC) concept, the inherent 3-D problem is simplified as a 1-D problem. Based on the EDC concept, a 1-D analytical model is presented to qualitatively and quantitatively explore the impact of curvature effect on the breakdown mechanism of SOI lateral double diffused MOS. The analytical solutions are found out to be consistent with the simulation results well obtained from MEDICI, a commercial technology computer-aided design tool. To the best of our knowledge, the proposed model is the first 1-D model which can accurately describe the 3-D curvature effect.

Floating gate effect in amorphous InGaZnO thin-film transistor

In recent years, considerable attention has been paid to amorphous indium gallium-zinc-oxide (a-IGZO) thin film transistors (TFTs) for high performance flat panel display, such as liquid-crystal displays (LCDs), active-matrix organic light-emitting diode (AMOLED) display and flexible display. This is because IGZO TFTs are more suitable for pixels and circuit integrations on display panel than the conventional silicon-based devices. The merits of IGZO TFT technology include high mobility, decent reliability, low manufacturing cost, and excellent uniformity over large fabrication area. However, it was reported that the electrical characteristics of IGZO TFT are susceptible to shift after electrical aging measurement under illumination, which is caused by the activation of trapped electrons from sub-gap states to conducting states. Therefore, it is necessary to introduce light shielding layer to suppress the electrical characteristic shift under illumination aging measurements. Lim et al. demonstrated the characteristics of IGZO TFT with additional light shielding metal layer, and proved that the threshold voltage of TFT can be tuned linearly by adjusting the biasing voltage of the light shielding metal. Taking advantage of this tunable threshold voltage, AMOLED pixel circuit with a threshold voltage shift compensation function can be implemented. However, drawback of this method lies in the adding of additional biasing line, which increases the circuit area and restricts the integration of high-resolution pixel circuits. Thus, Zan et al. proposed adopting floating (unbiased) light shielding metal layer to improve the characteristics of device. However, Zeng et al. demonstrated the abnormal output characteristics of the IGZO TFT, as it cannot be saturated due to the introduction of floating light shielding metal layer. It seems that the IGZO TFT with floating metal is different from the conventional double-gate or single gate structure. To date, the current conducting mechanism of IGZO TFT with floating metal has not been discussed yet. In this paper, the distribution of electrical potential in the IGZO TFT with a cross sectional view is thoroughly analyzed. It is confirmed that the abnormal output characteristic of IGZO TFT is caused by the capacitive coupling between the floating gate and the drain electrode of the transistor. On the basis of the voltage distribution relationship between the equivalent capacitances, a threshold-voltage-dependent current-voltage model is proposed. The simulated results by technology computer-aided design tool and those by the proposed model are in good agreement with each other. Therefore, the mechanism of floating gate effect for IGZO TFT is comprehensively demonstrated. The illustrated conducting mechanism and the proposed current-voltage model are helpful in developing the device and process of IGZO TFT with novel structure.

Fully Depleted GeOI-Channel Junctionless pMOSFET with a Low-Resistance-Raised NiGe Alloy S/D

We fabricated a Ge junctionless p-channel metal–oxide–semiconductor field-effect transistor (JL pMOSFET) with a raised metal source/drain (S/D) composed of a metal alloy. An ultrathin-body Ge channel was trimmed to 10 nm, which is lower than the maximum depletion width, to completely switch off the device. The fabricated Ge JL pMOSFET containing a raised Ni/NiGe S/D exhibited a high on/off current ratio (Ion/Ioff) value (approximately 105 at VDS = −0.1 V). The S/D series resistance of the full metal S/D structure was exactly lower than the structures of Ge/NiGe and Ge bulk S/D. Synopsys Technology Computer-Aided Design tools were used to confirm the advantages of the full metal S/D structure and demonstrate the enhancement of the S/D resistance in a device with scaled gate length. The proposed scheme is suitable for reducing the series resistance of a device with minimized dimensions.

Asymmetric Underlapped Sub-10-nm n-FinFETs for High-Speed and Low-Leakage 6T SRAMs

A 6T SRAM design at a sub-10-nm node calls for carefully designed transistors so that new leakage mechanisms, such as direct source-to-drain tunneling (DSDT) and short channel effects that lead to $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ degradation, are kept under control. In this paper, we explore asymmetric underlap for mitigating DSDT, thermionic leakage, and for improving $I_{\mathrm{\scriptscriptstyle ON}}/I_{\mathrm{\scriptscriptstyle OFF}}$ of double-gate FinFETs. We demonstrate that for 6T SRAMs, asymmetric underlapped n-FinFETs are superior to symmetric underlap/overlap in improving access time and leakage power. We model the atomistic nature of sub-10-nm FinFET channels, quantum confinement, subband nonparabolicity, and anisotropy latent at such length scales using quantum physics-based simulators instead of the conventional semiclassical, drift-diffusion-based Technology Computer Aided Design tools. Using a device/circuit/system-level codesign approach consisting of NEMO5 quantum mechanical device simulations, HSPICE circuit simulations of a 6T SRAM bit cell, and a system-level analysis of a 8-kB L1 and 4-MB L2 cache, we show that the adoption of optimized asymmetric underlapped n-FinFETs can offer up to 6.5% improvement in L1 cache access times and a 2.3-mW reduction in L2 cache leakage power, while delivering noise margins close to symmetric underlapped n-FinFET-based caches.

Numerical Modelling of Polycrystalline Diamond device for Advanced Sensor Design

Technology Computer Aided Design (TCAD) simulation tools are routinely adopted within the design flow of semiconductor devices to simulate their electrical characteristics. However, the device level simulation of diamond is not straightforward within the state-of-the-art TCAD tools. Physical models have to be specifically formulated and tuned for single-crystal CVD (scCVD) and polycrystalline (pcCVD) diamond in order to account for, among others, incomplete ionization, intrinsic carrier free material, dependences of carrier transport on doping and temperature, impact ionization, traps and recombination centers effects.In this work, we propose the development and the application of a numerical model to simulate the electrical characteristics of polycrystalline diamond conceived for sensors fabrication. The model is based on the introduction of an articulated, yet physically based, picture of deep-level defects acting as recombination centers and/or trap states. This approach fosters the exploration and optimization of innovative semiconductor devices conjugating the capabilities of CMOS electronics devices and the properties of diamond substrates, e.g. for biological sensor applications or single particle detectors for High Energy Physics experiments.

Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits

In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computeraided-design (TCAD) simulation shows that the onstate current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from 10° to 20° is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

Numerical simulation of ISFET structures for biosensing devices with TCAD tools.

BackgroundIon Sensitive Field Effect Transistors (ISFETs) are one of the primitive structures for the fabrication of biosensors (BioFETs). Aiming at the optimization of the design and fabrication processes of BioFETs, the correlation between technological parameters and device electrical response can be obtained by means of an electrical device-level simulation. In this work we present a numerical simulation approach to the study of ISFET structures for bio-sensing devices (BioFET) using Synopsys Sentaurus Technology Computer-Aided Design (TCAD) tools.MethodsThe properties of a custom-defined material were modified in order to reproduce the electrolyte behavior. In particular, the parameters of an intrinsic semiconductor material have been set in order to reproduce an electrolyte solution.By replacing the electrolyte solution with an intrinsic semiconductor, the electrostatic solution of the electrolyte region can therefore be calculated by solving the semiconductor equation within this region.ResultsThe electrostatic behaviour (transfer characteristics) of a general BioFET structure has been simulated when the captured target number increases from 1 to 10. The ID current as a function of the VDS voltage for different positions of a single charged block and for different values of the reference electrode have been calculated.The electrical potential distribution along the electrolyte-insulator-semiconductor structure has been evaluated for different molar concentrations of the electrolyte solution.ConclusionsWe presented a numerical simulation approach to the study of Ion-Sensitive Field Effect Transistor (ISFET) structures for biosensing devices (BioFETs) using the Synopsys Sentaurus Technology Computer-Aided Design (TCAD) tools.A powerful framework for the design and optimization of biosensor has been devised, thus helping in reducing technology development time and cost. The main finding of the analysis of a general reference BioFET shows that there is no linear relationship between the number of charges and the current modulation. Actually, there is a strong position dependent effect: targets localized near the source region are most effective with respect to targets localized near the drain region. In general, even randomly distributed targets are more efficient with respect to locally grouped targets on the current modulation. Moreover, for the device at hand, a small positive biasing of the electrolyte solution, providing that the transistor goes on, will result in a greater enhancement of the current levels, still retaining a good sensitivity but greatly simplifying the operations of a real device.

Toward solotronics design in the Wigner formalism

The capability of manipulating single dopant atoms in semiconductor materials, with atomic precision, has given birth to a new branch of electronics known as solotronics (solitary dopant optoelectronics). While experiments are advancing rapidly, the theoretical comprehension of quantum phenomena occurring at that scale is relatively basic. Indeed, in this context, simulations come with incredible mathematical challenges. This eventually prevents practical design and optimization of solotronic devices. In this work, we focus our attention on a planar honeycomb structure exploiting single dopants embedded in silicon and study under which conditions it behaves as an electron ballistic channel. To this aim, we apply the time-dependent Wigner Monte Carlo formalism, based on signed particles to simulate and analyze the phenomena occurring in the proposed structure. We show that, by positioning the dopant atoms (phosphorus and boron) in particular planar patterns (honeycomb), it is possible to control the dynamics of a single electron. Finally, by introducing spatial distortions, we can show how the time-dependent electron dynamics is eventually affected. The results confirm that the Wigner Monte Carlo method is an efficient TCAD (Technology Computer Aided Design) tool which can be exploited for the time-dependent simulation of even more realistic situations necessary for the design of active solotronic devices.

Investigation of Static and Dynamic Characteristics of Optically Controlled Field Effect Transistors

In this paper, we report on an optically controlled field effect transistor (OCFET). The device is based on a modified MOSFET geometry with a Germanium layer interposed between the gate oxide and the gate metal contact. The investigation is performed using the technology computer aided design tool. We describe the principle of operation and investigate the static and dynamic properties of the OCFET under near infrared light at 1.55 μm. Device performance in terms of both ON/OFF current ratio and switching times are studied versus design parameters such as Germanium doping and lifetime as well as gate bias voltage and optical power. Strategies toward best operating conditions and satisfactory tradeoff are investigated and discussed along with future perspective and possible fundamental limitations.

Three-dimensional simulation study of bias effect on single event effects of SiGe heterojunction bipolar transistor

In this paper we establish a three-dimensional (3D) numerical simulation model of domestic SiGe heterojunction bipolar transistor (SiGe HBT) by using technology computer aided design tools, to study the bias effect on single event effect (SEE) of SiGe HBT. The response relationship between SEE and the bias of SiGe HBT is identified based on the analyses of transient current peak and charge collection of each terminal. The results show that the worst biases for SEE are different for different terminals. Even for the same terminal, the worst biases for charge collection and transient current peak are different. This phenomenon is caused mainly by the influence of applied electric field and the change of carrier transport mode.

Low-Power Circuit Analysis and Design Based on Heterojunction Tunneling Transistors (HETTs)

The theoretical lower limit of subthreshold swing in mosfets (60 mV/decade) significantly restricts low-voltage operation since it results in a low ON -to- OFF current ratio at low supply voltages. This paper investigates extremely low-power circuits based on new Si/SiGe heterojunction tunneling transistors (HETTs) that have a subthreshold swing of . Device characteristics, as determined through technology computer aided design tools, are used to develop a Verilog-A device model to simulate and evaluate a range of HETT-based circuits. We show that an HETT-based ring oscillator (RO) shows a 9-19 times reduction in dynamic power compared to a CMOS RO. We also explore two key differences between HETTs and traditional mosfets, namely, asymmetric current flow and increased Miller capacitance, analyze their effect on circuit behavior, and propose methods to address them. HETT characteristics have the most dramatic impact on static random access memory (SRAM) operation and we propose a novel seven-transistor HETT-based SRAM cell topology to overcome, and take advantage of, the asymmetric current flow. This new HETT SRAM design achieves 7-37 times reduction in leakage power compared to CMOS.