Technology Computer-aided Design Simulation Research Articles

High-density 3D-NAND flash with dual-string select line (D-SSL)

In this study, high-density 3D-NAND flash memory is proposed. Using D-SSL, lateral shrink of cell area can be achieved by distinguishing two strings in a word-line (WL). We verify erase/program and read characteristics using technology computer-aided design (TCAD) simulations with rigorous calibrated condition. The proposed high density NAND flash has normally-on state SSLs through additional process and electrical treatment. In the conventional reference NAND flash, the cell string connected to the bit-line (BL) is distinguished by WL cut (WLC). On the other hand, in the proposed high density NAND flash, the cell string is selected by utilizing the normally-on state SSLs using trapped hole and doped arsenic at the intersection of SSL1 and SSL2. Compared with the conventional scheme, the proposed D-SSL exhibits almost same erase/program and read characteristics. Consequently, the proposed D-SSL scheme can increase memory density with reduced number of WLCs by distinguishing strings using D-SSL.

Aggravated NBTI reliability due to hard-to-detect open defects

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. In the other hand, the behavior of FinFET devices is influenced by self-heating effect (SHE) due to its 3D structure, low thermal coupling and quantum confinement effect, among others. SHE degrades the device’s performance and could worsen reliability mechanisms like NBTI. In addition, some hard-to-detect open defects in FinFET based-circuits using logic gates designed with multi-fin and multi-finger techniques may escape the test and present abnormal static currents, which may increase the impact of self-heating effect and make the NBTI degradation more severe. Hence, it is crucial to accurately determine the temperature profiles of those chips passing the test and presenting abnormal static currents. This paper investigates the reliability of chips passing the test with abnormal static currents using Sentaurus Technology Computer-Aided Design (TCAD). FinFET transistors are calibrated with Intel 14-nm FinFET technology. Our TCAD simulation framework determines accurately the temperature and NBTI degradation. Using the TCAD information, the device degradation over time can be predicted. Moreover, the delay penalization of a critical logic path of an ISCAS benchmark circuit is investigated. The delay penalization of logic paths, attributed to the defect and NBTI, is analyzed with varying logic depths, emphasizing the importance of addressing critical paths with different logic depths. Our study leads to new considerations for improving the prediction of circuit reliability and taking countermeasures.

Multi-objective optimization and inverse design of complementary field-effect transistor using combined approach of machine learning and non-dominated sorting genetic algorithms for next-generation semiconductor devices

Complementary field-effect transistors (CFETs), which are structures in which different types of transistors are vertically stacked with a shared control gate, are being focused on for continuing to satisfy Moore's law by overcoming the limitations in pitch scaling. The structures of semiconductor devices become more complex as technology node shrinks, and interrelated multivariate parameters increase. In addition, predicting problems and proposing solutions by identifying complex patterns within extensive data collected for emerging semiconductor designs pose significant computational challenges and are inherently difficult. As a breakthrough in design technology co-optimization for advanced devices, this study developed a novel optimization framework integrating technology computer-aided design simulations, machine learning, and non-dominated sorting genetic algorithms. The developed framework provides unbiased optimal solutions, even in a high-dimensional objective space, while considering the tradeoff relationships between multiple variables. In addition, it enables inverse design to identify the design parameters of devices that satisfy specific electrical performance criteria using only a forward model, while achieving an error rate of less than 2%. Using this framework, we analyzed the operational mechanism of CFETs by comparing the inverse designs of various devices. This novel approach is particularly important when the design space is complex and extensive and is well suited for developing devices that emerge with technological advancements in the semiconductor industry.

Field management in NiO x /β-Ga2O3 merged-PIN Schottky diodes: simulation studies and experimental validation

In recent years, p-type NiO x has emerged as a promising alternative to realize kilovolt-class β-Ga2O3-based PN junction diodes. However, only a handful of studies could realize β–Ga2O3-based unipolar diodes using NiO x as a guard ring or floating rings. In this work, we investigate the device design of NiO x /β-Ga2O3 unipolar diodes using the technology computer aided design simulations and experimental validations. We show that a systematic electric field management approach can potentially lead to NiO x /β-Ga2O3 heterojunction unipolar diode and offer enhanced breakdown characteristics without a severe compromise in the ON-state resistance. Accordingly, the NiO x /β-Ga2O3 heterojunction diode in the merged-PIN Schottky configuration is shown to outperform the regular Schottky diode or junction barrier Schottky diode counterpart. The analysis performed in this work is believed to be valuable in the device design of β-Ga2O3-based unipolar diodes that use a different p-type semiconductor candidate as guard rings and floating rings.

Measurements and TCAD simulations of guard-ring structures of thin silicon sensors before and after irradiation

The developing of high performing silicon detectors for particle tracking in the next generation of high-energy physics experiments at future colliders (e.g., HL-LHC, FCC) able to operate efficiently up to very high fluence (∼1⋅10171MeVneq/cm2) is of the utmost importance. In order to sustain high voltage values with minimum leakage current injection into the core region of the sensor, the design and optimization of the Guard-Ring (GR) protection structure is crucial, especially when small substrate thicknesses are used. In a recent R&D batch produced at Fondazione Bruno Kessler (FBK) in the framework of the “eXFlu” project - INFN CSN5 grant for Young Researchers, different optimisation studies of GR structures for thin substrates (45, 30, 20 and 15μm) up to high fluence (2.5⋅10151MeVneq/cm2) have been addressed. These have been enabled thanks to ad-hoc advanced Technology CAD (TCAD) modelling of different GR design strategies, accounting for the comprehensive bulk and surface radiation-induced damage effects, and an extensive test campaign on such GR structures, both before and after irradiation. In this paper the validation of the development framework of the various GR design options before and after irradiation is presented.

Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism.

This study examines the memory and read delay characteristics of quasi-nonvolatile memory (QNVM) devices operating in a positive feedback mechanism through technology computer-aided design simulation. The QNVM devices exhibit a rapid operation speed of 5 ns, a significant sensing margin of approximately 8.0 μA, and a retention time of around 1 s without any external bias. These devices showcase an exceptionally brief read delay of 0.12 ns. The energy band diagrams during the memory operation are analysed to clarify the factors influencing the read delay. The write and standby conditions modulate the potential barrier height during the standby operation, thereby affecting the read delay. Moreover, the shorter rising time causes the reduction of the read delay. This study demonstrates that the QNVM device has the potential to resolve energy consumption and speed issues in nonvolatile memory devices.

Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries

In this study, a complementary field-effect transistor (CFET) based on a polycrystalline silicon (poly-Si) stacked-nanosheet (NS) structure with a grain boundary (GB) is designed and analyzed using a technology computer-aided design (TCAD) simulation. The advantage of the CFET using a poly-Si is that the active cell region can be reduced by 50 % because the p-type transistors are vertically stacked on the n-type transistors. In addition, it is possible to replace the conventional CMOS process and fabricate a three-dimensional vertically stacked structure at a low cost. To consider the effect of the GB in poly-Si, we assumed that there is a single GB at the center of the body region. By optimizing the geometrical parameters of the proposed CFET, the transfer characteristics of the NMOS and PMOS transistors, such as the threshold voltage (Vth), on current (Ion), off current (Ioff), and subthreshold swing (SS), are symmetrical. The proposed CFET demonstrated a superior logic performance of NML = 0.299 V and NMH = 0.297 V at an operation voltage of VDD = 0.65 V. To consider random GBs in the poly-Si, we assumed that five GBs existed in the proposed CFET, and the variation in CMOS logic inverter characteristics are statistically analyzed. As a result, the RSDs for Vm of the NMOS and PMOS transistors are 2.067 % and 0.293 %, and the RSDs of the pull-down delay time (tpHL) and pull-up delay time (tpLH) are 5.320 % and 3.244 %, respectively. An acceptor-like traps with high trap density are dominant in the proposed CFET, and this trend is similar across the 1024 samples. Nevertheless, most of the differences are within 5 % and the proposed CFET exhibited stability against GBs and the potential to replace the conventional CMOS logic inverters.

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

In this work, we systematically investigate the DC performance of fully depleted silicon-on-insulator (FD-SOI) MOSFETs at both room and cryogenic temperatures as low as 77 K. The influences of back-gate bias on normal and flip-well devices are measured and analyzed. Both types devices display non-linear behaviors when adjusting the back-gate voltage at cryogenic temperatures. Notably, the non-linear effects are more prominent in normal-well devices. The possible reasons are analyzed and verified by technology computer aided design simulation, suggesting that normal-well devices are more susceptible to the formation of depletion regions between the buried oxide layer and the well. This phenomenon disrupts the linearity of the back-gate effect. This research contributes to understanding and characterizing of the back-gate effects in cryogenic environments and holds potential for high-performance computing applications.

Tunable Band‐to‐Band Tunneling and Conducting Path Transition in Local‐Control‐Gate Heterostructure Transistor

AbstractTransition metal dichalcogenide (TMD) material‐based heterostructures have exhibited great potential for building advanced architectures in novel logic devices. A local‐control‐gate (LCG) transistor based on MoTe2/MoS2 heterostructure is fabricated and analyzed, illustrating its tunable electrical characteristics and achieving band‐to‐band tunneling (BTBT) enhancement with an improved peak‐to‐valley current ratio (PVCR) value of 3.04. Compared to the basic dual‐gate tunnel field‐effect transistor (TFET) structure, adding LCG at the bottom not only isolates defect‐induced doping effects from the deposition of top gate dielectrics, but also paves the way for broader applications in multivalued logic and artificial intelligence. Aiming to further verify the operating mechanism of conducting path transition and electrical characteristic trends, commercial technology computer‐aided design (TCAD) is systematically employed assisted by density functional theory (DFT). So that the transition of conducting paths in the heterostructure channel including interlayer quantum effects can be visibly demonstrated while applying various voltages to the LCG. In summary, this work highlights the feasibility of a new LCG structure with tunable electrical characteristics and presents DFT‐assisted TCAD simulations for effective verifications.

Energy-Performance Assessment of Oscillatory Neural Networks Based on VO2 Devices for Future Edge AI Computing.

Oscillatory neural network (ONN) is an emerging neuromorphic architecture composed of oscillators that implement neurons and are coupled by synapses. ONNs exhibit rich dynamics and associative properties, which can be used to solve problems in the analog domain according to the paradigm let physics compute. For example, compact oscillators made of VO2 material are good candidates for building low-power ONN architectures dedicated to AI applications at the edge, like pattern recognition. However, little is known about the ONN scalability and its performance when implemented in hardware. Before deploying ONN, it is necessary to assess its computation time, energy consumption, performance, and accuracy for a given application. Here, we consider a VO2-oscillator as an ONN building block and perform circuit-level simulations to evaluate the ONN performances at the architecture level. Notably, we investigate how the ONN computation time, energy, and memory capacity scale with the number of oscillators. It appears that the ONN energy grows linearly when scaling up the network, making it suitable for large-scale integration at the edge. Furthermore, we investigate the design knobs for minimizing the ONN energy. Assisted by technology computer-aided design (TCAD) simulations, we report on scaling down the dimensions of VO2 devices in crossbar (CB) geometry to decrease the oscillator voltage and energy. We benchmark ONN versus state-of-the-art architectures and observe that the ONN paradigm is a competitive energy-efficient solution for scaled VO2 devices oscillating above 100 MHz. Finally, we present how ONN can efficiently detect edges in images captured on low-power edge devices and compare the results with Sobel and Canny edge detectors.

Investigation of the forward gate leakage current in pGaN/AlGaN/GaN HEMTs through TCAD simulations

In this study, we examined the gate leakage characteristics of normally off pGaN/AlGaN/GaN HEMTs through a simulation study. The Fowler Nordheim Tunneling (FNT) mechanism mainly contributes to the gate leakage process as indicated by the Technology Computer-Aided Design (TCAD) simulation. However, at low bias, the FNT undercalculates the leakage current since the electric field is low in this region. This extra leakage current component at this low bias region can be attributed to the presence of surface traps. Trap-assisted tunneling current along with the FNT current can explain forward leakage characteristics of the pGaN HEMTs. Our TCAD simulations were matched with the experimental data for five devices from four different research groups to support this claim. Using TCAD simulations, we have been able to analyze several device parameters including the various potential drops inside the gate stack structure. We were able to identify some of the trap levels and compare them to the dominant defects expected to be present in the pGaN cap layer. Furthermore, we studied the effects of different device parameters on the gate leakage process in the pGaN HEMT.

3.3 kV-class NiO/β-Ga2O3 heterojunction diode and its off-state leakage mechanism

This Letter demonstrates a high-performance 3.3 kV-class β-Ga2O3 vertical heterojunction diode (HJD) along with an investigation into its off-state leakage mechanism. The vertical β-Ga2O3 HJD with field plate assisted deep mesa (FPDM) termination was fabricated using a self-aligned technique to etch the deep mesa to a depth of 9 μm, thereby reducing electric field crowding at the anode edge. In addition, a thick dielectric is deposited to fill the trench, facilitating the utilization of a field plate to further reduce the electric field at the anode edge. TCAD (Technology Computer Aided Design) simulations show significant suppression of electric field crowding at the anode edge. The fabricated HJD exhibits a high current swing of ∼1010 over a temperature range from 25 °C to 175 °C. The specific on-resistance (Ron,sp) is extracted to be 3.9 mΩ cm2, and the breakdown voltage is 3.42 kV with the FPDM termination. These conduction and blocking characteristics lead to a high power figure of merit of 3 GW/cm2, which is one of the highest among multi-kilovolt β-Ga2O3 diodes. Furthermore, the off-state current leakage mechanism of the HJD under a reverse bias up to 2000 V was investigated. The fitted results reveal that the leakage current is primarily dominated by Poole–Frenkel (PF) emission, with the trap level of PF extracted to be 0.36 eV below the conduction band of NiO.

Understanding of multiway heat extraction using peripheral diamond in an AlGaN/GaN high electron mobility transistor by electrothermal simulations

High-power operation of high electron mobility transistors (HEMTs) is limited due to a variety of thermal resistances in HEMT devices that cause self-heating effects (SHEs). To reduce SHEs, diamond heat spreaders integrated in the device have proven efficient in extracting heat from the device. In this report, we use electrothermal technology computer-aided design simulations to demonstrate a qualitative understanding of multiway heat extraction utilizing diamond heat spreaders to improve HEMT thermal performance at high DC output power densities (∼40 W mm−1). The impact of each heat extraction pathway is understood while considering the thermal boundary resistance between the diamond/GaN heterointerface and optimization of the GaN buffer layer thickness. Using these findings, we simulate an AlGaN/GaN HEMT device operating at 40 W mm−1 DC output power and demonstrate significant reduction in the temperature.

Comprehensive design and analysis of thin film Sb2S3/CIGS tandem solar cell: TCAD simulation approach

This research presents a design and analysis of a tandem solar cell, combining thin film wide bandgap Sb2S3 (1.72 eV) and narrow bandgap CIGS (1.15 eV) for the top and bottom sub-cells, respectively. The integration of all thin film layers enhances flexibility, rendering the tandem solar cell suitable for applications such as wearable electronics. To optimize the power conversion efficiency (PCE) of the tandem solar device, advanced technology computer-aided design (TCAD) simulation tools are employed to estimate loss mechanisms and fine-tune parameters for each layer. An experimentally validated optoelectronic model is introduced, calibrated and validated against fabricated reference solar cells for the individual top and bottom cells. The calibrated model is then utilized to propose optimization routines for the Sb2S3/CIGS tandem solar cell. The initial tandem cell exhibits a J SC of 15.72 mA cm−2 and a PCE of 15.36%. The efficiency drop in the tandem configuration is identified primarily in the top cell. A systematic optimization process for the top cell is initiated, exploring various configurations, including HTL-free and ETL-free setups. Moreover, an np homojunction structure for the top cell is proposed. Optimization routines are applied that involve determining optimal thickness and doping concentration of the n-layer, investigating the effect of p-layer doping concentration, and exploring the influence of the work function of the front contact. As a result, the tandem cell efficiency is significantly improved to 23.33% at the current matching point (CMP), with a J SC of 17.15 mA cm−2. The findings contribute to the advancement of thin-film tandem solar cell technology, showcasing its potential for efficient and flexible photovoltaic applications.

A design methodology for highly reliable operation for 2T0C dynamic random access memory application based on IGZO channel-all-around ferroelectric field-effect transistors

In this paper, the memory characteristics of In-Ga-Zn-O (IGZO)-channel ferroelectric FETs (FeFETs) with stackable vertical channel-all-around structure are investigated by technology computer-aided design (TCAD) simulation. The simulated drain current–gate voltage (I DS–V GS) curves of the IGZO FeFET show an on–off ratio of up to 107 and a memory window of 1.76 V, proving that ferroelectric hafnium oxide (FE-HfO2) is suitable for a 2T0C transistor. To solve the potential current-sharing problem of the 2T0C dynamic random access memory (DRAM) array, an advanced operation design methodology is proposed, which utilizes the bipolar polarization characteristics of FE-HfO2. This solution shows a remarkable current ratio between data “1” and data “0”, not only demonstrating the feasibility of the IGZO-based FeFET on 2T0C DRAM memory cells, but also providing an array design guideline for highly reliable 2T0C memory applications.

Low-Voltage IGZO Field-Effect Ultraviolet Photodiode

Abstract In the era of Internet of Things (IoTs), an energy-efficient ultraviolet (UV) photodetector (PD) is highly desirable considering the massive usage scenarios such as environmental sterilization, fire alarm and corona discharge monitoring. So far, common self-powered UV PDs are mainly based on metal-semiconductor hetero-structures or p–n heterojunctions, where the limited intrinsic built-in electric field restricts further enhancement of the photoresponsivity. In this work, an extremely low-voltage field-effect UV PD is proposed using a gate-drain shorted amorphous IGZO (a-IGZO) thin film transistor (TFT) architecture. A combined investigation of the experimental measurements and technology computer-aided design (TCAD) simulations suggests that the reverse current (I R) of field-effect diode (FED) is highly related with the threshold voltage (V th) of the parental TFT, implying an enhancement-mode TFT is preferable to fabricate the field-effect UV PD with low dark current. Driven by a low bias of −0.1 V, decent UV response has been realized including large UV/visible (R 300/R 550) rejection ratio (1.9 × 103), low dark current (1.15 × 10−12 A) as well as high photo-to-dark current ratio (PDCR, ∼ 103) and responsivity (1.89 A/W). This field-effect photodiode provides a new platform to construct UV PDs with well-balanced photoresponse performance at a low bias, which is attractive for designs of large-scale smart sensor networks with high energy efficiency.

Modeling and Bulk Characterization of 4HSIC Radiation Detector in Sentaurus TCAD Simulation Environment

This paper gives an insight into the need for radiation detection and the most commonly flexible and efficient radiation detector. It also examines bulk characteristics of 4H-SiC semiconductor radiation detector with Ni and Ti as metals for the contact. Bulk characterization of the device, including: doping concentration, electrons and holes behaviors, space charge and current densities were carried out. The modeling is conducted using Sentaurus Technology Computer Aided Design (TCAD) to examine charge transport in bulk 4HSiC material. Data obtained were further analyzed through Sentaurus visual, sentaurus Techplot and Excel to clearly determine the characteristics of the device. It is observed that when the semiconductor and metal are in contact, the Fermi-level is established where the doping concentration varied with either magnitude of the doping concentration or nature of the dopant. Similarly, Schottky and ohmic contacts and temperature effect were observed from the device characteristics which demonstrate that, the detector can withstand a temperature from the range of 100K to 700K in no fluctuating state.

Study on the single-event burnout mechanism of p-GaN gate AlGaN/GaN HEMTs

In this work, the single-event burnout (SEB) mechanism of p-GaN gate AlGaN/GaN HEMTs has been studied systematically. The irradiation experiment was carried out based on Ta ions with high linear energy transfer of 75.4 MeV/(mg/cm2), a standard criterion for commercial space applications. It is clearly observed that both the drain current and gate current increase during the irradiation. With the increasing drain bias, the device burns out eventually. Technology computer-aided design simulation was used to explore the possible burnout mechanism. The local high electric field peak induced by the electron and hole redistribution was proposed to explain the permanent damage. When heavy ions impact the device, electron–hole pairs are formed. With the aid of a horizontal electric field across the channel, electrons and holes move toward the drain and gate, respectively. The accumulation of electrons and holes around the drain edge and gate edge induces the local high electric field, which is even higher than the intrinsic breakdown electric field of GaN and AlGaN. The scanning electron microscope results verified the proposed SEB mechanism. This research offers significant theoretical and experimental insights for evaluating the reliability of GaN power devices against high-energy single-event burnout in aerospace applications.

Enhanced Breakdown Voltage of AlGaN/GaN MISHEMT using GaN Buffer with Carbon-Doping on Silicon for Power Device

In recent years, Gallium Nitride (GaN)-based metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) have attracted interest in high-power and high-frequency applications. The breakdown mechanism in E-mode GaN MISHEMTs with carbon doping in the GaN buffer grown on a Silicon (Si) substrate (Sub) was investigated using technology computer-aided design simulations. Results showed that GaN MISHEMTs without Si Sub had a breakdown voltage (BV) of 600 V. However, after adding Si Sub to the GaN buffer layer, the electric field (EF) increased, creating a vertical breakdown through the total buffer thickness, therefore, BV was reduced to around 240 V. On the other hand, BV is increased to approximately >1100 V, and the Electric field is reduced after employing a carbon deep acceptor with the proper doping concentration in this device. The GaN MISHEMTs with Si Sub is presented as threshold voltage +1.5 V with transconductance of 700 mS/mm, which is an excellent result compared to GaN MISHEMTs without Si Sub. Eventually, the study device depicted higher BV performance compared to other C-doped GaN HEMT devices. This suggests that the designed GaN MISHEMTs device could effectively be used in power semiconductor devices with optimum performance.

Characteristics of β-(AlxGa1−x)2O3/Ga2O3 dual-metal gate modulation-doped field-effect transistors simulated by TCAD

β-(AlxGa1−x)2O3/Ga2O3 modulation-doped field-effect transistors (MODFETs) with a dual-metal gate (DMG) architecture are designed, and the electrical characteristics of the DMG device are investigated in comparison with the single-metal gate (SMG) device by the Technology Computer-Aided Design (TCAD) simulation. The results demonstrate that the DMG MODFETs possess a superior transconductance (gm), current gain cut-off frequency (fT), and power gain cut-off frequency (fMAX) than those of SMG transistors, which is attributed to the regulated channel electric field by a DMG structure. With a gate length of 0.1 μm, the peak values of fT/fMAX of the designed DMG MODFET are obtained as 48.6/50.6 GHz, respectively. Moreover, a comprehensive thermal analysis is conducted between the SMG and DMG devices under steady-state and transient conditions. The DMG MODFET exhibits a lower maximum temperature than the SMG counterpart due to the reduced channel electric field, each subjected to the same power dissipation. This finding underscores the potential of the β-(AlxGa1−x)2O3/Ga2O3 MODFET with the DMG architecture as a promising approach for high-power radio frequency operations.