Technology Computer-aided Design Simulation Research Articles

Optimization of negative capacitance junctionless gate-all-around field-effect transistor using asymmetric non-local lateral Gaussian doping

Technology advancements directed towards Internet-of-Things (IoT) and wearable computing electronics applications are booming in low-power devices, which requires downscaling of power supply voltage without sacrificing the performance of the device. A negative capacitance junctionless gate-all-around field-effect transistor (NC-JL-GAAFET) is investigated using technology computer-aided design (TCAD) simulations to further suppress the short-channel effects and reduce power consumption. Lateral Gaussian doping (LGD), proposed for the NC-JL-GAAFET, is considered its main doping mode. An asymmetric structure with varying lengths of source/drain extension regions is introduced into non-local LGD NC-JL-GAAFET. The results reveal that the proposed device with a larger length ratio for drain extension region has a higher switching current ratio and lower subthreshold swing. Furthermore, the TCAD simulations validate that the electrical characteristics can be easily optimized by adjusting the ferroelectric (FE) layer thickness on the gate stack. Therefore, an asymmetric non-local LGD NC-JL-GAAFET provides a potential scaling solution for the next-generation low-power devices.

Random ferroelectric and dielectric phase distribution-induced device variation of negative capacitance field-effect transistors

Negative-capacitance field-effect transistors (NC-FETs) are significantly affected by their ferroelectric (FE)/dielectric (DE) phase configurations owing to the uncertainty of their crystalline phases. This study presents an analysis of random FE/DE grain distribution-induced variations from multiple perspectives using a seed random number generator in a technology computer-aided design (TCAD) simulation. The results obtained for the NC fully depleted silicon-on-insulator (NC-FDSOI) FETs indicate that device variations can be effectively reduced by increasing the probability of FE grains which improves the switching characteristics. Additionally, the FE distribution at the source presents a larger ON-state current (Ion), while the complete DE path from the source to the drain presents a larger OFF-state current (Ioff). The simulation results also demonstrate that reducing the lateral grain size reduces the device variations while improving the switching current ratio. Increasing the ferroelectric layer thickness of the NC-FDSOI FET can improve its switching performance; however, this also increases its variations. The random FE/DE distribution-induced variations can be reduced by adequately increasing the gate width through device scaling.

Mechanical stress in a tapered channel hole of 3D NAND flash memory

Mechanical stress impact according to the taper angle in 3D vertical NAND flash memory (V-NAND) was investigated using technology computer-aided design simulation (TCAD). In the non-tapered V-NAND, the stress of the polysilicon channel is similar regardless of the number of layers and the position of the WL. On the other hand, in tapered V-NAND, as the taper angle decreases, the CD variation of the channel hole increases, and the compressive stress increases close to the lower WL. The compressive stress applied to the polysilicon channel produces a negative threshold voltage shift (ΔVth) due to conduction band lowering. In tapered V-NAND, the lower WL has a larger ΔVth than the upper WL, and a non-uniform Vth shift occurs. However, as the gate length of the tapered V-NAND is scaled down, the stress of the polysilicon channel is decreased, and the stress difference between the lower WL and upper WL is reduced; therefore, the non-uniform Vth shift is suppressed.

Prediction of SET on SRAM Based on WOA-BP Neural Network

<p>The incidence of high-energy particles into the semiconductor device would induce single event transients (SETs), which is a main threaten to MOS device. And the incidence distances and Linear Energy Transfers (LETs) have important effects on the SET current. A machine learning method based on Whale Optimization Algorithm-Back Propagation neural network (WOA-BPNN) model considering injection distances and LETs has been proposed to predict SET current in this paper. And this method could effectively reduce the simulation time from hours to seconds compared to device model. The current data that predicted by this method has been compared with the Technology Computer Aided Design (TCAD) simulation result which obtained in the background of the 40 nm process technology, the regression coefficient between the predicted value based on the proposed method and the TCAD simulation result was 99.76%, and the maximum integral relative error was 0.287% while the minimum integral relative error is 0.04%. Besides, the proposed method is also compared with PSO-BPNN (Particle Swarm Optimization, PSO) and GA-BPNN (Genetic Algorithm, GA), and the results demonstrated that the WOA-BPNN has prediction accuracy and timing saving advantages over the other two methods.</p> <p> </p>

A Quantum-Computing-Based Method for Solving Quantum Confinement Problem in Semiconductor

Technology computer-aided design (TCAD) of semiconductor devices relies on the numerical solution of differential equations in devices. Recent advances in quantum computing provide a new opportunity for TCAD simulations to be performed on a quantum computer. Based on a variational quantum algorithm, we develop a quantum-computing-based method to solve quantum confinement problems in semiconductor nanostructures. As the number of numerical discretization grid points for solving the Schrödinger equation increases, the number of qubits needed scales only logarithmically, ~ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${O}[\log(N)]$ </tex-math></inline-formula> . The method is applied to solve quantum confinement problems at all dimensions, which are related to confinement in a quantum well, semiconductor nanowire, and semiconductor quantum dot structures. The method can treat an anisotropic band structure and electrostatic potential in semiconductor nanostructures. We further show that the design of ansatz plays an important role in the performance of the method in terms of solution accuracy. The quantum-computing-based method can compute the energies and wave functions of both the ground and excited states with high accuracy.

Characterization of a novel radiation hardened by design (RHD14) bit-cell based on 20-nm FinFET technology using TCAD simulations

Radiation has been a traditional concern in microelectronic devices used in space applications, causing high probability of single event upsets (SEUs). SEUs induced by particle radiation are becoming an increasingly important threat to the reliability of memories. Moreover, recent studies reveals that single event multiple-node upsets (SEMNUs) is the prime effect of radiation in SRAM chips fabricated in nanoscale CMOS technologies. In view of the weaknesses of the existing radiation hardened bit-cell configurations, a highly reliable radiation hardened by design (RHD14) bit-cell is proposed in this paper to address the issues related to SEUs and SEMNUs. Hardness against radiation of the proposed bit-cell is compared with the recently reported radiation hardened bit-cells and popular SRAM bit-cell (6T). Radiation and its effect in the bit-cells under consideration are simulated with the help of 3-D Technology Computer Aided Design (TCAD) and Visual Particle (VP) tools. Radiation hardening capability of RHD14 over the existing and conventional bit-cells is demonstrated focusing on linear energy transfer (LET) threshold and recovery time. It is observed that the proposed radiation hardened cell needs lesser silicon area and performs better in terms of power dissipation. Other performance metrics like read delay, write delay are also evaluated in order to study ensuing trade-off.

A Theoretical Study of Negative Capacitance Field‐Effect Transistors Using Ferroelectrics Having First‐ and Second‐Order Phase Transitions

Herein, a theoretical study of negative capacitance field‐effect transistors (NCFETs) using ferroelectrics (FEs), having first‐ and second‐order phase transitions (FPT and SPT, respectively), applying the Landau–Devonshire (LD) theory, is presented. The expressions for the Landau parameters for FPT FEs are derived from the basic relations, and subsequently, these are used in the numerical models for the surface potential, gate charge, and drain current for NCFETs with FPT FEs, developed in this work. The results show an excellent match with those obtained from technology computer‐aided design (TCAD) simulations. Next, the Landau parameters and the numerical models for the charge and drain current for NCFETs with SPT FEs are developed, following a similar procedure, and then the results of these two structures are compared, along with those obtained from TCAD simulations, which shows an excellent match. The results bring out some interesting observations—notable among them is a higher Ion/Ioff ratio for FPT structures, as compared to that for SPT ones, caused by a reduction in the subthreshold current, with a marginal increase in the strong inversion current in the former. This feature, by itself, may make NCFETs with FPT FEs more suitable than those with SPT FEs for low‐power applications.

A Physics-Based Dynamic Compact Model of Ferroelectric Tunnel Junctions

In this letter, we proposed a dynamic compact model for metal-ferroelectric-semiconductor (MFS) ferroelectric tunnel junctions (FTJ) based on their device physics. The voltage control over dynamic polarizations and the semiconductor surface potentials is achieved for full-region operations, supporting complex FTJ state transitions. A unified and smooth current model across different regions was proposed by formulating tunneling transports in FTJ with complicated barrier shapes from the first-principle tunneling theory. The model was extensively verified with both experimental data and technology computer-aided design (TCAD) simulations, featuring accurate descriptions of multi-states, frequency dependent programming, and circuit simulations.

Novel Trench Inner-Spacer Scheme to Eliminate Parasitic Bottom Transistors in Silicon Nanosheet FETs

A novel and feasible trench inner-spacer (TIS) scheme to eliminate undesired parasitic bottom transistors (trpbt) in gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) is proposed based on fully calibrated Technology Computer-Aided Design (TCAD) simulation. Highly doped punch-through stopper (PTS) layers are generally used to suppress trpbt. Unfortunately, trpbt is still a fatal failure factor in electrical performance degradation when the source/drain (S/D) recess is overetched. Moreover, the proposed TIS scheme prevents the diffusion of S/D dopants toward the PTS region beneath the bottom gate, thereby inhibiting the formation of trpbt. Furthermore, the TIS-NSFETs exhibit excellent immunity to overetched S/D recess depth variations. Additionally, the thermal characteristics of the TIS scheme are compared to that of the bottom oxide (BOX) scheme forming dielectrics beneath the S/D epitaxies, one of the methods used to suppress trpbt. Lattice temperature caused by self-heating and thermal resistance in the TIS-NSFETs are much lower than that in the BOX-NSFETs for both n/p-type devices. The thermal advantage of TIS-NSFETs compared to BOX-NSFETs is confirmed in both DC and AC conditions, similar to an actual operating environment. Therefore, the proposed TIS scheme is highly recommended to eliminate the undesired trpbt without critical DC/AC degradation and to resolve poor heat dissipation problems in the BOX scheme simultaneously.

Bias Dependence of Non-Fourier Heat Spreading in GaN HEMTs

In this article, self-heating in gallium nitride (GaN) high-electron-mobility transistors (HEMTs) is studied by combining the technology computer-aided design (TCAD) and phonon Monte Carlo (MC) simulations. The simulation results indicate that the bias-dependent heat generation in the channel can have a remarkable impact on the thermal spreading process and the phonon ballistic effects simultaneously. Based on the two-heat-source model, we propose a two-thermal-conductivity model to predict the device junction temperature with the consideration of bias-dependent phonon transport in the HEMT. The proposed model is easy to be coupled with the finite-element method (FEM)-based thermal analysis without the need for time-consuming multiscale electrothermal simulations.

Machine Learning Algorithm for Efficient Design of Separated Buffer Super-Junction IGBT

An improved structure for an Insulated Gate Bipolar Transistor (IGBT) with a separated buffer layer is presented in order to improve the trade-off between the turn-off loss (Eoff) and on-state voltage (Von). However, it is difficult to set efficient parameters due to the increase in the new buffer doping concentration variable. Therefore, a machine learning (ML) algorithm is proposed as a solution. Compared to the conventional Technology Computer-Aided Design (TCAD) simulation tool, it is demonstrated that incorporating the ML algorithm into the device analysis could make it possible to achieve high accuracy and significantly shorten the simulation time. Specifically, utilizing the ML algorithm could achieve coefficients of determination (R2) of Von and Eoff of 0.995 and 0.968, respectively. In addition, it enables the optimized design to fit the target characteristics. In this study, the structure proposed for the trade-off improvement was targeted to obtain the minimum Eoff at the same Von, especially by adjusting the concentration of the separated buffer. We could improve Eoff by 36.2% by optimizing the structure, which was expected to be improved by 24.7% using the ML approach. In another way, it is possible to inversely design four types of structures with characteristics close to the target characteristics (Eoff = 1.64 μJ, Von = 1.38 V). The proposed method of incorporating machine learning into device analysis is expected to be very strategic, especially for power electronics analysis (where the transistor size is comparatively large and requires significant computation). In summary, we improved the trade-off using a separated buffer, and ML enabled optimization and a more precise design, as well as reverse engineering.

A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation.

The effect of the source/drain compressive stress on the mechanical stability of stacked Si nanosheets (NS) during the process of channel release has been investigated. The stress of the nanosheets in the stacking direction increased first and then decreased during the process of channel release by technology computer-aided design (TCAD) simulation. The finite element simulation showed that the stress caused serious deformation of the nanosheets, which was also confirmed by the experiment. This study proposed a novel channel release process that utilized multi-step etching to remove the sacrificial SiGe layers instead of conventional single-step etching. By gradually releasing the stress of the SiGe layer on the nanosheets, the stress difference in the stacking direction before and after the last step of etching was significantly reduced, thus achieving equally spaced stacked nanosheets. In addition, the plasma-free oxidation treatment was introduced in the multi-step etching process to realize an outstanding selectivity of 168:1 for Si0.7Ge0.3 versus Si. The proposed novel process could realize the channel release of nanosheets with a multi-width from 30 nm to 80 nm with little Si loss, unlocking the full potential of gate-all-around (GAA) technology for digital, analog, and radio-frequency (RF) circuit applications.

Device simulations with A U-Net model predicting physical quantities in two-dimensional landscapes

Although Technology Computer-Aided Design (TCAD) simulation has paved a successful and efficient way to significantly reduce the cost of experiments under the device design, it still encounters many challenges as the semiconductor industry goes through rapid development in recent years, i.e. Complex 3D device structures, power devices. Recently, although machine learning has been proposed to enable the simulation acceleration and inverse‑design of devices, which can quickly and accurately predict device performance, up to now physical quantities (such as electric field, potential energy, quantum-mechanically confined carrier distributions, and so on) being essential for understanding device physics can still only be obtained by traditional time-consuming self-consistent calculation. In this work, we employ a modified U-Net and train the models to predict the physical quantities of a MOSFET in two-dimensional landscapes for the first time. Errors in predictions by the two models have been analyzed, which shows the importance of a sufficient amount of data to prediction accuracy. The computation time for one landscape prediction with high accuracy by our well-trained U-Net model is much faster than the traditional approach. This work paves the way for interpretable predictions of device simulations based on convolutional neural networks.

A Simple-Structured Perovskite Wavelength Sensor for Full-Color Imaging Application

In this study, simple-structured wavelength sensors were developed by depositing two back-to-back Au/MAPbI3/Au photodetectors on an MAPbI3 single crystal. This sensor could quantitatively distinguish wavelengths. Further device analysis showed that both photodetectors possess entirely disparate optoelectronic properties. Consequently, the as-developed wavelength sensor could accurately distinguish incident-light wavelengths ranging from 265 to 860 nm with a resolution of less than 1.5 nm based on the relation between the photocurrent ratios of both photodetectors and the incident light wavelengths. Notably, a high resolution and wide detection range are among the optimum reported values for such sensors and enable full-color imaging. Furthermore, technology computer-aided design (TCAD) simulations showed that a mechanism involved in distinguishing wavelengths is attributed to the wavelength-dependent photon generation rate in MAPbI3 single crystals. The high-performance MAPbI3 wavelength sensor can potentially drive the research progress of perovskites in wavelength recognition and full-color imaging.

A core drain current model for β-Ga2O3 power MOSFETs based on surface potential

For the first time, a core drain current model based on surface potential without any implicit functions is developed for beta-phase gallium oxide (β-Ga2O3) power metal-oxide-semiconductor field-effect transistors (MOSFETs). The surface potential solution is analytically deduced by solving the Poisson equation with appropriate simplification assumptions in accumulation, partial-depletion, and full-depletion modes. Then, the drain current expression is analytically derived from the Pao–Sah integral as a function of the mobile charge density obtained from the surface potential at the source and drain terminals. In addition, nonlinear resistors in the source/drain access region are considered. It continuously predicts the characteristics of β-Ga2O3 power MOSFETs in all operation modes, including accumulation mode, partial-depletion mode, and full-depletion mode. Furthermore, the validity of the model is verified by comparing the results of the model with the numerical simulations carried out with the technology computer-aided design (TCAD) tool ATLAS Device Simulator from Silvaco. Good agreement between the proposed model and TCAD simulations is shown for β-Ga2O3 power MOSFETs with different intrinsic channel lengths, channel doping concentrations, and channel thicknesses. Ultimately, the Gummel symmetry test and the harmonic balance simulation test are performed to validate the model’s robustness and convergence.

Holistic Optimization of Trap Distribution for Performance/Reliability in 3-D NAND Flash Using Machine Learning

A machine learning (ML) method was used to optimize the trap distribution of the charge trap nitride (CTN) to simultaneously improve its performance/reliability (P/R) characteristics, which are tradeoffs in 3-D NAND flash memories. Using an artificial neural network (ANN), we modeled the relationship between trap distributions and P/R characteristics. The ANN was trained using a large experimentally-calibrated technology computer-aided design (TCAD) simulation dataset. The gradient descent method was adapted to optimize the trap distribution, achieving the best P/R characteristics based on the well-trained ANN. Eventually, we found the best trap profile distributed in both space and energy. In particular, the energetic trap distribution had a larger impact on the P/R characteristics than that of the spatial trap distribution. Furthermore, in terms of the P/R characteristics, it was generally preferable to increase all inputs of the energetic trap distribution. However, the acceptor-like trap energy level ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{TA}$ </tex-math></inline-formula> ) and its standard deviation ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma _{EA}$ </tex-math></inline-formula> ) caused a tradeoff between P/R characteristics; therefore, ML was used to determine their optimal points. The proposed ML method allows the optimization of trap distribution to obtain the best P/R characteristics rapidly and quantitatively. Our findings could be used as a guideline for determining the physical properties of CTN in 3-D NAND flash cells.

Vertical van der Waals heterojunction diodes comprising 2D semiconductors on 3D β-Ga2O3.

Wide bandgap semiconductors such as gallium oxide (Ga2O3) have attracted much attention for their use in next-generation high-power electronics. Although single-crystal Ga2O3 substrates can be routinely grown from melt along various orientations, the influence of such orientations has been seldom reported. Further, making rectifying p-n diodes from Ga2O3 has been difficult due to lack of p-type doping. In this study, we fabricated and optimized 2D/3D vertical diodes on β-Ga2O3 by varying the following three factors: substrate planar orientation, choice of 2D material and metal contacts. The quality of our devices was validated using high-temperature dependent measurements, atomic-force microscopy (AFM) techniques and technology computer-aided design (TCAD) simulations. Our findings suggest that 2D/3D β-Ga2O3 vertical heterojunctions are optimized by substrate planar orientation (-201), combined with 2D WS2 exfoliated layers and Ti contacts, and show record rectification ratios (>106) concurrently with ON-Current density (>103 A cm-2) for application in power rectifiers.

TCAD Modeling of High-Field Electron Transport in Bulk Wurtzite GaN: The Full-Band SHE-BTE

Gallium Nitride (GaN) High-Electron Mobility Transistors (HEMTs) actually represent one of the best candidates for medium-high power and radio frequency applications. As they operate at large bias and electric fields, a comprehensive analysis of the high-field transport properties is fundamentals, as hot electrons are expected to play a relevant role for the device reliability. In this perspective, Technology Computer-Aided Design (TCAD) simulations can be a very useful tool for the understanding of the phenomena dominating hot-electron degradation mechanisms. The most-accurate modeling approaches are based on the direct solution of the Boltzmann equation, which is not actually available for the GaN material. In this work, the deterministic solution of the Boltzmann transport equation via the spherical-harmonics expansion (SHE-BTE), as incorporated in a commercial TCAD tool, has been extended to the analysis of GaN electrons. To this purpose, the details of the full-band structure has been derived from DFT calculations as in state-of-art literature works, and the electron density of states, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g(E)$ </tex-math></inline-formula> , and group velocity <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$u_{g}(E)$ </tex-math></inline-formula> , have been calculated for the SHE-BTE for the first time. In addition to this, an accurate calibration of the total scattering rate accounting for nonpolar acoustic and optical carrier-phonon interaction, Coulomb scattering and impact ionization has been carried out against available Monte Carlo data and experiments. The proposed model is also shown to correctly predict the temperature dependence of the electron impact-ionization coefficient and current density up to breakdown.

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors

In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN-based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

An Optimized Vertical GaN Parallel Split Gate Trench MOSFET Device Structure for Improved Switching Performance

This work proposes a vertical gallium nitride (GaN) parallel split gate trench MOSFET (PSGT-MOSFET) device architecture suitable for power conversion applications. Wherein two parallel gates, and a field plate are introduced vertically on the sidewalls and connected, respectively, to the gate and source. Technology computer-aided design (TCAD) simulator was used in the design process to achieve a specific on-resistance as low as 0.79 mΩ.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for the device, which has the capacity of blocking voltages up to 600 V. The peak electric field of the PSGT-MOSFET could well be lowered to 2.95 MV/cm, which is about 17% lower than that of a conventional trench gate MOSFET (TG-MOSFET) near the trench corner with help of suitable design and optimization of trench depth, drift doping, and field plate thickness. The TCAD simulation shows that the higher drift doping on the device performance of PSGT-MOSFET produces ~2× lower switching losses when compared with a similarly rated conventional TG-MOSFET device.