Technology Computer-aided Design Simulation Research Articles

High-density 3D-NAND flash with dual-string select line (D-SSL)

Abstract In this study, high-density 3D-NAND flash memory is proposed. Using D-SSL, lateral shrink of cell area can be achieved by distinguishing two strings in a word-line (WL). We verify erase/program and read characteristics using technology computer-aided design (TCAD) simulations with rigorous calibrated condition. The proposed high density NAND flash has normally-on state SSLs through additional process and electrical treatment. In the conventional reference NAND flash, the cell string connected to the bit-line (BL) is distinguished by WL cut (WLC). On the other hand, in the proposed high density NAND flash, the cell string is selected by utilizing the normally-on state SSLs using trapped hole and doped arsenic at the intersection of SSL1 and SSL2. Compared with the conventional scheme, the proposed D-SSL exhibits almost same erase/program and read characteristics. Consequently, the proposed D-SSL scheme can increase memory density with reduced number of WLCs by distinguishing strings using D-SSL.

Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism.

This study examines the memory and read delay characteristics of quasi-nonvolatile memory (QNVM) devices operating in a positive feedback mechanism through technology computer-aided design simulation. The QNVM devices exhibit a rapid operation speed of 5 ns, a significant sensing margin of approximately 8.0 μA, and a retention time of around 1 s without any external bias. These devices showcase an exceptionally brief read delay of 0.12 ns. The energy band diagrams during the memory operation are analysed to clarify the factors influencing the read delay. The write and standby conditions modulate the potential barrier height during the standby operation, thereby affecting the read delay. Moreover, the shorter rising time causes the reduction of the read delay. This study demonstrates that the QNVM device has the potential to resolve energy consumption and speed issues in nonvolatile memory devices.

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

In this work, we systematically investigate the DC performance of fully depleted silicon-on-insulator (FD-SOI) MOSFETs at both room and cryogenic temperatures as low as 77 K. The influences of back-gate bias on normal and flip-well devices are measured and analyzed. Both types devices display non-linear behaviors when adjusting the back-gate voltage at cryogenic temperatures. Notably, the non-linear effects are more prominent in normal-well devices. The possible reasons are analyzed and verified by technology computer aided design simulation, suggesting that normal-well devices are more susceptible to the formation of depletion regions between the buried oxide layer and the well. This phenomenon disrupts the linearity of the back-gate effect. This research contributes to understanding and characterizing of the back-gate effects in cryogenic environments and holds potential for high-performance computing applications.

Tunable Band‐to‐Band Tunneling and Conducting Path Transition in Local‐Control‐Gate Heterostructure Transistor

AbstractTransition metal dichalcogenide (TMD) material‐based heterostructures have exhibited great potential for building advanced architectures in novel logic devices. A local‐control‐gate (LCG) transistor based on MoTe2/MoS2 heterostructure is fabricated and analyzed, illustrating its tunable electrical characteristics and achieving band‐to‐band tunneling (BTBT) enhancement with an improved peak‐to‐valley current ratio (PVCR) value of 3.04. Compared to the basic dual‐gate tunnel field‐effect transistor (TFET) structure, adding LCG at the bottom not only isolates defect‐induced doping effects from the deposition of top gate dielectrics, but also paves the way for broader applications in multivalued logic and artificial intelligence. Aiming to further verify the operating mechanism of conducting path transition and electrical characteristic trends, commercial technology computer‐aided design (TCAD) is systematically employed assisted by density functional theory (DFT). So that the transition of conducting paths in the heterostructure channel including interlayer quantum effects can be visibly demonstrated while applying various voltages to the LCG. In summary, this work highlights the feasibility of a new LCG structure with tunable electrical characteristics and presents DFT‐assisted TCAD simulations for effective verifications.

Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries

In this study, a complementary field-effect transistor (CFET) based on a polycrystalline silicon (poly-Si) stacked-nanosheet (NS) structure with a grain boundary (GB) is designed and analyzed using a technology computer-aided design (TCAD) simulation. The advantage of the CFET using a poly-Si is that the active cell region can be reduced by 50 % because the p-type transistors are vertically stacked on the n-type transistors. In addition, it is possible to replace the conventional CMOS process and fabricate a three-dimensional vertically stacked structure at a low cost. To consider the effect of the GB in poly-Si, we assumed that there is a single GB at the center of the body region. By optimizing the geometrical parameters of the proposed CFET, the transfer characteristics of the NMOS and PMOS transistors, such as the threshold voltage (Vth), on current (Ion), off current (Ioff), and subthreshold swing (SS), are symmetrical. The proposed CFET demonstrated a superior logic performance of NML = 0.299 V and NMH = 0.297 V at an operation voltage of VDD = 0.65 V. To consider random GBs in the poly-Si, we assumed that five GBs existed in the proposed CFET, and the variation in CMOS logic inverter characteristics are statistically analyzed. As a result, the RSDs for Vm of the NMOS and PMOS transistors are 2.067 % and 0.293 %, and the RSDs of the pull-down delay time (tpHL) and pull-up delay time (tpLH) are 5.320 % and 3.244 %, respectively. An acceptor-like traps with high trap density are dominant in the proposed CFET, and this trend is similar across the 1024 samples. Nevertheless, most of the differences are within 5 % and the proposed CFET exhibited stability against GBs and the potential to replace the conventional CMOS logic inverters.

Investigation of the forward gate leakage current in pGaN/AlGaN/GaN HEMTs through TCAD simulations

In this study, we examined the gate leakage characteristics of normally off pGaN/AlGaN/GaN HEMTs through a simulation study. The Fowler Nordheim Tunneling (FNT) mechanism mainly contributes to the gate leakage process as indicated by the Technology Computer-Aided Design (TCAD) simulation. However, at low bias, the FNT undercalculates the leakage current since the electric field is low in this region. This extra leakage current component at this low bias region can be attributed to the presence of surface traps. Trap-assisted tunneling current along with the FNT current can explain forward leakage characteristics of the pGaN HEMTs. Our TCAD simulations were matched with the experimental data for five devices from four different research groups to support this claim. Using TCAD simulations, we have been able to analyze several device parameters including the various potential drops inside the gate stack structure. We were able to identify some of the trap levels and compare them to the dominant defects expected to be present in the pGaN cap layer. Furthermore, we studied the effects of different device parameters on the gate leakage process in the pGaN HEMT.

A design methodology for highly reliable operation for 2T0C dynamic random access memory application based on IGZO channel-all-around ferroelectric field-effect transistors

In this paper, the memory characteristics of In-Ga-Zn-O (IGZO)-channel ferroelectric FETs (FeFETs) with stackable vertical channel-all-around structure are investigated by technology computer-aided design (TCAD) simulation. The simulated drain current–gate voltage (I DS–V GS) curves of the IGZO FeFET show an on–off ratio of up to 107 and a memory window of 1.76 V, proving that ferroelectric hafnium oxide (FE-HfO2) is suitable for a 2T0C transistor. To solve the potential current-sharing problem of the 2T0C dynamic random access memory (DRAM) array, an advanced operation design methodology is proposed, which utilizes the bipolar polarization characteristics of FE-HfO2. This solution shows a remarkable current ratio between data “1” and data “0”, not only demonstrating the feasibility of the IGZO-based FeFET on 2T0C DRAM memory cells, but also providing an array design guideline for highly reliable 2T0C memory applications.

Modeling and Bulk Characterization of 4HSIC Radiation Detector in Sentaurus TCAD Simulation Environment

This paper gives an insight into the need for radiation detection and the most commonly flexible and efficient radiation detector. It also examines bulk characteristics of 4H-SiC semiconductor radiation detector with Ni and Ti as metals for the contact. Bulk characterization of the device, including: doping concentration, electrons and holes behaviors, space charge and current densities were carried out. The modeling is conducted using Sentaurus Technology Computer Aided Design (TCAD) to examine charge transport in bulk 4HSiC material. Data obtained were further analyzed through Sentaurus visual, sentaurus Techplot and Excel to clearly determine the characteristics of the device. It is observed that when the semiconductor and metal are in contact, the Fermi-level is established where the doping concentration varied with either magnitude of the doping concentration or nature of the dopant. Similarly, Schottky and ohmic contacts and temperature effect were observed from the device characteristics which demonstrate that, the detector can withstand a temperature from the range of 100K to 700K in no fluctuating state.

Study on the single-event burnout mechanism of p-GaN gate AlGaN/GaN HEMTs

In this work, the single-event burnout (SEB) mechanism of p-GaN gate AlGaN/GaN HEMTs has been studied systematically. The irradiation experiment was carried out based on Ta ions with high linear energy transfer of 75.4 MeV/(mg/cm2), a standard criterion for commercial space applications. It is clearly observed that both the drain current and gate current increase during the irradiation. With the increasing drain bias, the device burns out eventually. Technology computer-aided design simulation was used to explore the possible burnout mechanism. The local high electric field peak induced by the electron and hole redistribution was proposed to explain the permanent damage. When heavy ions impact the device, electron–hole pairs are formed. With the aid of a horizontal electric field across the channel, electrons and holes move toward the drain and gate, respectively. The accumulation of electrons and holes around the drain edge and gate edge induces the local high electric field, which is even higher than the intrinsic breakdown electric field of GaN and AlGaN. The scanning electron microscope results verified the proposed SEB mechanism. This research offers significant theoretical and experimental insights for evaluating the reliability of GaN power devices against high-energy single-event burnout in aerospace applications.

Enhanced Breakdown Voltage of AlGaN/GaN MISHEMT using GaN Buffer with Carbon-Doping on Silicon for Power Device

In recent years, Gallium Nitride (GaN)-based metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) have attracted interest in high-power and high-frequency applications. The breakdown mechanism in E-mode GaN MISHEMTs with carbon doping in the GaN buffer grown on a Silicon (Si) substrate (Sub) was investigated using technology computer-aided design simulations. Results showed that GaN MISHEMTs without Si Sub had a breakdown voltage (BV) of 600 V. However, after adding Si Sub to the GaN buffer layer, the electric field (EF) increased, creating a vertical breakdown through the total buffer thickness, therefore, BV was reduced to around 240 V. On the other hand, BV is increased to approximately >1100 V, and the Electric field is reduced after employing a carbon deep acceptor with the proper doping concentration in this device. The GaN MISHEMTs with Si Sub is presented as threshold voltage +1.5 V with transconductance of 700 mS/mm, which is an excellent result compared to GaN MISHEMTs without Si Sub. Eventually, the study device depicted higher BV performance compared to other C-doped GaN HEMT devices. This suggests that the designed GaN MISHEMTs device could effectively be used in power semiconductor devices with optimum performance.

Characteristics of β-(AlxGa1−x)2O3/Ga2O3 dual-metal gate modulation-doped field-effect transistors simulated by TCAD

β-(AlxGa1−x)2O3/Ga2O3 modulation-doped field-effect transistors (MODFETs) with a dual-metal gate (DMG) architecture are designed, and the electrical characteristics of the DMG device are investigated in comparison with the single-metal gate (SMG) device by the Technology Computer-Aided Design (TCAD) simulation. The results demonstrate that the DMG MODFETs possess a superior transconductance (gm), current gain cut-off frequency (fT), and power gain cut-off frequency (fMAX) than those of SMG transistors, which is attributed to the regulated channel electric field by a DMG structure. With a gate length of 0.1 μm, the peak values of fT/fMAX of the designed DMG MODFET are obtained as 48.6/50.6 GHz, respectively. Moreover, a comprehensive thermal analysis is conducted between the SMG and DMG devices under steady-state and transient conditions. The DMG MODFET exhibits a lower maximum temperature than the SMG counterpart due to the reduced channel electric field, each subjected to the same power dissipation. This finding underscores the potential of the β-(AlxGa1−x)2O3/Ga2O3 MODFET with the DMG architecture as a promising approach for high-power radio frequency operations.

Study of the mechanism of single event burnout in lateral depletion-mode Ga2O3 MOSFET devices via TCAD simulation

This study investigates the sensitive region and safe operation voltage of single-event burnout (SEB) in lateral depletion-mode Ga2O3 MOSFET devices via technology computer aided design simulation. Based on the distribution of the electric field, carrier concentration, and electron current density when SEB occurs, the radiation damage mechanism of SEB is proposed. The mechanism of SEB in Ga2O3 MOSFET was revealed to be the result of a unique structure without a PN junction within it, which possesses gate control ability and exerts a significant influence on the conduction of the depletion region.

Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer

In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.

Analysis of Mechanical Stress on Fowler-Nordheim Tunneling for Program Operation in 3D NAND Flash Memory

This study investigated the relationship between mechanical stress and program efficiency in three-dimensional (3D) NAND flash memory devices. A stacked memory array transistor (SMArT) 3D NAND flash structure was modeled using a technology computer-aided design (TCAD) simulation. The mechanical stress distribution in the device depended on the deposition temperature (TD) of the constituent material. In particular, the TD of tungsten (TD,W) dominated the mechanical stress. The tensile stress on the polycrystalline silicon (poly-Si) channel increased as the TD,W decreased, and the compressive stress on the tunneling oxide (Tox) decreased. Consequently, the barrier height between Tox and poly-Si, and the effective electron mass decreased as the electric field in the Tox increased. These changes significantly increased the Fowler-Nordheim (FN) tunneling process and program efficiency, indicating the crucial performance of 3D NAND flash. Moreover, the mechanical stress caused by the differences in TD,W improved the program efficiency at a lower program voltage (VPGM). Therefore, a change in the mechanical stress based on decreasing TD,W improved the program efficiency through a higher FN tunneling process.

Two- and Three-Dimensional Recrystallization of Discrete Amorphous in C3H5-Molecular-Ion-Implanted Silicon Surface Analyzed by TCAD Simulation

Technology computer-aided design (TCAD) kinetic Monte Carlo simulations revealed the unique recrystallization processes of discrete amorphous regions connected to a buried amorphous layer in a C3H5-molecular-ion-implanted silicon (Si) substrate. The faithful simulation models show that the discrete amorphous regions are first recrystallized two-dimensionally in the lateral direction from both sides and separated from the buried amorphous layer. Then, the separated discrete amorphous regions are recrystallized three-dimensionally in the lateral and vertical directions from both sides and the bottom. We found that the first two-dimensional recrystallization of discrete amorphous regions is caused by the retardation of solid-phase epitaxial growth at the Si substrate surface and near the buried amorphous layer. We also found that the large (small) discrete amorphous regions require a long (short) two-dimensional recrystallization before separating from the buried amorphous layer. The transition point in the recrystallization dimension can be determined from the lateral recrystallization length and the equivalent radius of discrete amorphous regions.

A 3-D GaAs-based Hall sensor design with dual active layers structure

A fully integrated 3-D Hall magnetic sensor with dual active structure was proposed. Results by technology computer-aided design simulation show that the proposed sensor provides a doubled magnitude improvement in sensitivity of vertical magnetic field direction and maintains a good level sensing of horizontal magnetic field direction compared with the sensor with single active layer. The designed sensor was fabricated by wet etching process and a method of preparing Ohmic contacts on the "pseudo-sidewalls" is proposed. The measurements show that the non-linearity does not exceed 0.5% and a voltage sensitivity of up to 0.046 T−1, which matches the simulation results. The proposed sensor boasts a simplified structure that allows for fabrication using different layers only through a planar process, which makes it more conducive to the integration of devices and systems.

Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory

This paper presents an innovative approach to alleviate Z-interference in 3D NAND flash memory by proposing an optimized confined nitride trap layer structure. Z-interference poses a significant challenge in 3D NAND flash memory, especially with the reduction in cell spacing to accommodate an increased number of vertically stacked 3D NAND flash memories. While the confined nitride trap layer device designed for complete isolation of the trapping layer in three dimensions effectively reduces Z-interference, the results showed substantial variations based on the confined structure. To clarify this issue, we compared three distinct confined nitride trap layer structures and investigated their impact on Z-interference. Our findings indicate that the rectangle structure exhibited the most significant mitigation, implying that differences in the electric field applied to the poly silicon channel, which is influenced by the structure, and the increase in effective channel length are effective strategies for alleviating Z-interference. The proposed structure undergoes a comprehensive examination through technology computer-aided design (TCAD) simulations. Additionally, we introduce a practical process flow designed to minimize Z-interference.

Design and 3D TCAD simulation of a novel floating-electrode silicon pixel detector

A novel floating-electrode silicon pixel detector has been proposed. The novel configuration of the floating electrode in the silicon pixel detector reduces the size of the collecting cathode and decreases both the capacitance and leakage current of the detector compared to the conventional silicon pixel detector. For the design, we used a 200 × 200 µm2 detector as the model to analyze the impact of varying numbers of floating rings on the electrical performance [Wu et al., AIP Adv. 11(2), 025315 (2021)]. We used Technology Computer Aided Design simulation to compare and analyze the simulated electric field, potential, capacitance, and breakdown voltage of the detector. The results show that decreasing the gap-to-width ratio of the floating electrode, as well as increasing the quantity of floating rings, enhances the detector’s performance.

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

AbstractIn the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance.

Simulation Research on High-Voltage β-Ga2O3 MOSFET Based on Floating Field Plate

The simulation model of a depletion-mode (D-mode) β-Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET) is constructed by Silvaco ATLAS technology computer-aided design (TCAD) simulation, which employs an epitaxial drift layer grown on a sapphire substrate. On this basis, the floating field plate (F-FP) structure based on the gate-pad-connected field plate (P-FP) is proposed to improve the breakdown characteristics of the device, which is easy to be prepared. The working principle of F-FP is investigated with the help of the device with one F-FP. Based on the principle that the number of floating field plates is increased on an optimized floating field plate structure. Subsequently, the devices with two and three floating field plates are simulated in turn, and the optimal structural parameters of the three F-FPs device are finally obtained, and the breakdown voltage is 3800 V at this time. In addition, it is found that the device breakdown voltage is increased by approximately 500–600 V for each additional floating field plate.