Technology Computer-aided Design Simulation Research Articles

A comprehensive investigation of total ionizing dose effects on bulk FinFETs through TCAD simulation

This study investigates the total-ionizing-dose (TID) effect on bulk FinFETs under ON-state irradiation bias, aiming to analyze the cause and physical mechanism of irradiation enhancement effects. Utilizing technology computer-aided design (TCAD), for the first time, we find that parasitic transistors located at the apex of the shallow trench isolation (STI) oxide significantly contribute to the subthreshold degradation of the device, leading to a notable increase in off-state leakage current. Furthermore, under identical irradiation bias conditions, narrower-fin and shorter-channel devices exhibit a more pronounced increase in off-state leakage current. This escalation is attributed to an increased amount of trapped charge in the STI oxide and the elevated electrostatic potential of the punch-through stop (PTS) layer, respectively. Additionally, higher drain voltage reduces the threshold voltage of the STI parasitic transistors, resulting in an increased off-state current as drain voltage rises. In summary, investigating the TID effect of bulk FinFETs under ON-bias is crucial, as it can provide theoretical support for reinforcing nanostructured devices against irradiation-induced degradation.

Experimental-Modeling Framework for Identifying Defects Responsible for Reliability Issues in 2D FETs.

In this work, a self-consistent method is used to identify and describe defects plaguing 300 mm integrated 2D field-effect transistors. This method requires measurements of the transfer characteristic hysteresis combined with physics-based modeling of charge carrier capture and emission processes using technology computer aided design (TCAD) tools. The interconnection of experiments and simulations allows one to thoroughly characterize charge trapping/detrapping by/from defects, depending on their energy position. Once the trap energy distribution is extracted, it is used as input in transient TCAD simulations to reproduce the experimental hysteretic transfer characteristics. Our method is widely applicable to any 2D channel/gate stack combination. Here, it is demonstrated on FAB-integrated devices with AlOx/HfO2 gate oxide. A Gaussian-approximated defect band in the AlOx interlayer centered at a position of about 0.1 eV below the conduction band minimum of WS2 is obtained. Based on this energy position, it is concluded that aluminum interstitial and oxygen vacancies are the defects giving rise to the observed hysteresis. These defects are detrimental to the stability of the studied devices as they are easily accessible by channel carriers during on-state operation. A prominent hysteresis obtained during measurements is consistent with this conclusion.

The mechanism of degradation and failure in NiO/ β -Ga2O3 heterojunction diodes induced by the high-energy ion irradiation

This work investigated the single-event effects (SEE) of NiO/β-Ga2O3 heterojunction diodes (HJDs) irradiated by 1.86 GeV tantalum ions with linear energy transfer over 80 MeV cm2/mg. The HJDs exhibited radiation responses with the early single-event leakage current (SELC) degradation until the fatal single-event burnout (SEB) failure, which was far below their breakdown voltages. Meanwhile, the surface morphology revealed the SELC damage expressed as burnout of topside NiO and metal stacks, while the SEB damage was observed as a burned hole in the β-Ga2O3 epitaxial layer. According to technology computer aided design simulations, the thicker p-type region in HJDs could further alleviate the electric field crowding effect exacerbated by the heavy-ion strike because of the extension of charge distribution in the p-type region. The SEB threshold was raised to 250 V by thickening the NiO layer to 300 nm. As for the SELC degradation process along with the burnout of topside stacks in HJDs, we supposed the probable reason was the intolerance of NiO to the high electric field under the SEE. This paper analyzed the SEE mechanism in β-Ga2O3 diodes and paved the way for heavy-ion irradiation hardening.

Development of UV light-emitting diodes based AlGaN/GaN heterojunction utilizing thermal oxidation annealing

Ultraviolet (UV) irradiation has a significant impact on enhancing the performance of sensors. Currently, there is still an urgent need for devices that are simple and easy to fabricate. In this work, a cost-effective and convenient method was employed to fabricate a UV light emitting diode. A four-inch silicon based AlGaN/GaN heterojunction substrate was used. The Ni/Au (20/20 nm) layer was deposited on the AlGaN barrier layer, followed by thermal oxidation to prepare the UV diode. The diode annealed in oxygen can emit UV light at a wavelength of 365 nm and is visible, and no light is emitted from the device in nitrogen annealing. The I–V and C–V characteristics of the device are tested to explore the mechanism. Transmission electron microscopy and technology computer aided design simulation methods were used to analyze the device luminescence mechanism.

Self-bias Mo–Sb–Ga multilayer photodetector encompassing ultra-broad spectral response from UV–C to IR–B

Achieving an ultra-broad spectral response in a self-bias detector is a formidable challenge that persists in optoelectronics that necessitates innovative solutions. We propose a unique ultra-broadband photodetecting device, utilizing a multilayer structure comprising Molybdenum Di-sulfide (MoS2), Antimony Tri-selenide (Sb2Se3), and Gallium Nitride (GaN), which exhibits the unique capability of detecting photons without applied bias. The fabricated device demonstrates exceptional sensitivity to a wide range of illumination wavelengths, spanning from ultraviolet–C (UV–C) to infrared–B (IR–B). The design detector displays the highest photo-responsivity of 665 mAW−1 in photovoltaic mode and 3.89 × 105 mAW−1 in photoconductive mode. The designed detector also exhibits a minimal dark current of 90 nA and an extremely weak signal detection capability of ∼12 femto watt-hertz−1/2 at 6 V bias. Additionally, the thermal stability of the MoS2-Sb2Se3-GaN (Mo-Sb-Ga) multi-layer-based self-bias detector was explored. Under the self-bias conditions, the photodetector exhibits a stable behavior up to 250°C with a peak responsivity of 635 mAW−1. The thermal durability of the self-bias ultra-broadband photodetector indicates excellent potential for developing futuristic optoelectronic devices. Further, the performance of the developed detector was examined using Technology Computer-Aided Design (TCAD) simulations, providing valuable insights into the device behavior and the transport of photo-generated carriers, enhancing our understanding of the device operation and enabling performance optimization for diverse applications.

Measurements and TCAD simulations of guard-ring structures of thin silicon sensors before and after irradiation

The developing of high performing silicon detectors for particle tracking in the next generation of high-energy physics experiments at future colliders (e.g., HL-LHC, FCC) able to operate efficiently up to very high fluence (∼1⋅10171MeVneq/cm2) is of the utmost importance. In order to sustain high voltage values with minimum leakage current injection into the core region of the sensor, the design and optimisation of the Guard-Ring (GR) protection structure is crucial, especially when small substrate thicknesses are used. In a recent R&D batch produced at Fondazione Bruno Kessler (FBK) in the framework of the “eXFlu” project - INFN CSN5 grant for Young Researchers, different optimisation studies of GR structures for thin substrates (45, 30, 20 and 15μm) up to high fluence (2.5⋅10151MeVneq/cm2) have been addressed. These have been enabled thanks to ad-hoc advanced Technology CAD (TCAD) modelling of different GR design strategies, accounting for the comprehensive bulk and surface radiation-induced damage effects, and an extensive test campaign on such GR structures, both before and after irradiation. In this paper the validation of the development framework of the various GR design options before and after irradiation is presented.

High-density 3D-NAND flash with dual-string select line (D-SSL)

In this study, high-density 3D-NAND flash memory is proposed. Using D-SSL, lateral shrink of cell area can be achieved by distinguishing two strings in a word-line (WL). We verify erase/program and read characteristics using technology computer-aided design (TCAD) simulations with rigorous calibrated condition. The proposed high density NAND flash has normally-on state SSLs through additional process and electrical treatment. In the conventional reference NAND flash, the cell string connected to the bit-line (BL) is distinguished by WL cut (WLC). On the other hand, in the proposed high density NAND flash, the cell string is selected by utilizing the normally-on state SSLs using trapped hole and doped arsenic at the intersection of SSL1 and SSL2. Compared with the conventional scheme, the proposed D-SSL exhibits almost same erase/program and read characteristics. Consequently, the proposed D-SSL scheme can increase memory density with reduced number of WLCs by distinguishing strings using D-SSL.

Aggravated NBTI reliability due to hard-to-detect open defects

FinFET technology has become an attractive candidate for high-performance and power-efficient applications. In the other hand, the behavior of FinFET devices is influenced by self-heating effect (SHE) due to its 3D structure, low thermal coupling and quantum confinement effect, among others. SHE degrades the device’s performance and could worsen reliability mechanisms like NBTI. In addition, some hard-to-detect open defects in FinFET based-circuits using logic gates designed with multi-fin and multi-finger techniques may escape the test and present abnormal static currents, which may increase the impact of self-heating effect and make the NBTI degradation more severe. Hence, it is crucial to accurately determine the temperature profiles of those chips passing the test and presenting abnormal static currents. This paper investigates the reliability of chips passing the test with abnormal static currents using Sentaurus Technology Computer-Aided Design (TCAD). FinFET transistors are calibrated with Intel 14-nm FinFET technology. Our TCAD simulation framework determines accurately the temperature and NBTI degradation. Using the TCAD information, the device degradation over time can be predicted. Moreover, the delay penalization of a critical logic path of an ISCAS benchmark circuit is investigated. The delay penalization of logic paths, attributed to the defect and NBTI, is analyzed with varying logic depths, emphasizing the importance of addressing critical paths with different logic depths. Our study leads to new considerations for improving the prediction of circuit reliability and taking countermeasures.

Multi-objective optimization and inverse design of complementary field-effect transistor using combined approach of machine learning and non-dominated sorting genetic algorithms for next-generation semiconductor devices

Complementary field-effect transistors (CFETs), which are structures in which different types of transistors are vertically stacked with a shared control gate, are being focused on for continuing to satisfy Moore's law by overcoming the limitations in pitch scaling. The structures of semiconductor devices become more complex as technology node shrinks, and interrelated multivariate parameters increase. In addition, predicting problems and proposing solutions by identifying complex patterns within extensive data collected for emerging semiconductor designs pose significant computational challenges and are inherently difficult. As a breakthrough in design technology co-optimization for advanced devices, this study developed a novel optimization framework integrating technology computer-aided design simulations, machine learning, and non-dominated sorting genetic algorithms. The developed framework provides unbiased optimal solutions, even in a high-dimensional objective space, while considering the tradeoff relationships between multiple variables. In addition, it enables inverse design to identify the design parameters of devices that satisfy specific electrical performance criteria using only a forward model, while achieving an error rate of less than 2%. Using this framework, we analyzed the operational mechanism of CFETs by comparing the inverse designs of various devices. This novel approach is particularly important when the design space is complex and extensive and is well suited for developing devices that emerge with technological advancements in the semiconductor industry.

Field management in NiO x /β-Ga2O3 merged-PIN Schottky diodes: simulation studies and experimental validation

In recent years, p-type NiO x has emerged as a promising alternative to realize kilovolt-class β-Ga2O3-based PN junction diodes. However, only a handful of studies could realize β–Ga2O3-based unipolar diodes using NiO x as a guard ring or floating rings. In this work, we investigate the device design of NiO x /β-Ga2O3 unipolar diodes using the technology computer aided design simulations and experimental validations. We show that a systematic electric field management approach can potentially lead to NiO x /β-Ga2O3 heterojunction unipolar diode and offer enhanced breakdown characteristics without a severe compromise in the ON-state resistance. Accordingly, the NiO x /β-Ga2O3 heterojunction diode in the merged-PIN Schottky configuration is shown to outperform the regular Schottky diode or junction barrier Schottky diode counterpart. The analysis performed in this work is believed to be valuable in the device design of β-Ga2O3-based unipolar diodes that use a different p-type semiconductor candidate as guard rings and floating rings.

(Invited) A Neural Compact Model Based on Transfer Learning for Organic FETs

Organic field-effect transistors (organic FETs) exhibit highly non-linear electrical characteristics due to their distinctive transport mechanism manifested by thermally-assisted hopping via localized states randomly distributed in both energy and space domains. This feature impedes the establishment of an analytical compact model. In this context, we present an approach to adopt artificial neural networks (ANN) for the development of a compact model, namely a neural compact model, by exploiting the powerful ability of the ANN to describe a non-linear function accurately. In addition, we evaluate the knowledge transfer method to reduce learning time and improve accuracy even when the data is scarce and costly. By technology computer-aided design simulation, we constructed a dataset of electrical characteristics of organic FETs with Gaussian disorder which is calibrated to the experimental measurement. Subsequently, we constructed and compared neural compact models based on conventional deep learning and transfer learning. We showed that the neural compact model with transfer learning provides an equivalent accuracy at a shorter modeling time. A complex dependence on the gate voltage, drain voltage, and temperature is successfully modeled over a wide range of operation regimes and temperatures.

Linearity and noise evaluation based analysis of extended source heterojunction double gate tunnel FET

This research work evaluates a performance analysis of heterostructure (SiGe/Si) double gate extended source Tunnel FET (Hetero-ES-TFET) to enhance the analog performance, linearity and noise performance. At the source-channel junction, a Hetero-ES-TFET's source is extended into the channel to increase point and line tunneling in the device. The Hetero-ES-TFET exhibits a high ION/IOFF of 3.57 × 1012 and a maximum cut off frequency fT of 54.19 GHz for optimization of device structural parameters. This analysis is conducted using a calibrated SILVACO, technology computer-aided design (TCAD) simulator. The proposed structure includes evaluation of linearity and noise performance characteristics. Furthermore, a linearity analysis as a figure of merit was conducted for the proposed device under study, including different parameters such as 3rd order intermodulation distortion point (IMD3), 3rd order intermodulation intercept point (IIP3), 2nd and 3rd order voltage intercept point (VIP2 and VIP3). The proposed Hetero-ES-TFET has achieved an incredibly high ON current and low threshold voltage. The effect of increasing source width has been examined in this work while sub-threshold swing (SS) remains unchanged during the analysis. There is an improvement in threshold voltage and ION/IOFF value by using silicon-germanium (SiGe) as a source material.

Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism.

This study examines the memory and read delay characteristics of quasi-nonvolatile memory (QNVM) devices operating in a positive feedback mechanism through technology computer-aided design simulation. The QNVM devices exhibit a rapid operation speed of 5 ns, a significant sensing margin of approximately 8.0 μA, and a retention time of around 1 s without any external bias. These devices showcase an exceptionally brief read delay of 0.12 ns. The energy band diagrams during the memory operation are analysed to clarify the factors influencing the read delay. The write and standby conditions modulate the potential barrier height during the standby operation, thereby affecting the read delay. Moreover, the shorter rising time causes the reduction of the read delay. This study demonstrates that the QNVM device has the potential to resolve energy consumption and speed issues in nonvolatile memory devices.

Statistical analysis of vertically stacked nanosheet complementary FET based on polycrystalline silicon with multiple grain boundaries

In this study, a complementary field-effect transistor (CFET) based on a polycrystalline silicon (poly-Si) stacked-nanosheet (NS) structure with a grain boundary (GB) is designed and analyzed using a technology computer-aided design (TCAD) simulation. The advantage of the CFET using a poly-Si is that the active cell region can be reduced by 50 % because the p-type transistors are vertically stacked on the n-type transistors. In addition, it is possible to replace the conventional CMOS process and fabricate a three-dimensional vertically stacked structure at a low cost. To consider the effect of the GB in poly-Si, we assumed that there is a single GB at the center of the body region. By optimizing the geometrical parameters of the proposed CFET, the transfer characteristics of the NMOS and PMOS transistors, such as the threshold voltage (Vth), on current (Ion), off current (Ioff), and subthreshold swing (SS), are symmetrical. The proposed CFET demonstrated a superior logic performance of NML = 0.299 V and NMH = 0.297 V at an operation voltage of VDD = 0.65 V. To consider random GBs in the poly-Si, we assumed that five GBs existed in the proposed CFET, and the variation in CMOS logic inverter characteristics are statistically analyzed. As a result, the RSDs for Vm of the NMOS and PMOS transistors are 2.067 % and 0.293 %, and the RSDs of the pull-down delay time (tpHL) and pull-up delay time (tpLH) are 5.320 % and 3.244 %, respectively. An acceptor-like traps with high trap density are dominant in the proposed CFET, and this trend is similar across the 1024 samples. Nevertheless, most of the differences are within 5 % and the proposed CFET exhibited stability against GBs and the potential to replace the conventional CMOS logic inverters.

Nonlinear behaviors in back-gate effects of FDSOI MOSFETs at cryogenic temperatures

In this work, we systematically investigate the DC performance of fully depleted silicon-on-insulator (FD-SOI) MOSFETs at both room and cryogenic temperatures as low as 77 K. The influences of back-gate bias on normal and flip-well devices are measured and analyzed. Both types devices display non-linear behaviors when adjusting the back-gate voltage at cryogenic temperatures. Notably, the non-linear effects are more prominent in normal-well devices. The possible reasons are analyzed and verified by technology computer aided design simulation, suggesting that normal-well devices are more susceptible to the formation of depletion regions between the buried oxide layer and the well. This phenomenon disrupts the linearity of the back-gate effect. This research contributes to understanding and characterizing of the back-gate effects in cryogenic environments and holds potential for high-performance computing applications.

Tunable Band‐to‐Band Tunneling and Conducting Path Transition in Local‐Control‐Gate Heterostructure Transistor

AbstractTransition metal dichalcogenide (TMD) material‐based heterostructures have exhibited great potential for building advanced architectures in novel logic devices. A local‐control‐gate (LCG) transistor based on MoTe2/MoS2 heterostructure is fabricated and analyzed, illustrating its tunable electrical characteristics and achieving band‐to‐band tunneling (BTBT) enhancement with an improved peak‐to‐valley current ratio (PVCR) value of 3.04. Compared to the basic dual‐gate tunnel field‐effect transistor (TFET) structure, adding LCG at the bottom not only isolates defect‐induced doping effects from the deposition of top gate dielectrics, but also paves the way for broader applications in multivalued logic and artificial intelligence. Aiming to further verify the operating mechanism of conducting path transition and electrical characteristic trends, commercial technology computer‐aided design (TCAD) is systematically employed assisted by density functional theory (DFT). So that the transition of conducting paths in the heterostructure channel including interlayer quantum effects can be visibly demonstrated while applying various voltages to the LCG. In summary, this work highlights the feasibility of a new LCG structure with tunable electrical characteristics and presents DFT‐assisted TCAD simulations for effective verifications.

Energy-Performance Assessment of Oscillatory Neural Networks Based on VO2 Devices for Future Edge AI Computing.

Oscillatory neural network (ONN) is an emerging neuromorphic architecture composed of oscillators that implement neurons and are coupled by synapses. ONNs exhibit rich dynamics and associative properties, which can be used to solve problems in the analog domain according to the paradigm let physics compute. For example, compact oscillators made of VO2 material are good candidates for building low-power ONN architectures dedicated to AI applications at the edge, like pattern recognition. However, little is known about the ONN scalability and its performance when implemented in hardware. Before deploying ONN, it is necessary to assess its computation time, energy consumption, performance, and accuracy for a given application. Here, we consider a VO2-oscillator as an ONN building block and perform circuit-level simulations to evaluate the ONN performances at the architecture level. Notably, we investigate how the ONN computation time, energy, and memory capacity scale with the number of oscillators. It appears that the ONN energy grows linearly when scaling up the network, making it suitable for large-scale integration at the edge. Furthermore, we investigate the design knobs for minimizing the ONN energy. Assisted by technology computer-aided design (TCAD) simulations, we report on scaling down the dimensions of VO2 devices in crossbar (CB) geometry to decrease the oscillator voltage and energy. We benchmark ONN versus state-of-the-art architectures and observe that the ONN paradigm is a competitive energy-efficient solution for scaled VO2 devices oscillating above 100 MHz. Finally, we present how ONN can efficiently detect edges in images captured on low-power edge devices and compare the results with Sobel and Canny edge detectors.

Investigation of the forward gate leakage current in pGaN/AlGaN/GaN HEMTs through TCAD simulations

In this study, we examined the gate leakage characteristics of normally off pGaN/AlGaN/GaN HEMTs through a simulation study. The Fowler Nordheim Tunneling (FNT) mechanism mainly contributes to the gate leakage process as indicated by the Technology Computer-Aided Design (TCAD) simulation. However, at low bias, the FNT undercalculates the leakage current since the electric field is low in this region. This extra leakage current component at this low bias region can be attributed to the presence of surface traps. Trap-assisted tunneling current along with the FNT current can explain forward leakage characteristics of the pGaN HEMTs. Our TCAD simulations were matched with the experimental data for five devices from four different research groups to support this claim. Using TCAD simulations, we have been able to analyze several device parameters including the various potential drops inside the gate stack structure. We were able to identify some of the trap levels and compare them to the dominant defects expected to be present in the pGaN cap layer. Furthermore, we studied the effects of different device parameters on the gate leakage process in the pGaN HEMT.

3.3 kV-class NiO/β-Ga2O3 heterojunction diode and its off-state leakage mechanism

This Letter demonstrates a high-performance 3.3 kV-class β-Ga2O3 vertical heterojunction diode (HJD) along with an investigation into its off-state leakage mechanism. The vertical β-Ga2O3 HJD with field plate assisted deep mesa (FPDM) termination was fabricated using a self-aligned technique to etch the deep mesa to a depth of 9 μm, thereby reducing electric field crowding at the anode edge. In addition, a thick dielectric is deposited to fill the trench, facilitating the utilization of a field plate to further reduce the electric field at the anode edge. TCAD (Technology Computer Aided Design) simulations show significant suppression of electric field crowding at the anode edge. The fabricated HJD exhibits a high current swing of ∼1010 over a temperature range from 25 °C to 175 °C. The specific on-resistance (Ron,sp) is extracted to be 3.9 mΩ cm2, and the breakdown voltage is 3.42 kV with the FPDM termination. These conduction and blocking characteristics lead to a high power figure of merit of 3 GW/cm2, which is one of the highest among multi-kilovolt β-Ga2O3 diodes. Furthermore, the off-state current leakage mechanism of the HJD under a reverse bias up to 2000 V was investigated. The fitted results reveal that the leakage current is primarily dominated by Poole–Frenkel (PF) emission, with the trap level of PF extracted to be 0.36 eV below the conduction band of NiO.

Understanding of multiway heat extraction using peripheral diamond in an AlGaN/GaN high electron mobility transistor by electrothermal simulations

High-power operation of high electron mobility transistors (HEMTs) is limited due to a variety of thermal resistances in HEMT devices that cause self-heating effects (SHEs). To reduce SHEs, diamond heat spreaders integrated in the device have proven efficient in extracting heat from the device. In this report, we use electrothermal technology computer-aided design simulations to demonstrate a qualitative understanding of multiway heat extraction utilizing diamond heat spreaders to improve HEMT thermal performance at high DC output power densities (∼40 W mm−1). The impact of each heat extraction pathway is understood while considering the thermal boundary resistance between the diamond/GaN heterointerface and optimization of the GaN buffer layer thickness. Using these findings, we simulate an AlGaN/GaN HEMT device operating at 40 W mm−1 DC output power and demonstrate significant reduction in the temperature.