Technology Computer-aided Design Simulation Research Articles

Bipolar nonlinear photo-controlled thyristor with variable-resistance effect

With the advancement of artificial intelligence technology, volatile memristors emulating neurons have gained widespread attention in the field of neuromorphic computing. This paper proposes a volatile bipolar nonlinear photo-controlled thyristor (PCT) compatible with CMOS technology, providing a reference for the structural design of silicon-based neurons. Technology computer aided design (TCAD) simulation is used to analyze the variable-resistance mechanism and photoelectric effect of the device. The PCT fabricated based on the 0.18 μm Bipolar-CMOS-DMOS (BCD) process has two electrode ports. When a fixed amplitude bipolar periodic excitation signal is applied to the anode of the device, the output current and voltage of PCT show nonlinear changes at the same time due to the negative differential resistance effect, satisfying the fundamental requirements of an oscillatory neuron. By further coupling the photoelectric effect, the device can achieve continuous switching from high-resistance state to low-resistance state under light source driving conditions. Finally, the transient data of PCT is extracted and the hysteresis loop is fitted, which verifies the accuracy of the device theory and model simulation.Index Terms—CMOS technology, variable-resistance effect, photoelectric effect, TCAD simulation.

Hardmask engineering by mask encapsulation for enabling next generation reactive ion etch scaling

Miniaturization and scaling of semiconductor devices require development of innovative techniques to sustain advancements. A promising trend is the migration from 2D to 3D device architectures that necessitate fabrication of high-aspect-ratio narrow features through layers of different materials. Reactive ion etching can achieve this but poses unique challenges due to the requirement of etch chemistries capable of etching dissimilar materials with varying etch rates while maintaining high productivity. The choice of hardmask is also crucial, as it plays a critical role in determining efficacy of the etch process and the final shape of the feature being etched. To address these challenges, we introduce a new concept of hardmask engineering that involves a bilayer hardmask scheme consisting of a patterned conventional hardmask encapsulated with a thin layer of etch-resistant ruthenium (Ru) layer. Experimental results for etching multilayer stacks consisting of alternating pairs of SiO2 and Mo show that this engineered hardmask results in improved hardmask remaining and etch profile with smaller critical dimensions (CDs). Technology computer-aided design simulations with the Ru encapsulation layer on conventional carbon hardmask demonstrate increased poly-Si etch depth with reduced bow CD. This concept can be extended to any semiconductor nanofabrication step involving high-aspect-ratio etching where precise control of CDs is essential in the vertical direction.

Current collapse suppression in AlGaN/GaN HEMTs using dual-layer SiNx stressor passivation

In this work, a dramatic reduction in current collapse is achieved in GaN-based high-electron-mobility transistors (HEMTs) using dual-layer SiNx stressor passivation (DSSP), and the related mechanism is proposed. The SiNx compression neutralizes the inherent piezo polarization caused by the lattice mismatch at the heterojunction and effectively mitigates the peak electric field crowding at the drain-side gate edge, as supported by technology computer-aided design simulation. Thus, the inverse piezoelectric effect is suppressed and the trapped charge density is reduced under high electrical stress. As a result, the current collapse effect can be significantly restrained. Upon pulsing (Vg = −6 and Vds = 20 V), the device with DSSP exhibits a negligible current collapse (∼3%), which is significantly lower than the baseline device (∼34%). Moreover, it shows a one-order-of-magnitude reduction in gate leakage and a significant enhancement in gate stability. These results prove that the DSSP process is an attractive technique to facilitate high-reliability GaN-on-Si HEMTs.

Sensitivity Analysis of Al0.3Ga0.7N/GaN Dielectric Modulated MOSHEMT Biosensor

Emerging and newly proposed devices integrate various materials at different scales (from nano to submicron), which reveals sensor response. Prefab simulation is in great demand to elucidate fundamental biosensor phenomena that are based on transistors. Numerous HEMT-based biosensors have been developed, however, MOSHEMT deserves to be further investigated. The sensitivity analysis with neutral and charged biomolecules is thus carried out in this research using a single gate high-κ dielectric MOSHEMT through Technology Computer Aided Design simulation. The device performance is evaluated through the shift (sensing action) of device parameters like Two-Dimensional Electron Gas, on-current, transconductance, drain current and output conductance due to the immobilization of biomolecules in the cavity created under the gate. For the neutral biomolecule (), the fluctuation in on-current, transconductance, drain current, and output conductance is determined to be 330.3 μA μm−1, 102.0 μS μm−1, 319.0 μA μm−1, and 534.9 μS μm−1, respectively. Positively charged biomolecules were more sensitive to the device than negatively charged ones. Analysis is done on the response to the fill rates of the biomolecules in the cavity. For the vertical, horizontal, and tapered profiles, the transconductance sensitivities are 0.65, 0.17, and 0.32 and the drain current sensitivities are 0.25, 0.16, and 0.27 at the lowest fill (25%). In light of this, the AlGaN/GaN dielectric modulated MOSHEMT assures that the device can be used in sensitive intelligent biomedical applications.

Low-Voltage Operated High DC Gain Amplification Stage Based on Large-Area Manufacturable Amorphous Oxide Semiconductor Thin-Film Transistor

The industry-standard amorphous metal–oxide–semiconductor (AOS) thin-film transistor (TFT) technology is demonstrated for making low-voltage high intrinsic gain devices. It is revealed by the technology computer-aided design (TCAD) simulation that, without need of making Schottky barrier contacts, large output resistance and high intrinsic gain can be achieved in a subthreshold regime for AOS TFTs. It is further proved by the measurement results with the fabricated AOS TFT from a Gen-4.5 manufacturing line. A simple single-stage zero- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{V}_{\text{GS}}$</tex-math> </inline-formula> load amplifier is implemented as a proof of concept, achieving a voltage gain larger than 50 for weak signal detection at a supply voltage of 5 V.

Metal–Ferroelectric–Semiconductor Tunnel Junction: Essential Physics and Design Explorations

The essential physics of the ferroelectric tunnel junction (FTJ) is assessed with technology computer-aided design (TCAD) simulations and analytical models. With experimental data calibrations, a TCAD simulation framework including electrostatic potentials, ferroelectric (FE) polarizations, and nonlocal tunneling is built. Full regions of the FTJ operations, including the read/write, are then explored. Key parameters such as the memory state threshold voltages ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {mth}}$ </tex-math></inline-formula> ) and the region boundary voltages are defined, and their model formulations are developed. With the essential physics captured, FTJ figure-of-merits (FoMs) are accessed with not only tunneling electroresistance (TER), but also power consumption. Design parameters from FE layer thickness, polarizations, and coercive field to silicon doping and metal work functions are studied, with their impacts on key FTJ FoMs evaluated.

Analysis of Hump Effect Induced by Positive Bias Temperature Instability in the Local Oxidation of Silicon n-MOSFETs

In this study, the degradation of the subthreshold swing (S.S.) and the hump effect are observed in the local oxidation of silicon (LOCOS) metal-oxide-semiconductor field-effect transistors (MOSFETs) under short-and long-term positive bias temperature instability tests, respectively. S.S. collapse is considered to be caused by anode hot-hole injection, and the hump effect occurs because the geometric structure from LOCOS isolation forms parasitic transistors on both sides of the channel, which can be verified by a Silvaco Technology computer-aided design (TCAD) simulation. In addition, the body effect measurement method is proposed to elucidate the mechanism of the hump effect for further confirmation of hump formation.

Tunnel Field-Effect Transistor Triggered Silicon-Controlled Rectifier

In this article, a tunnel field-effect transistor (TFET) triggered silicon-controlled rectifier (SCR) device is proposed. A TFET is embedded into the SCR enabling an early carrier’s transportation through the n-well/p-well reverse-biased junction. This accelerates the junction breakdown and helps to establish the SCR’s positive feedback regeneration. The applications of the TFET-triggered SCR (TTSCR) in electrostatic discharge (ESD) protection are explored and the electrical characteristics are investigated. Moreover, the impact of the device structure on the device performance is discussed. The principle of the proposed device is verified using technology computer-aided design (TCAD) simulation. The simulation results show that compared to the prevalent diode-triggered SCR, the proposed device has a small layout area, a low leakage current, and a low overshoot voltage.

Investigation of 4H-SiC UMOSFET Architectures for High Voltage and High Speed Power Switching Applications

A comparative TCAD (Technology Computer Aided Design) simulation study of various 4H-SiC trench gate MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (or U-shaped trench gate MOSFET abbreviated for UMOSFET) architectures for high voltage and high-speed switching applications is reported. The DC (Direct Current) and AC (Alternating Current) characteristics of the different trench gate structures are investigated. Particularly, compared to conventional 4H-SiC UMOSFETs, the breakdown voltage of the UMOSFET having a p-type implanted bottom shield is increased by 44%. However, due to the extra JFET (Junction Field Effect Transistor) region, the specific on resistance also increases by 6%. Furthermore, under 1000 V drain bias, the peak electric field at the bottom oxide of the shielded trench gate is below 0.3 MV/cm. In contrast, the peak electric field of conventional UMOSFETs can be as high as 8 MV/cm, which might cause reliability issues. On the other hand, when the bottom oxide thickness of the trench gate is increased, the UMOSFET exhibits 22% less total gate charge, leading to 76% and 71% shorter switching delay time, compared to conventional UMOSFETs and bottom shield UMOSFETs, respectively. As revealed by the simulation results, the UMOSFETs with the p-type implanted bottom shield or thick bottom oxide are advantageous for high voltage and high-speed power switching applications.

Impact of fin width on nano scale tri-gate FinFET including the quantum mechanical effect

An inversion charge-based threshold voltage model is proposed for 10 nm channel length Tri-gate (TG) FinFET. The variation threshold voltage has been studied with respect to fin width for different fin height and channel length The effect of width quantization has been explained with the help of the quantum mechanical effect (QME). A precise comparison of threshold voltage in terms of classical mechanics and quantum mechanics depicts the presence of width quantization in short channel device. The improvement of the short channel effects (SCEs), like subthreshold swing (SS), drain-induced barrier lowering (DIBL) and threshold voltage roll off have been studied. The impact of channel length to fin width ratio on DIBL and has been examined. The improvement of the SCEs at the same oxide thickness has been observed for high-k dielectric material. The potential and effect of hafnium oxide (HfO2) have been discussed and validated using technology computer-aided design (TCAD) simulation.

Theoretical Modeling of a Temperature-Dependent Threshold-Voltage Shift in Self-Aligned Coplanar IZTO Thin-Film Transistors

Here, we investigate the effect of increasing temperature on threshold voltage (VTH) stability in self-aligned coplanar amorphous indium-zinc-tin oxide (a-IZTO) thin-film transistors (TFTs). An analytical model of the temperature dependency of VTH stability reveals the importance of device geometry and subgap density-of-state (DOS) reductions in highly stable a-IZTO TFTs. The validity of the analytical model is confirmed using experiments and technology computer-aided design simulations to predict quantitative relationships under various shifts in temperatures, subgap DOS, and VTH. The role of hydrogen impurity in performance and VTH stability is also examined. The incorporation of hydrogen in a-IZTO channels improves TFT performance and thermal stability (ΔVTH/ΔT = 3.18 mV/K) due to hydrogen’s role as a passivation center. However, excessive incorporation of hydrogen increases subgap DOS distribution, causing a slight deterioration in thermal stability (ΔVTH/ΔT = 3.31 mV/K). This suggests that hydrogen can be converted from a shallow donor to an acceptor-like deep trap state. Our findings inform future designs of stable oxide semiconductor TFTs in terms of thermal stability in emerging organic light-emitting diode, augmented and virtual reality, memory, logic, and monolithic three-dimensional applications.

Effects of Gamma Irradiation on Switching Characteristics of SiC MOSFET Power Devices of Different Structures

The switching characteristics of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power devices of different structures were experimented after exposure to a gamma irradiation environment. The experimental results for on-state were studied. The comparisons are shown for SiC MOSFET power devices with planar, trench and double trench structures tested for total ionizing dose (TID). A higher degradation of the switching characteristics was observed for the double trench structure. The physical mechanisms for these switching characteristics variations were analyzed. In addition, they were confirmed by technology computer-aided design (TCAD) simulation.

Modulation of Contact Resistance of Dual-Gated MoS2 FETs Using Fermi-Level Pinning-Free Antimony Semi-Metal Contacts.

Achieving low contact resistance (RC ) is one of the major challenges in producing 2D FETs for future CMOS technology applications. In this work, the electrical characteristics for semimetal (Sb) and normal metal (Ti) contacted MoS2 devices are systematically analyzed as a function of top and bottom gate-voltages (VTG and VBG ). The semimetal contacts not only significantly reduce RC but also induce a strong dependence of RC on VTG , in sharp contrast to Ti contacts thatonly modulate RC by varying VBG . The anomalous behavior is attributedto the strongly modulated pseudo-junction resistance (Rjun ) by VTG , resulting from weak Fermi level pinning (FLP) of Sb contacts. In contrast, the resistances under both metallic contacts remain unchanged by VTG as metal screens the electric field from the applied VTG . Technology computer aided design simulations further confirm the contribution of VTG to Rjun , which improves overall RC of Sb-contacted MoS2 devices. Consequently, the Sb contact has a distinctive merit in dual-gated (DG) device structure, as it greatly reduces RC and enables effective gate control by both VBG and VTG . The results offer new insight into the development of DG 2D FETs with enhanced contact properties realized by using semimetals.

Influence of the STI on Single-Event Transients in Bulk FinFETs

The single-event transient (SET) produced by laser irradiation in a bulk FinFET is found to have a large plateau current in the tail. 3D technology computer-aided design (TCAD) simulation results show that the cause of the plateau current is the shallow trench isolation (STI) on both sides of the channel stop of a bulk FinFET. When the bulk FinFET is irradiated by heavy ions or laser, the electron-hole pairs are generated by ionization in the active region and the STI of the device. The electron mobility in the STI is much greater than that of the hole, so the electrons generated in the STI are collected quickly, and the holes are left in the STI. The holes left in the STI generate an electric field and form an electron inversion layer in the channel stop. Under the bias voltage of the drain terminal, the electrons in the source flow to the drain through the electron inversion layer in the channel stop to form a drain current. Since holes can exist in the the STI for more than 100 ns, the drain current caused by the electron inversion layer forms a plateau current at the tail of the pulse. And the plateau current increases as the gate length of the bulk FinFET becomes shorter, and decreases as the fin width of the bulk FinFET becomes larger.

A derivation of the electric field inside MAPS detectors from beam-test data and limited TCAD simulations

Solid semiconductor sensors are used as detectors in high-energy physics experiments, in medical applications, in space missions and elsewhere. Minimal knowledge of the electric field inside the elementary cells of these sensors is highly important for their performance understanding. The field governs the charge propagation processes and ultimately determines the size and quality of the electronic signal of the cell. Hence, the simulation of these sensors as detectors in different analyses relies strongly on the field knowledge. For a certain voltage applied to the cell, the field depends on the specifics of the device's growth and fabrication. The information about these is often commercially protected or otherwise very difficult to encode in state-of-the-art technology computer-aided-design (TCAD) software. In this work, we show that by taking the top-down approach, combining public beam-test data and a very limited public TCAD knowledge, we are able to effectively approximate the 3D electric field function in the pixel cell of one important and widely used example, namely the ALPIDE sensor, for simulating the charge propagation processes. Despite its broad usage worldwide, the ALPIDE field is not available to the community. We provide an effective field function, that adequately describes the sensor behaviour without trying to reconstruct further details about the device or the details behind its processing. We comment on the process by which the effective field function is derived with the help of the Allpix2 software, and on how similar work can be performed for other devices, starting from the same grounds.

Investigation of Gate Induced Drain Leakage in Nanotube and Nanowire: A Comprehensive Study

In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon-nanotube (Si-NT JLFET), SiGe Source/Drain silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET) and conventional nanowire (NW) have been performed using technology computer-aided design simulations. We have also demonstrated that inclusion of SiGe S/D in Si-NT JLFET reduced the OFF-state current by order of [Formula: see text]3 from NT JLFET and by order of [Formula: see text]6 from NW JLFET. The impact of variation of core gate thickness ([Formula: see text], germanium (Ge) content [Formula: see text], and location of SiGe in source and drain regions of the S/D Si-NT JLFET have been studied from the GIDL perspective. We found that SiGe S/D Si-NT JLFET exhibits impressively high [Formula: see text]/[Formula: see text] ratio [Formula: see text]10[Formula: see text] with reduced lateral band-to-band tunneling (L-BTBT)-induced GIDL than the conventional nanowire device. The is due to SiGe S/D that creates a energy valence band discontinuity at source drain interfaces which limits the flow of electrons from channel to drain region in the OFF-state.

String-level compact modeling for dynamic operation and transient analysis of 3D charge trapping flash memory

In this article, we propose a string-level compact model, which is based on accurate and seamless channel electrostatic potential, for dynamic operation of 3D charge trapping flash (CTF) memory. First, we introduce a unit cell model for 3D CTF memory structure based on a conventional BSIM-CMG model using an extended netlist of equivalent circuits which describe the gate-all-around (GAA) structure composed of a metal gate, a blocking oxide, a charge trapping layer, and a tunneling oxide. Then, a string-level compact model is proposed, implying three advantages of inter-cell behaviors, seamless channel potential and process variation. To enhance the accuracy of the model behavior, extended model parameters are extracted showing good agreement with experimental data, such as I-V characteristics, program/erase speed, and incremental step pulse programming (ISPP). Furthermore, to predict channel electrostatic potential more precisely, we verify simulation program with integrated circuit emphasis (SPICE) simulation results of positively and negatively boosted channels comparing them with technology computer-aided design (TCAD) simulation results. Finally, we demonstrate that the proposed model can be efficiently applied to circuit simulation for analysis of the disturbance or failure mechanism and would equip the circuit designers and system architects with an effective tool for design optimization of 3D CTF memory devices.

Feasibility and equivalence analysis of transient dose rate effect simulation by pulsed laser in level-shifting transceiver and TCAD simulation on its ESD circuits

Compared to linear accelerators, pulsed lasers have the characteristics of high efficiency, low cost, stable pulse output, and low environment interference for researching the transient dose rate effect (TDRE) on semiconductor devices. In this paper, pulsed laser radiation experiments are performed on a level-shifting transceiver. The experimental results are consistent with the results of the transient γ-ray radiation experiment, demonstrating the feasibility of using the pulsed laser in TDRE research on the level-shifting transceiver. This paper obtains theoretical and experimental conversion factors (CFs) through theoretical analysis and equivalency of the peak photocurrents, which are measured in pulsed laser and transient γ-ray radiation experiments. The CF results from the two approaches are within 7% of each other. In pulsed laser radiation experiments, an uncommon phenomenon is found. At the I/O (Input/Output) ports of the level-shifting transceiver, a trend of a positive photocurrent followed by a negative pulse is observed. A hypothesis is proposed that this photocurrent is produced by the turn-on and turn-off of the parasitic PNP (Positive-Negative-Positive) transistors in electrostatic discharge circuits at the level-shifting transceiver I/O ports. In addition, this hypothesis is verified by TCAD (Technology Computer Aided Design) simulations.

Modeling of Stacking Faults in 4H-SiC n-Type Epilayer for TCAD Simulation

Current–voltage characteristics of an n-type 4H-silicon carbide (SiC) epilayer containing a stacking fault (SF) were analyzed using a technology computer-aided design (TCAD) simulation. In the simulation, the SF was modeled by a quantum well (QW) formed in the conduction band, which traps electrons and induces a potential barrier. The simulation analysis clarified that the electron conductance in the n-type epilayer containing a SF was dominantly determined by the potential barrier height. Based on this insight and the experimental results obtained from our previous study, the energetic depth and width of the QW in the conduction band were deduced for four types of SFs. The temperature dependence of the experimental current–voltage characteristics of Schottky barrier diodes (SBDs), containing the SF, was effectively reproduced by adopting the deduced QW depth and width, proving the feasibility of the proposed simulation model quantitatively predicting the impacts of SFs on SiC unipolar device performances.

Machine Learning-Based Device Modeling and Performance Optimization for FinFETs

This brief introduces a machine learning based framework to model FinFET’s I-V and C-V curves with artificial neural networks and to further optimize FinFET’s performance on DC and AC characteristics. Our ML-based device model for FinFETs takes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{gs}$ </tex-math></inline-formula> and other nine parameters that define geometry, doping, stress, and work function profile as input variables. Experimental results show that our ML-based device model can predict current and capacitance accurately. Besides, the proposed ML-based performance optimization flow is a promising alternative to the traditional design of experiment method based on technology computer-aided design simulations. Our optimization flow can locate optimized device features accurately and require fewer simulations. Our work demonstrates that ML can perform compact modeling of advanced devices with high accuracy, and the trained ANN models can accelerate performance optimization.