Radiation Hardening Techniques Research Articles

Transistor-Level Radiation Hardening by Design Techniques in Complex Gates

Single Event Transients (SETs) have become a major reliability concern for integrated circuits used in critical applications. Research to improve the radiation robustness of digital circuits has been conducted, assessing all abstraction levels (from the device up to the system). This study evaluates transistor-level radiation-hardened techniques in combinational logic, such as transistor folding, sizing and reordering. In addition, the efficiency of using supergates, including series-parallel and non-series-parallel CMOS structures, to harden the combinational logic is discussed. The dependence of input signals probability on a logic cell susceptibility to SET is assessed. Moreover, a new concept of electrical masking is introduced. The robustness of the investigated logic cells was evaluated regarding their SET rate. The CREME96 tool was used to generate the SET rates, and an electrical model was used to perform particle hit simulations. Obtained results have indicated that modifying the structure of logic gates can substantially improve circuit robustness without necessarily worsening its performance. Besides, using supergates in combinational logic design has demonstrated to be a promising hardening strategy. The most robust supergate implementation of a five-input logic function provided up to [Formula: see text] SET rate reduction regarding an approach based on standard cells, along with lower critical delay ([Formula: see text]) and average power ([Formula: see text]).

A Radiation-Hardened Delay-Locked Loop Applied for Multiple Frequency Ranges

A radiation-hardened delay-locked loop (DLL) applied for multiple frequency ranges is proposed in this paper. Novel and effective radiation-hardened techniques are applied in charge pump (CP) and voltage-controlled delay line (VCDL) to avoid inverted lock error and missing pulses error caused by single-event transient (SET). In order to ensure a wide operation frequency range, a frequency detection module is designed to detect the frequency of input signals and adjust the current source array of VCDL so as to change its delay time. Besides, an accelerate module is designed to reduce the lock time of DLL by providing an extra discharge current. According to the simulation results, the proposed DLL shows good performance when ion strikes occur and can work properly in a wide operation frequency range from 3.7[Formula: see text]GHz to 7.4[Formula: see text]GHz. Also, the proposed accelerate module helps to reduce lock time by 22.2%.

Analysis and Design of a Delay-Locked Loop with Multiple Radiation-hardened Techniques

Analysis and Design of a Delay-Locked Loop with Multiple Radiation-hardened Techniques

ALDO2, a multi-function rad-hard linear regulator for SiPM-based HEP detectors

ALDO2 is a multi-function, adjustable, low dropout linear regulator designed in onsemi I3T80 0.35μm HV CMOS technology for use in HEP detectors that adopt silicon photomultipliers (SiPMs). The chip features four independent regulators, two low voltage channels (max 3.3 V) used to filter and stabilize the power supply of front-end chips, and two HV channels (max 70 V), specifically designed to provide the bias voltage to arrays of SiPMs. Each regulator can be independently shut down and is protected for over-current and over-temperature. The HV regulators also implement a circuit to monitor the bias current of the SiPM arrays, allowing to perform I–V curves and thus to fine-tune the working point of the SiPM arrays during the detector lifetime. The chip adopts radiation hardening techniques and has been fully qualified up to a TID of 20 Mrad, a 1-MeV-equivalent neutron fluence of 1015 cm−2, and with heavy ions up to 40 MeV cm2 mg−1 LET and 1010 cm−2 cumulative fluence. The chip will be installed in two CMS detectors in the HL-LHC phase, the Barrel Timing Detector (BTL) and the High Granularity Calorimeter (HGCAL).

Layout based radiation hardening techniques against single-event transient

The single-event transient (SET) is regarded as one of the critical reliability issues for the soft errors in modern circuit designs, especially at the advanced technology node. To improve the SET robustness of circuits applied in the space environment, two kinds of layout-based radiation hardening techniques, namely split active area (SAA), gapless well and source (GWS), are proposed to reduce the charge collection efficiency from vertical and horizontal direction respectively. The hardening efficiency of different layout configurations is investigated by TCAD simulations and the underlying reasons for pulse width mitigation of SET are elaborated. The results indicate the combination of the two layout techniques is highly recommended in the construction of hardened standard cell library.

A New Scheme of the Low-Cost Multiple-Node-Upset-Tolerant Latch

The single event upset (SEU) in integrated circuit (IC) occurs due to the striking of heavy charged particles. It results in the multiple node upset (MNU) problem frequently, with the scaling down of semiconductor devices. To address this challenge, the radiation hardening by design (RHBD) methods of circuit are required, in addition to the layout and device level radiation hardening techniques. The latch is one of the basic components of logic circuit, and the RHBD method of latch circuit is still an open issue. The Muller C-element (MCE) and/or the dual interlocked storage cell (DICE) based RHBD methods for latch circuit introduce too much area overhead, because of the redundant circuit structures. This work proposes a new design method of the low-cost multiple-node-upset-tolerant latch without the MCE and DICE modules. For the N-Node-Upset-Tolerant latch, the proposed RHBD latch only consists of N input-split inverters, 2N CMOS transmission gates and one Schmidt trigger. The generic design method is discussed, and a quadruple-node-upset-tolerant latch is designed and analyzed as an instance. The simulation results show that the RHBD latches designed by the proposed scheme consume less area and power compared with those previous counterparts.

Radiation-Tolerant All-Digital PLL/CDR with Varactorless LC DCO in 65 nm CMOS

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop (PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications. Several radiation hardening techniques are proposed to achieve state-of-the-art immunity to Single-Event Effects (SEEs) up to 62.5 MeV cm2 mg−1 as well as tolerance to the Total Ionizing Dose (TID) exceeding 1.5 Grad. The LC Digitally Controlled Oscillator (DCO) is implemented without MOS varactors, avoiding the use of a highly SEE sensitive circuit element. The circuit is designed to operate at reference clock frequencies from 40 MHz to 320 MHz or at data rates from 40 Mbps to 320 Mbps and displays a jitter performance of 520 fs with a power dissipation of only 11 mW and an FOM of −235 dB.

Review on Radiation Hardness Assurance by Design, Process and NextGen Devices

Aggressive scaling, shrinking device size and exponential rise in device densityover the past two decades has contributed significantly in improving the power and performance metrics of Integrated Circuit (IC) technology. For specific applications like Space electronics, Implanted Biomedical, Sensor devices etc. drastic scaling has resulted in increasing the susceptibility of the nanoscale circuits to radiation effects. The objective of the paper is to provide an overview of the radiation hardening techniques at various levels of IC design and development, i.e. at Device Structure-Fabrication process (Radiation Hardening by Process) and Circuit and layout design (Radiation Hardening by Design), to mitigate the effects of radiation and improve reliability. The work also presents comparison of next generation device structure that utilize Carbon Nano Tubes (CNTs) and Semiconductor NanoWires (GAA-Si, GaAs, InN) against traditional MOSFET based device structures for operation under the radiation environment.

Applications of Direct-Current Current–Voltage Method to Total Ionizing Dose Radiation Characterization in SOI NMOSFETs with Different Process Conditions

As a promising candidate in space radiation hardened applications, silicon-on-insulator (SOI) devices face the severe problem of total ionizing dose (TID) radiation because of the thick buried oxide (BOX) layer. The direct-current current–voltage (DCIV) method was applied for studying TID radiation of SOI metal–oxide–semiconductor field–effect transistors (MOSFETs) with different manufacture processes. It is found that the peak of high-voltage well (PX) devices shows a larger left-shift and a slower multitude increase along with radiation dose, compared with that of low-voltage well (PV) devices. It is illustrated that the high P-type impurity concentration near back interface makes it more difficult to break up silicon hydrogen bonds, which gives the PX devices superiority in resisting the build-up of interface traps. The study results indicate that increasing doping concentration of the body region near the back-gate interface might be an alternative radiation hardening technique of SOI MOSFET devices to avoid the parasitic back transistors’ leakage.

Evaluating Architectural, Redundancy, and Implementation Strategies for Radiation Hardening of FinFET Integrated Circuits

In this article, authors explore radiation hardening techniques through the design of a test chip implemented in 16-nm FinFET technology, along with architectural and redundancy design space exploration of its modules. Nine variants of matrix multiplication were taped out and irradiated with neutrons. The results obtained from the neutron campaign revealed that the radiation-hardened variants present superior resiliency when either local or global triple modular redundancy (TMR) schemes are employed. Furthermore, simulation-based fault injection was utilized to validate the measurements and to explore the effects of different implementation strategies on failure rates. We further show that the interplay between these different implementation strategies is not trivial to capture and that synthesis optimizations can effectively break assumptions about the effectiveness of redundancy schemes.

Exploiting Transistor Folding Layout as RHBD Technique Against Single-Event Transients

Radiation-hardening techniques can be extensively used in the design level to improve the robustness of very large-scale integration (VLSI) circuits used in space applications. Accordingly, this work analyzes the efficiency of transistor folding layout in improving the single-event transient (SET) robustness of digital circuits. Additionally, diffusion splitting is proposed to reduce the area overhead of multiple-finger designs. Besides increasing threshold linear energy transfer, results show that both techniques can also reduce the overall cross section and the in-orbit SET rate for protons and heavy ions in low-earth orbit (LEO) and international space station (ISS) orbits.

Design and Characterizations of the Radiation-Hardened XCR4C ASIC for X-Ray CCDs for Space Astronomical Applications

Correlated double sampling (CDS) circuits are essential to processing the X-ray charge-coupled devices (CCDs) that have been widely used in the modern X-ray astronomical field. For timing observations, both energy resolution and timing resolution are of great importance. We are developing the XCR4C application-specific integrated circuit (ASIC), which is a fully customized four-channel radiation-hardened CDS ASIC targeting the readout of X-ray CCDs, for future space astronomical missions. The ASIC is implemented in a differential switched-capacitor architecture, making it highly linear, low power, immune to common-mode noise and interferences, as well as easily configurable. To combat the harsh low-earth-orbit space environment, some radiation-hardening techniques are applied, including the process hardening method, even-finger double-side bulk butting, and pseudo-double guard ring layout techniques. The XCR4C ASIC was fabricated with 0.35- $\mu \text{m}$ 2P4M CMOS technology with an epitaxial layer. The ASIC achieves a maximum 23-ppm integral nonlinearity and 5.8 e− rms equivalent noise charge under a typical 1-MHz pixel rate and only consumes 50 mW approximately from a single 3.3-V supply voltage. The results from radiation hardness assurance testing show that the ASIC has at least a total ionizing dose tolerance of 300 krad(Si), and no single-event latchup has been found up to a linear energy transfer of $81.35~\text {MeV}\cdot \text {cm}^{2}$ /mg with a total fluence up to $1.68\times 10^{7}$ ions/cm2.

Mitigation of Single-Event Effects in SiGe-HBT Current-Mode Logic Circuits.

It has been known that negative feedback loops (internal and external) in a SiGe heterojunction bipolar transistors (HBT) DC current mirrors improve single-event transient (SET) response; both the peak transient current and the settling time significantly decrease. In the present work, we demonstrate how radiation hardening by design (RHBD) techniques utilized in DC bias blocks only (current mirrors) can also improve the SET response in AC signal paths of switching circuits (e.g., current-mode logic, CML) without any additional hardening in those AC signal paths. Four CML circuits both with and without RHBD current mirrors were fabricated in 130 nm SiGe HBT technology. Two existing RHBD techniques were employed separately in the current mirrors of the CML circuits: (1) applying internal negative feedback and (2) adding a large capacitor in a sensitive node. In addition, these methods are also combined to analyze the overall SET performance. The single-event transients of the fabricated circuits were captured under the two-photon-absorption laser-induced single-event environment. The measurement data clearly show significant improvements in SET response in the AC signal paths of the CML circuits by using the two radiation hardening techniques applied only in DC current mirrors. The peak output transient current is notably reduced, and the settling time upon a laser strike is shortened significantly.

Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI

This article presents the radiation hardened by design (RHBD) techniques applied to a 15-GHz quadrature subsampling phase-locked loop (PLL) at a sub-50 nm partially depleted silicon-on-insulator technology node. Radiation-hardening techniques are integrated into a subsampling architecture for robust noise and radiation performance. Experimentally validated bias-dependent single-event models are used to characterize the radiation response, and the applicability of existing RHBD techniques to subsampling PLLs is examined. A significant vulnerability introduced in dual-loop architectures such as subsampling is identified and mitigated with a proposed technique. Favorable noise and loop perturbation suppression characteristics of the subsampling architecture are leveraged to develop a high-performance RHBD PLL, maintaining performance specifications comparable to unhardened designs.

Progress on the radiation tolerance of CMOS Monolithic Active Pixel Sensors

CMOS Monolithic Active Pixel Sensors (CPS) are ultra-light and highly granular silicon pixel detectors suited for highly sensitive charged particle tracking. Being manufactured with cost efficient standard CMOS processes, CPS may integrate sensing elements together with analogue and digital data processing circuits into one monolithic chip. This turns into 50 μm thin sensors, which provide an outstanding typical spatial resolution of fewμm and a detection efficiency for minimum ionizing particles above 99.9%. The radiation tolerance of CPS was initially constrained by the limits of the CMOS processes used for their production but has been improved by orders of magnitudes during the last years. This work reviews the related R&D on the radiation tolerance of traditional CPS with partially depleted active medium as pioneered by the MIMOSA-series developed by the IPHC Strasbourg. Procedures for assessing radiation damage in those non-standard pixels are discussed and the major mechanisms of radiation damage are introduced. Techniques for radiation hardening are shown. Moreover, recent results on next generation CPS featuring fully depleted sensors based on improved CMOS processes are summarized.

Design and Characterization of SEU Hardened Circuits for SRAM-Based FPGA

The mitigation of single-event upset (SEU) in SRAM-based field-programmable gate array (FPGA) is increasingly important as utilization and demand for SRAM-based FPGA dramatically increased in radiation environments such as space. As D flip-flop (DFF) and memory [including block random-access memory (BRAM) and configuration random-access memory (CRAM)] are constituted as the key elements in an FPGA, it is fundamentally necessary to develop radiation hardening techniques targeted for enhanced reliability of DFF and memory. A novel SEU hardened memory design for FPGA is proposed with capabilities of multibit upset protection. We further developed two prototype FPGA chips, one with SEU and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process and have a volume of three million equivalent logic gates. In terms of SEU cross section, CRAM in the hardened FPGA design is about four orders of magnitude lower than in the unhardened FPGA design, while BRAM demonstrates a reduction by three orders of magnitude. On the conditions of linear energy transfer being up to 14 MeV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\cdot$ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg, no SEU errors were observed from DFF in the hardened FPGA design.

Heavy-Ion Induced Single Event Upsets in Advanced 65 nm Radiation Hardened FPGAs

The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded RAMs (EBRAMs) and flip-flops. This radiation hardened circuits include large-spacing interlock CRAM cells, area saving debugging logics, the redundant flip-flops cells, and error mitigated 6-T EBRAMs. Heavy ion irradiation test result indicates that the hardened CRAMs had a high linear energy transfer threshold of upset ∼18 MeV/(mg/cm 2 ) with an extremely low saturation cross-section of 6.5 × 10 − 13 cm 2 /bit, and 71% of the upsets were single-bit upsets. The combinational use of triple modular redundancy and check code could decline ∼86.5% upset errors. Creme tools were used to predict the CRAM upset rate, which was merely 8.46 × 10 − 15 /bit/day for the worst radiation environment. The effectiveness of radiation tolerance has been verified by the irradiation and prediction results.

Single Event Upset tests and failure rate estimation for a front-end ASIC adopted in high-flux-particle therapy applications

A 64 channels Application Specific Integrated Circuit, named TERA09, designed in a 0.35 μm technology for particle therapy applications, has been characterized for Single Event Upset probability. TERA09 is a current-to-frequency converter that offers a wide input range, extending from few nA to hundreds of μA, with linearity deviations in the order of a few percent. This device operates as front-end readout electronics for parallel plate ionization chambers adopted in clinical applications. This chip is going to be located beside the monitor chamber, thus not directly exposed to the particle beam. For this reason, no radiation hardening techniques were adopted during the microelectronics design. The intent of the test reported in this paper is to predict the TERA09 upset rate probability in a real application scenario. Due to the fact that TERA09 has an extended digital area with registers and counters, it is interesting to estimate the effect of the secondary neutron field produced during the treatment. The radiation damage test took place at the SIRAD facility of the Italian National Institute for Nuclear Physics in Padova, Italy. The SIRAD facility allows to study the CMOS upset rate as a function of the energy deposited during irradiation. By irradiating the chip with ions of different Linear Energy Transfer, it is possible to calculate the single event effect cross-section as a function of the deposited energy. It resulted that the minimum deposited energy in a CMOS silicon sensitive volume of 1μm3, responsible for a Single Event Upset probability higher than zero, is 690 keV. In the last part of the paper, we calculated the expected upset probability in a typical clinical environment, knowing the fluence of secondary, backward-emitted neutrons. Considering as an example a treatment room located at the CNAO particle therapy center in Pavia, the expected upset rate for TERA09 is ∼102 events/year. Using a redundant and independent monitor chamber, the upset probability expected during one detector readout is lower than 10−24, as explained in the document.

Displacement Damage in Silicon Detectors for High Energy Physics

In this paper, we review the radiation damage issues caused by displacement damage in silicon sensors operating in the harsh radiation environments of high energy physics experiments. The origin and parameterization of the changes in the macroscopic electrical sensor properties such as depletion voltage, leakage current, and charge collection efficiency as a function of fluence of different particles, annealing time, and annealing temperature are reviewed. The impact of impurities in the silicon base crystal on these changes is discussed, revealing their effects on the degradation of the sensor properties. Differences on how segmented and nonsegmented devices are affected and how device engineering can improve radiation hardness are explained and characterization techniques used to study sensor performance and the electric field distribution inside the irradiated devices are outlined. Finally, recent developments in radiation hardening and simulation techniques using technology computer-aided design modeling are given. This paper concludes with radiation damage issues in presently operating experiments and gives an outlook of radiation-hardened technologies to be used in the future upgrades of the Large Hadron Collider and beyond.

SET analysis and radiation hardening techniques for CMOS LNA topologies

This paper analyses the effects of single-event transients (SETs) on CMOS low noise amplifiers (LNA) designed for a 0.18 technology. Two well-known topologies, the common-source and common-gate cascodes, have been analysed when heavy ions strike the most sensitive nodes of these structures. In order to simulate these strikes both a physics-based technology computer aided design (TCAD) tool and an electrical circuit domain simulator have been used. This way the physics information given by the TCAD tool is combined with the fast transient simulations performed in circuit simulators. To study their SET performance, the maximum voltage peak and the recovery time of the output signal were calculated for both LNAs. Additionally, a safe operating area can be defined, setting the boundaries for acceptable SETs. Radiation hardening by design techniques have been applied at the most vulnerable nodes of both LNAs. The proposed mitigation approaches make both LNAs hardened against radiation, considerably improving their SET performance.