Layout based radiation hardening techniques against single-event transient

Abstract

The single-event transient (SET) is regarded as one of the critical reliability issues for the soft errors in modern circuit designs, especially at the advanced technology node. To improve the SET robustness of circuits applied in the space environment, two kinds of layout-based radiation hardening techniques, namely split active area (SAA), gapless well and source (GWS), are proposed to reduce the charge collection efficiency from vertical and horizontal direction respectively. The hardening efficiency of different layout configurations is investigated by TCAD simulations and the underlying reasons for pulse width mitigation of SET are elaborated. The results indicate the combination of the two layout techniques is highly recommended in the construction of hardened standard cell library.