Abstract
Radiation-hardening techniques can be extensively used in the design level to improve the robustness of very large-scale integration (VLSI) circuits used in space applications. Accordingly, this work analyzes the efficiency of transistor folding layout in improving the single-event transient (SET) robustness of digital circuits. Additionally, diffusion splitting is proposed to reduce the area overhead of multiple-finger designs. Besides increasing threshold linear energy transfer, results show that both techniques can also reduce the overall cross section and the in-orbit SET rate for protons and heavy ions in low-earth orbit (LEO) and international space station (ISS) orbits.
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