Mitigation and Predictive Assessment of SET Immunity of Digital Logic Circuits for Space Missions

Ygor Q Aguiar,Vincent Pouget,Antoine D Touboul,Frédéric Saigné,Paul Leroux,Jean-Luc Autran,Frédéric Wrobel

doi:10.3390/aerospace7020012

Abstract

Due to the intrinsic masking effects of combinational circuits in digital designs, Single-Event Transient (SET) effects were considered irrelevant compared to the data rupture caused by Single-Event Upset (SEU) effects. However, the importance of considering SET in Very-Large-System-Integration (VLSI) circuits increases given the reduction of the transistor dimensions and the logic data path depth in advanced technology nodes. Accordingly, the threat of SET in electronics systems for space applications must be carefully addressed along with the SEU characterization. In this work, a systematic prediction methodology to assess and improve the SET immunity of digital circuits is presented. Further, the applicability to full-custom and cell-based design methodologies are discussed, and an analysis based on signal probability and pin assignment is proposed to achieve a more application-efficient SET-aware optimization of synthesized circuits. For instance, a SET-aware pin assignment can provide a reduction of 37% and 16% on the SET rate of a NOR gate for a Geostationary Orbit (GEO) and the International Space Station (ISS) orbit, respectively.

Highlights

Within the advancements of technology process, an increased susceptibility to radiation effects is observed in deeply scaled Complementary Metal-Oxide Semiconductor (CMOS) transistors [1].Energetic particles present in harsh environments, such as in space or in the Earth’s atmosphere, can induce physical and functional damage to electronics systems in space missions
Single-Event Upset (SEU) have been vastly studied in the literature while Single-Event Transient (SET) were not given important attention due to the intrinsic masking effects of combinational logic circuits [2]
MC-Oracle is a Monte Carlo simulation code developed to analyze the SEU/SET immunity of electronics based on the particle interaction physics within the sensitive devices

Summary

Introduction

Within the advancements of technology process, an increased susceptibility to radiation effects is observed in deeply scaled Complementary Metal-Oxide Semiconductor (CMOS) transistors [1].Energetic particles present in harsh environments, such as in space or in the Earth’s atmosphere, can induce physical and functional damage to electronics systems in space missions. Single-Event Effects (SEEs) are a group of destructive and nondestructive effects originating from a single particle hit in electronic devices. When a single particle hits a memory element, such as a Static Random-Access. Memory (SRAM) or flip-flops, and it changes the stored bit value, a so-called Single-Event Upset (SEU). If the particle hits a combinational logic circuitry, a parasitic transient is observed in the circuit node characterizing a Single-Event Transient (SET). SEUs have been vastly studied in the literature while SETs were not given important attention due to the intrinsic masking effects of combinational logic circuits [2]. There are three main masking effects inherent in digital circuits: (i) Electrical masking, in which the transient pulse is not able to propagate through a logic path due to electrical losses and attenuation of its amplitude; (ii) logical masking, in which a SET will

Methods

Results

Conclusion