Abstract
The 65 nm Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) was designed and manufactured, which employed tradeoff radiation hardening techniques in Configuration RAMs (CRAMs), Embedded RAMs (EBRAMs) and flip-flops. This radiation hardened circuits include large-spacing interlock CRAM cells, area saving debugging logics, the redundant flip-flops cells, and error mitigated 6-T EBRAMs. Heavy ion irradiation test result indicates that the hardened CRAMs had a high linear energy transfer threshold of upset ∼18 MeV/(mg/cm 2 ) with an extremely low saturation cross-section of 6.5 × 10 − 13 cm 2 /bit, and 71% of the upsets were single-bit upsets. The combinational use of triple modular redundancy and check code could decline ∼86.5% upset errors. Creme tools were used to predict the CRAM upset rate, which was merely 8.46 × 10 − 15 /bit/day for the worst radiation environment. The effectiveness of radiation tolerance has been verified by the irradiation and prediction results.
Highlights
Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) possesses plenty of flexible configuration switches and logics to implement million-gate circuits with a very short development time [1,2], which makes it a valuable Integrated Circuit (IC) for an electronic system
Redundancy (TMR) and Dual Interlocked storage Cell (DICE) that can be used in FPGAs, but they are area or power consuming and less effective when the Multiple Bit Upset (MBU) phenomenon occurs frequently [2]
Layout hardening including DICE hardened Configuration RAMs (CRAMs), 8-T hardened Debugging Logics (DLs), and double redundant DFF aimed at reducing the SEU sensitivity and system errors, while the configuration hardening was more flexible and applicable to secondarily significant parts such as 6-T Embedded RAMs (EBRAMs)
Summary
Static Random Access Memory (SRAM) based Field Programmable Gate Array (FPGA) possesses plenty of flexible configuration switches and logics to implement million-gate circuits with a very short development time [1,2], which makes it a valuable Integrated Circuit (IC) for an electronic system. The Complementary Metal Oxide Semiconductor (CMOS) based architectures in SRAM-FPGA are very sensitive to radiation effects, which reduces the on-orbit safety and reliability [3,4,5,6,7,8,9]. It is necessary to evaluate and mitigate the Single Event Effects (SEEs) of SRAM-based FPGAs for potential space applications. There have been some radiation hardened SRAM-based FPGAs such as XQVR300 (220 nm) and XQR4VSX55 (90 nm) employed for space mission, a fast system scrubbing is still required to reduce the on-orbit risks [7]. Different circuit blocks in an FPGA have different functions and importance
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