Low-power Techniques Research Articles

Neuromorphic System for Spatial and Temporal Information Processing

Neuromorphic systems that learn and predict from streaming inputs hold significant promise in pervasive edge computing and its applications. In this paper, a neuromorphic system that processes spatio-temporal information on the edge is proposed. Algorithmically, the system is based on hierarchical temporal memory that inherently offers online learning, resiliency, and fault tolerance. Architecturally, it is a full custom mixed-signal design with an underlying digital communication scheme and analog computational modules. Therefore, the proposed system features reconfigurability, real-time processing, low power consumption, and low-latency processing. The proposed architecture is benchmarked to predict on real-world streaming data. The network's mean absolute percentage error on the mixed-signal system is 1.129X lower compared to its baseline algorithm model. This reduction can be attributed to device non-idealities and probabilistic formation of synaptic connections. We demonstrate that the combined effect of Hebbian learning and network sparsity also plays a major role in extending the overall network lifespan. We also illustrate that the system offers 3.46X reduction in latency and 77.02X reduction in power consumption when compared to a custom CMOS digital design implemented at the same technology node. By employing specific low power techniques, such as clock gating, we observe 161.37X reduction in power consumption.

Design and Analysis of Multipliers using Radix-8 Booth Encoding Technique for Low Power and Area Consumption

As innovation scaling is arriving at its points of confinement, new methodologies have been proposed for computational efficiency. Different techniques have been proposed with advancements in technology to model high-speed along with low power consumption and smaller area multipliers. For the radix-4 booth propagation algorithm for low-power and low complexity applications, an efficient approximate 8 bit redundant multiplier is used. To minimize the complication present in modified booth encoder, approximate Booth RB encoders have been introduced by modifying the truth table with incorrect bits, which resulted in a reduction of the power delay product. Approximate computing is a relevant technique for low power and high performance circuits as used in error-tolerant applications. Approximate or inexact computing is an attractive design methodology for low power design but accomplished by loosening up the necessity of precision. It becomes critical to maintain full accuracy to attain reduced power utilization. In this paper, the design of approximate redundant binary (RB) multipliers is studied and modified to build less complex multiplier with Radix-8 modified booth encoding technique to reduce area and complexities of architectures.

Implementation of Leakage Power Reduction Techniques in Field Programmable Device

This paper provide a summary of low-power technique for field-programmable gate arrays (FPDs). It cover system level propose technique as well as device level propose methods that have besieged present trade devices. In addition to describe present investigate happening circuit level as well as architecture-level create technique. Current studies on power model as well as on low-power computer-aided design (CAD) are also information. At last, it proposes that would allow the use of Field Programmable Device (FPD) equipment in applications where power and energy consumption is critical, such as mobile devices.

Microplasma direct writing for site-selective surface functionalization of carbon microelectrodes

Carbon micro- and nanoelectrodes fabricated by carbon microelectromechanical systems (carbon MEMS) are increasingly used in various biosensors and supercapacitor applications. Surface modification of as-produced carbon electrodes with oxygen functional groups is sometimes necessary for biofunctionalization or to improve electrochemical properties. However, conventional surface treatment methods have a limited ability for selective targeting of parts of a surface area for surface modification without using complex photoresist masks. Here, we report microplasma direct writing as a simple, low-cost, and low-power technique for site-selective plasma patterning of carbon MEMS electrodes with oxygen functionalities. In microplasma direct writing, a high-voltage source generates a microplasma discharge between a microelectrode tip and a target surface held at atmospheric pressure. In our setup, water vapor acts as an ionic precursor for the carboxylation and hydroxylation of carbon surface atoms. Plasma direct writing increases the oxygen content of an SU-8-derived pyrolytic carbon surface from ~3 to 27% while reducing the carbon-to-oxygen ratio from 35 to 2.75. Specifically, a microplasma treatment increases the number of carbonyl, carboxylic, and hydroxyl functional groups with the largest increase observed for carboxylic functionalities. Furthermore, water microplasma direct writing improves the hydrophilicity and the electrochemical performance of carbon electrodes with a contact-angle change from ~90° to ~20°, a reduction in the anodic peak to cathodic peak separation from 0.5 V to 0.17 V, and a 5-fold increase in specific capacitance from 8.82 mF∙cm−2 to 46.64 mF∙cm−2. The plasma direct-writing technology provides an efficient and easy-to-implement method for the selective surface functionalization of carbon MEMS electrodes for electrochemical and biosensor applications.

A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.

Single low‐gain amplifier compensated hybrid delta‐sigma modulator

This article presents low-power circuit design techniques to achieve third-order noise shaping by employing multiple stages of passive switched-capacitor gain-boosted integrator and a passive switched-capacitor integrator. First integrator is a passive switched-capacitor for higher linearity. Second integrator is a three-stage passive switched-capacitor gain-boosted integrator to provide passive gain to the loop filter as well as the second DAC feedback. While the third integrator is a two-stage passive switched-capacitor gain-boosted integrator to provide passive gain as well as third DAC feedback for higher stability. Multiple lower stages of passive switched-capacitor gain-boosted integrators employed to enhance the noise shaping order of the modulator and suppress the parasitic effect. The preamplifier is the only active block, while the dynamic comparator used as single-bit quantiser. The complete transistor level with thermal noise simulation can achieve 84 dB of dynamic range (DR), 78.2 dB signal-to-noise-plus-distortion ratio (SNDR), and 78.5 dB signal-to-noise ratio (SNR) for 500 Hz signal bandwidth. It can also achieve signal-to-spurious-free dynamic range (SFDR) of 78.2 dB with estimated power consumption of 220 nW at 1 V supply voltage in SMIC 28 nm CMOS Technology. Finally, it can achieve state-of-the-art Walden Figure-of- Merit (FoM W ) of 33 fJ/Conv-Step and Schreier FoM S of 171.2 dB.

A low-power, low-noise, high-accurate epileptic-seizure detection system for wearable applications

This paper presents a low-power epileptic-seizure-detection-system (ESDS), including an instrumentational-amplifier (IA), a level-detection-ADC (LD-ADC) and frequency-detection-units (FDUs). In the proposed ESDS, by utilizing low-power techniques, and a new mixed-mode detection-system, the power is reduced to 2 μW. Also, by using large input capacitors and a high-pass-filter (HPF), the electrode-offset-voltage (EOV) is rejected. Hence, the supply voltage is reduced without saturating the input transistors. In the IA, by using the choppers, the input-referred-noise is obtained 0.96 μVrms over 0.5–100 Hz. Also, to avoid signal attenuation, an impedance-boosting-loop (IBL) is used to increase the input impedance up to 18.2 GΩ at 10 Hz. After amplifying the EEG signals, the LD-ADC and FDUs are utilized to detect the amplitudes and activities of the EEG signals. In the proposed ESDS, by using a PGA with variable-gain, a LD-ADC with variable sampling-frequency and FDUs with variable reset-time, the sensitivity is increased up to 100% with the latency of 8.8 s. Besides, a compatible ESDS with different low-voltage fast-activity epileptic-seizures is achieved.

SmarTEG: An Autonomous Wireless Sensor Node for High Accuracy Accelerometer-Based Monitoring.

We report on a self-sustainable, wireless accelerometer-based system for wear detection in a band saw blade. Due to the combination of low power hardware design, thermal energy harvesting with a small thermoelectric generator (TEG), an ultra-low power wake-up radio, power management and the low complexity algorithm implemented, our solution works perpetually while also achieving high accuracy. The onboard algorithm processes sensor data, extracts features, performs the classification needed for the blade’s wear detection, and sends the report wirelessly. Experimental results in a real-world deployment scenario demonstrate that its accuracy is comparable to state-of-the-art algorithms executed on a PC and show the energy-neutrality of the solution using a small thermoelectric generator to harvest energy. The impact of various low-power techniques implemented on the node is analyzed, highlighting the benefits of onboard processing, the nano-power wake-up radio, and the combination of harvesting and low power design. Finally, accurate in-field energy intake measurements, coupled with simulations, demonstrate that the proposed approach is energy autonomous and can work perpetually.

Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators

This paper proposes a new design methodology to explore the state-of-the-art approximate adders for accelerator architectures conceived in the realm of multiplier-less multiple constant multiplication optimization problem. The proposed methodology is composed of: 1) a search heuristic to seek faster and feasible approximate configurations for the architectures under evaluation; 2) low-power techniques regarding hybrid approximate adders design for accelerators based on trees of shift-and-add operations; 3) high-performance evaluation by exploring parallel prefix adders and low power analysis through the use of the adder optimized by a commercial synthesis tool in the precise part of the approximate adders; and 4) energy efficiency analysis by considering both the approximate techniques and voltage over scaling estimation. Furthermore, improvements are proposed for the state-of-the-art approximate adders under evaluation in this paper. Two case studies are considered to assess the proposed methodology: 1) Gaussian image filter and 2) Sobel operator. The precise and approximate image filters were described in very high-speed integrated circuits hardware description language regarding the proposed methodology. Results are shown after synthesis to a 45-nm standard cell-based technology, where energy reductions ranging from 7.7% up to 73.2% were experienced for multiple levels of quality considering the applications under analysis.

Charge-Recycling-Based Redundant Write Prevention Technique for Low-Power SOT-MRAM

In spin–orbit torque magnetic random access memory (SOT-MRAM), as write energy is much larger than read energy, writing data to memory only when the new data is different from the stored data can lead to considerable write energy savings. In this paper, we propose three low-power techniques that can significantly reduce write energy in the read–compare–write process. In the proposed approaches, redundant charge in read operation has been efficiently reused to generate a negative voltage for write assistance, which leads to short write time. A selective precharging technique is also proposed to minimize the voltage swings between read and write operations. In addition, asymmetric write current due to source degeneration of write transistor can be resolved with the write voltage suppression scheme. Our circuit simulations with 65-nm CMOS technology show that when the stored data and new data are the same, up to 61% of write energy savings have been achieved compared with the conventional 2T-1MTJ cell. When the proposed SOT-MRAM is used as L3 caches of X86 processor, the gem5 simulations also show that average 48.2% of write energy savings can be achieved in various workloads of SPEC2006.

A Review On Modified Gate Diffusion Input Logic: An Approach For Area And Power Efficient Digital System Design

In recent days, the main motto of VLSI designers is to reduce the power and area as devices are becoming battery-operated, compact and require enhanced functionality and features. Due to the scaling and shrinking of devices, the transistor leakage power has increased at an exponential rate. In this paper, analysis on the research based on the Modified gate diffusion input technique (m-GDI) which has gained much attention in recent days are encompassed. Consequently, 31 research papers homologous to m-GDI technique are assessed and analysed based on the numerous targets. In this review, we present the m-GDI Technique, a low power technique and scrutinize the modern breakthroughs with several pros and cons. The thorough examination is done on finding the inclusion of the issues, methodologies, simulation tools and technologies used.

Edge Computing: A Survey On the Hardware Requirements in the Internet of Things World

In today’s world, ruled by a great amount of data and mobile devices, cloud-based systems are spreading all over. Such phenomenon increases the number of connected devices, broadcast bandwidth, and information exchange. These fine-grained interconnected systems, which enable the Internet connectivity for an extremely large number of facilities (far beyond the current number of devices) go by the name of Internet of Things (IoT). In this scenario, mobile devices have an operating time which is proportional to the battery capacity, the number of operations performed per cycle and the amount of exchanged data. Since the transmission of data to a central cloud represents a very energy-hungry operation, new computational paradigms have been implemented. The computation is not completely performed in the cloud, distributing the power load among the nodes of the system, and data are compressed to reduce the transmitted power requirements. In the edge-computing paradigm, part of the computational power is moved toward data collection sources, and, only after a first elaboration, collected data are sent to the central cloud server. Indeed, the “edge” term refers to the extremities of systems represented by IoT devices. This survey paper presents the hardware architectures of typical IoT devices and sums up many of the low power techniques which make them appealing for a large scale of applications. An overview of the newest research topics is discussed, besides a final example of a complete functioning system, embedding all the introduced features.

Powering Batteryless Embedded Platforms by Piezoelectric Transducers: A Pilot Study

This contribution presents a pilot study on powering battery-less embedded systems. First, a piezoelectric transducer principle and low-power techniques are reviewed in the background section. In the experimental part, the authors describe a testing setup consisting of piezoelectric transducer, DC/DC converter with energy storage, and evaluation microcontroller platform (FRDM KL25Z). Three types of experiments have been conducted for two voltage configurations including charging speed, continuous operation and discharge test. Results presented in this article concentrate on power supply voltage (1.8 V and 3.3 V), total efficiency (67.16 % and 76.75 %) and operation times (24.28 s and 15 s) of the embedded system. DOI: 10.5755/j01.eie.25.2.23201

RETRACTED: Content addressable memory as a teaching aid for low-power technique study

This article builds the confidence for undergraduate electrical/electronic engineering students in low-power very-large-scale integration by presenting a simple technique for enhancing the performance of precomputation-based content addressable memory. The proposed precomputation method provides minimal power consumption and has enhanced speed than the existing design. Experimental results were obtained using the cadence virtuoso 90 nm. The paper provides hands-on teaching in the basics of content addressable memory and low-power very-large-scale integration technique, stimulates students’ interest in very-large-scale integration, and scrutinizes pros and cons of different circuit choices.

Research of Fall Detection and Fall Prevention Technologies: A Systematic Review

Falls are abnormal activity events that occur infrequently; however, they are serious health problems among elderly individuals. With the advancements of technologies, falls have been widely studied by scientific researchers to minimize serious consequences and negative impacts. Fall detection and fall prevention are two strategies to tackle fall issues with a variety of sensing techniques and classifier models. Currently, many reviews on fall-related technologies have been presented and analyzed; however, most of them give surveys on the subfield of fall-related systems, while others are not extensive and comprehensive reviews. In fact, the latest researches have a new trend of fusion-based methods to improve the performance of the fall-related systems based on a combination of different sensors or classifier models. Adaptive threshold and radio frequency-based systems are also researched and proposed recently, which are seldom mentioned in other reviews. Therefore, a global taxonomy for current fall-related studies from four aspects, including current literature reviews, fall detection, and prevention systems based on different sensor apparatus and analytic algorithm, low power techniques, and sensor placements for fall-related systems are conducted in this paper. Several research challenges and issues in the fall-related field are also discussed and analyzed. The objective of this review paper is to conclude and provide a good position of current fall-related studies to inspire researchers in this field.

High Performance Reversible Direct Data Synthesizer for Radio Frequency Applications

Design of Reversible logic gate enabled Reconfigurable Direct digital synthesizer is evaluated here. The need for Direct Digital Synthesizers (DDS) inherently finds application in the area of radio frequency communication. DDS is a method of producing an analog waveform—usually a sine wave—by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. The proposed design presents an important analysis based on Reversible logic gates for the application of DDS which is a powerful device employed to produce standard signal sweeps from lowest frequency to highest frequency. The sweeps of DDS frequency depends on the configurable frequency words produced by high speed Field Programmable Gate Array (FPGA) platforms. Because operations within DDS devices are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little power. Here the proposed system focuses on development of DDS through Artificial Intelligence (AI) with Field Programmable Gate Array (FPGA) devices. The primary need for FPGA and AI combination provides the replacement of analog Phase Locked Loop (PLL) in traditional DDS circuits. The fully digital architecture enable the system able to configure the digital PLL developed inside the FPGA core. Low noise and Low power factor is being achieved through low power techniques utilized in the architecture development part. The proposed system increase the sweep frequency resolution, Reverse fluctuations through leakage voltage etc.

More Precise FPGA Power Estimation and Validation Tool (FPEV_Tool) for Low Power Applications

This paper provides a significant approach for designing the more accurate power estimation and validation models over the existing power estimation models given in the literature. It is well established that one of the existing power estimation models is not able to accurately estimate the power of the designs incorporated with low power techniques like clock enable. In this paper, an improvement over the existing power estimation model has been suggested termed as FPEV_Tool. This tool is accurately estimating the power of both types of digital circuits i.e. designs with clock enable and without clock enable specifically, with an average error of approximately 3% and peak error of 17%, respectively. The accuracy of the proposed tool is validated using Xpower Analyzer available for power analysis in Xilinx ISE and existing model given in the literature by Deng et al. This tool helps researchers to validate and compare their results with the results of existing models and commercial tools available in the market. This tool also provides a new move toward the power estimation and validation to the researchers those are working in the field of low power digital circuit design.

A System-Level Correction SAR ADC with Noise-Tolerant Technique

A system-level correction successive approximation register analog-to-digital converter (SAR ADC) with regulated comparator of noise-tolerant technique is proposed. First, a substrate voltage boost technique is provided to improve the linearity and speed of sampling switch. Secondly, the proposed SAR ADC provides a comparator of noise regulation without redundant comparison cycle. The proposed comparator would be regulated in high-speed large noise state in large input differential signals. In the condition of small input differential signals, the comparator would be adjusted to low-speed small noise state. Furthermore, a high-speed low-power technique is proposed to optimize the performance of dynamic comparator. Additionally, a fast SAR logic structure is provided to increase the conversion speed of SAR ADC. To demonstrate the proposed techniques, a design example of SAR ADC is fabricated in 65[Formula: see text]nm CMOS technology. The SAR ADC is able to tolerate about 1.1 LSB noise errors in post-simulation with the operation state regulated automatically. The core occupies an active area of only 0.025[Formula: see text]mm2 and consumes 1.5[Formula: see text]mW. Measurement results achieve SFDR [Formula: see text][Formula: see text]dB and SNDR [Formula: see text][Formula: see text]dB, resulting in the FOM of 21.6[Formula: see text]fJ per conversion step.

60 Gbps 4-PAM VCSEL-based Raman assisted hyper-scale data centre: In context of spectral efficiency and reach extension

Abstract Cost effective large-scale installation of hyper-scale data centres has attracted extensive research recently, due to the exponential bandwidth demand over extended reach. Low cost, power and spectral efficient techniques for increasing network capacity, as well as extending the transmission reach while maintaining duplex connectivity are still key challenges facing current big data networks such as hyper-scale data centre networks. In this work, a low cost energy efficient technique for maximizing carrier spectral efficiency and extending transmission reach is experimentally demonstrated. This is achieved through combined adoption of vertical cavity surface emitting lasers (VCSELs), four level pulse amplitude modulation (4-PAM), dense wavelength division multiplexing (DWDM) and Raman amplification. Three class 10 G VCSEL channels are directly modulated with a 20 Gbps 4-PAM data signal therefore maximizing carrier spectral efficiency by doubling the data rate per channel. The channels are then converged to a single fibre link through DWDM technique at 0.4 nm spacing, achieving a total aggregated data rate of 60 (3 × 20) Gbps. By exploiting the 8.6 dB flat gain of a forward Raman pump, a 77.12 km of standard single mode fibre (SMF) transmission is experimentally achieved. To the best of our knowledge, this is the longest error free fibre transmission distance reported using VCSEL-based 60 Gbps 4-PAM, without any forward error correction (FEC), equalization and pre-emphasis mechanisms. Results show that a real time uncorrected BER

Low Power Ultra-Wideband VCRO in 130nm CMOS Technology

The development of voltage-controlled oscillator (VCO) that can operate at high performance within the ultra-wideband (UWB) frequency with low power consumption is useful for the future device implementation in communication system. This paper presents a design of low power ultra-wideband voltage-controlled ring-oscillator (VCRO) in 130 nm complementary metal-oxide-semiconductor (CMOS) technology with single-ended differential pair architecture for UWB application. The aim of this project is to optimize the VCRO with low power technique to ensure it consumes less power and able to operate within the UWB frequency. All design architecture, schematic and layout and simulation and analysis are implemented using Cadence Tool in 130 nm CMOS technology. Through simulation and analysis process, this VCRO achieved a wider frequency from 7.186 GHz to 9.651 GHz with lowest power consumption of 0.78 mW. This VCRO has tuning range of 25.54%. The output noise and figure of merit (FOM) at 1 MHz offset frequency is -153.1 dBc/Hz and -234.83 dBc/Hz while at a 10 MHz offset frequency, the output noise and FOM is -162.0 dBc/Hz and -223.73 dBc/Hz respectively. Through overall analysis, it can be conclude that this VCRO has better performance compared to previous work in terms of power consumption, output noise and frequency tuning range.